| inst_queue.hh (8737:770ccf3af571) | inst_queue.hh (9184:a1a8f137b796) |
|---|---|
| 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 412 unchanged lines hidden (view full) --- 421 unsigned numPhysIntRegs; 422 423 /** The number of floating point registers in the CPU. */ 424 unsigned numPhysFloatRegs; 425 426 /** Delay between commit stage and the IQ. 427 * @todo: Make there be a distinction between the delays within IEW. 428 */ | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 412 unchanged lines hidden (view full) --- 421 unsigned numPhysIntRegs; 422 423 /** The number of floating point registers in the CPU. */ 424 unsigned numPhysFloatRegs; 425 426 /** Delay between commit stage and the IQ. 427 * @todo: Make there be a distinction between the delays within IEW. 428 */ |
| 429 unsigned commitToIEWDelay; | 429 Cycles commitToIEWDelay; |
| 430 431 /** Is the IQ switched out. */ 432 bool switchedOut; 433 434 /** The sequence number of the squashed instruction. */ 435 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 436 437 /** A cache of the recently woken registers. It is 1 if the register --- 101 unchanged lines hidden --- | 430 431 /** Is the IQ switched out. */ 432 bool switchedOut; 433 434 /** The sequence number of the squashed instruction. */ 435 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 436 437 /** A cache of the recently woken registers. It is 1 if the register --- 101 unchanged lines hidden --- |