inst_queue.hh (10510:7e54a9a9f6b2) inst_queue.hh (10511:e57f5bffc553)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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432 unsigned numEntries;
433
434 /** The total number of instructions that can be issued in one cycle. */
435 unsigned totalWidth;
436
437 /** The number of physical registers in the CPU. */
438 unsigned numPhysRegs;
439
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 423 unchanged lines hidden (view full) ---

432 unsigned numEntries;
433
434 /** The total number of instructions that can be issued in one cycle. */
435 unsigned totalWidth;
436
437 /** The number of physical registers in the CPU. */
438 unsigned numPhysRegs;
439
440 /** Number of instructions currently in flight to FUs */
441 int wbOutstanding;
442
440 /** Delay between commit stage and the IQ.
441 * @todo: Make there be a distinction between the delays within IEW.
442 */
443 Cycles commitToIEWDelay;
444
445 /** The sequence number of the squashed instruction. */
446 InstSeqNum squashedSeqNum[Impl::MaxThreads];
447

--- 102 unchanged lines hidden --- 		443 /** Delay between commit stage and the IQ.
444 * @todo: Make there be a distinction between the delays within IEW.
445 */
446 Cycles commitToIEWDelay;
447
448 /** The sequence number of the squashed instruction. */
449 InstSeqNum squashedSeqNum[Impl::MaxThreads];
450

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