1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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183 */
184 void insertBarrier(DynInstPtr &barr_inst);
185
186 /** Returns the oldest scheduled instruction, and removes it from
187 * the list of instructions waiting to execute.
188 */
189 DynInstPtr getInstToExecute();
190
191 /** Returns a memory instruction that was referred due to a delayed DTB
192 * translation if it is now ready to execute.
193 */
194 DynInstPtr getDeferredMemInstToExecute();
195
196 /**
197 * Records the instruction as the producer of a register without
198 * adding it to the rest of the IQ.
199 */
200 void recordProducer(DynInstPtr &inst)
201 { addToProducers(inst); }
202
203 /** Process FU completion event. */

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237 void completeMemInst(DynInstPtr &completed_inst);
238
239 /**
240 * Defers a memory instruction when its DTB translation incurs a hw
241 * page table walk.
242 */
243 void deferMemInst(DynInstPtr &deferred_inst);
244
245 /** Indicates an ordering violation between a store and a load. */
246 void violation(DynInstPtr &store, DynInstPtr &faulting_load);
247
248 /**
249 * Squashes instructions for a thread. Squashing information is obtained
250 * from the time buffer.
251 */
252 void squash(ThreadID tid);

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303 /** List of instructions that are ready to be executed. */
304 std::list<DynInstPtr> instsToExecute;
305
306 /** List of instructions waiting for their DTB translation to
307 * complete (hw page table walk in progress).
308 */
309 std::list<DynInstPtr> deferredMemInsts;
310
311 /**
312 * Struct for comparing entries to be added to the priority queue.
313 * This gives reverse ordering to the instructions in terms of
314 * sequence numbers: the instructions with smaller sequence
315 * numbers (and hence are older) will be at the top of the
316 * priority queue.
317 */
318 struct pqCompare {

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