1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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89 DynInstPtr inst;
90
91 /** Index of the FU used for executing. */
92 int fuIdx;
93
94 /** Pointer back to the instruction queue. */
95 InstructionQueue<Impl> *iqPtr;
96
97 bool freeFU;
98
99 public:
100 /** Construct a FU completion event. */
101 FUCompletion(DynInstPtr &_inst, int fu_idx,
102 InstructionQueue<Impl> *iq_ptr);
103
104 virtual void process();

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113 ~InstructionQueue();
114
115 /** Returns the name of the IQ. */
116 std::string name() const;
117
118 /** Registers statistics. */
119 void regStats();
120
121 void resetState();
122
123 /** Sets CPU pointer. */
124 void setCPU(FullCPU *_cpu) { cpu = _cpu; }
125
126 /** Sets active threads list. */
127 void setActiveThreads(std::list<unsigned> *at_ptr);
128
129 /** Sets the IEW pointer. */
130 void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
131
132 /** Sets the timer buffer between issue and execute. */
133 void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
134
135 /** Sets the global time buffer. */
136 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
137
138 void switchOut();
139
140 void takeOverFrom();
141
142 bool isSwitchedOut() { return switchedOut; }
143
144 /** Number of entries needed for given amount of threads. */
145 int entryAmount(int num_threads);
146
147 /** Resets max entries for all threads. */
148 void resetEntries();
149

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168 /** Inserts a new, non-speculative instruction into the IQ. */
169 void insertNonSpec(DynInstPtr &new_inst);
170
171 /** Inserts a memory or write barrier into the IQ to make sure
172 * loads and stores are ordered properly.
173 */
174 void insertBarrier(DynInstPtr &barr_inst);
175
176 DynInstPtr getInstToExecute();
177
178 /**
179 * Records the instruction as the producer of a register without
180 * adding it to the rest of the IQ.
181 */
182 void recordProducer(DynInstPtr &inst)
183 { addToProducers(inst); }

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271
272 //////////////////////////////////////
273 // Instruction lists, ready queues, and ordering
274 //////////////////////////////////////
275
276 /** List of all the instructions in the IQ (some of which may be issued). */
277 std::list<DynInstPtr> instList[Impl::MaxThreads];
278
279 std::list<DynInstPtr> instsToExecute;
280
281 /**
282 * Struct for comparing entries to be added to the priority queue. This
283 * gives reverse ordering to the instructions in terms of sequence
284 * numbers: the instructions with smaller sequence numbers (and hence
285 * are older) will be at the top of the priority queue.
286 */
287 struct pqCompare {
288 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
289 {
290 return lhs->seqNum > rhs->seqNum;
291 }
292 };
293

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390 /** The number of floating point registers in the CPU. */
391 unsigned numPhysFloatRegs;
392
393 /** Delay between commit stage and the IQ.
394 * @todo: Make there be a distinction between the delays within IEW.
395 */
396 unsigned commitToIEWDelay;
397
398 bool switchedOut;
399
400 /** The sequence number of the squashed instruction. */
401 InstSeqNum squashedSeqNum[Impl::MaxThreads];
402
403 /** A cache of the recently woken registers. It is 1 if the register
404 * has been woken up recently, and 0 if the register has been added
405 * to the dependency graph and has not yet received its value. It

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457 /** Stat for number of squashed instruction operands examined when
458 * squashing.
459 */
460 Stats::Scalar<> iqSquashedOperandsExamined;
461 /** Stat for number of non-speculative instructions removed due to a squash.
462 */
463 Stats::Scalar<> iqSquashedNonSpecRemoved;
464
465 Stats::VectorDistribution<> queueResDist;
466 Stats::Distribution<> numIssuedDist;
467 Stats::VectorDistribution<> issueDelayDist;
468
469 Stats::Vector<> statFuBusy;
470// Stats::Vector<> dist_unissued;
471 Stats::Vector2d<> statIssuedInstType;
472
473 Stats::Formula issueRate;
474// Stats::Formula issue_stores;
475// Stats::Formula issue_op_rate;
476 Stats::Vector<> fuBusy; //cumulative fu busy
477
478 Stats::Formula fuBusyRate;
479};
480
481#endif //__CPU_O3_INST_QUEUE_HH__