1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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89 DynInstPtr inst;
90
91 /** Index of the FU used for executing. */
92 int fuIdx;
93
94 /** Pointer back to the instruction queue. */
95 InstructionQueue<Impl> *iqPtr;
96
97 /** Should the FU be added to the list to be freed upon
98 * completing this event.
99 */
100 bool freeFU;
101
102 public:
103 /** Construct a FU completion event. */
104 FUCompletion(DynInstPtr &_inst, int fu_idx,
105 InstructionQueue<Impl> *iq_ptr);
106
107 virtual void process();

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116 ~InstructionQueue();
117
118 /** Returns the name of the IQ. */
119 std::string name() const;
120
121 /** Registers statistics. */
122 void regStats();
123
124 /** Resets all instruction queue state. */
125 void resetState();
126
127 /** Sets CPU pointer. */
128 void setCPU(FullCPU *_cpu) { cpu = _cpu; }
129
130 /** Sets active threads list. */
131 void setActiveThreads(std::list<unsigned> *at_ptr);
132
133 /** Sets the IEW pointer. */
134 void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
135
136 /** Sets the timer buffer between issue and execute. */
137 void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
138
139 /** Sets the global time buffer. */
140 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
141
142 /** Switches out the instruction queue. */
143 void switchOut();
144
145 /** Takes over execution from another CPU's thread. */
146 void takeOverFrom();
147
148 /** Returns if the IQ is switched out. */
149 bool isSwitchedOut() { return switchedOut; }
150
151 /** Number of entries needed for given amount of threads. */
152 int entryAmount(int num_threads);
153
154 /** Resets max entries for all threads. */
155 void resetEntries();
156

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175 /** Inserts a new, non-speculative instruction into the IQ. */
176 void insertNonSpec(DynInstPtr &new_inst);
177
178 /** Inserts a memory or write barrier into the IQ to make sure
179 * loads and stores are ordered properly.
180 */
181 void insertBarrier(DynInstPtr &barr_inst);
182
183 /** Returns the oldest scheduled instruction, and removes it from
184 * the list of instructions waiting to execute.
185 */
186 DynInstPtr getInstToExecute();
187
188 /**
189 * Records the instruction as the producer of a register without
190 * adding it to the rest of the IQ.
191 */
192 void recordProducer(DynInstPtr &inst)
193 { addToProducers(inst); }

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281
282 //////////////////////////////////////
283 // Instruction lists, ready queues, and ordering
284 //////////////////////////////////////
285
286 /** List of all the instructions in the IQ (some of which may be issued). */
287 std::list<DynInstPtr> instList[Impl::MaxThreads];
288
289 /** List of instructions that are ready to be executed. */
290 std::list<DynInstPtr> instsToExecute;
291
292 /**
293 * Struct for comparing entries to be added to the priority queue.
294 * This gives reverse ordering to the instructions in terms of
295 * sequence numbers: the instructions with smaller sequence
296 * numbers (and hence are older) will be at the top of the
297 * priority queue.
298 */
299 struct pqCompare {
300 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
301 {
302 return lhs->seqNum > rhs->seqNum;
303 }
304 };
305

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402 /** The number of floating point registers in the CPU. */
403 unsigned numPhysFloatRegs;
404
405 /** Delay between commit stage and the IQ.
406 * @todo: Make there be a distinction between the delays within IEW.
407 */
408 unsigned commitToIEWDelay;
409
410 /** Is the IQ switched out. */
411 bool switchedOut;
412
413 /** The sequence number of the squashed instruction. */
414 InstSeqNum squashedSeqNum[Impl::MaxThreads];
415
416 /** A cache of the recently woken registers. It is 1 if the register
417 * has been woken up recently, and 0 if the register has been added
418 * to the dependency graph and has not yet received its value. It

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470 /** Stat for number of squashed instruction operands examined when
471 * squashing.
472 */
473 Stats::Scalar<> iqSquashedOperandsExamined;
474 /** Stat for number of non-speculative instructions removed due to a squash.
475 */
476 Stats::Scalar<> iqSquashedNonSpecRemoved;
477
478 /** Distribution of number of instructions in the queue. */
479 Stats::VectorDistribution<> queueResDist;
480 /** Distribution of the number of instructions issued. */
481 Stats::Distribution<> numIssuedDist;
482 /** Distribution of the cycles it takes to issue an instruction. */
483 Stats::VectorDistribution<> issueDelayDist;
484
485 /** Number of times an instruction could not be issued because a
486 * FU was busy.
487 */
488 Stats::Vector<> statFuBusy;
489// Stats::Vector<> dist_unissued;
490 /** Stat for total number issued for each instruction type. */
491 Stats::Vector2d<> statIssuedInstType;
492
493 /** Number of instructions issued per cycle. */
494 Stats::Formula issueRate;
495// Stats::Formula issue_stores;
496// Stats::Formula issue_op_rate;
497 /** Number of times the FU was busy. */
498 Stats::Vector<> fuBusy;
499 /** Number of times the FU was busy per instruction issued. */
500 Stats::Formula fuBusyRate;
501};
502
503#endif //__CPU_O3_INST_QUEUE_HH__