iew_impl.hh (8471:18e560ba1539) iew_impl.hh (8513:f4272aa61e74)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 464 unchanged lines hidden (view full) ---

473 }
474
475}
476
477template<class Impl>
478void
479DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
480{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 464 unchanged lines hidden (view full) ---

473 }
474
475}
476
477template<class Impl>
478void
479DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
480{
481 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
482 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
483
481 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
482 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
483 // Need to include inst->seqNum in the following comparison to cover the
484 // corner case when a branch misprediction and a memory violation for the
485 // same instruction (e.g. load PC) are detected in the same cycle. In this
486 // case the memory violator should take precedence over the branch
487 // misprediction because it requires the violator itself to be included in
488 // the squash.
484 if (toCommit->squash[tid] == false ||
489 if (toCommit->squash[tid] == false ||
485 inst->seqNum < toCommit->squashedSeqNum[tid]) {
490 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
486 toCommit->squash[tid] = true;
491 toCommit->squash[tid] = true;
492
487 toCommit->squashedSeqNum[tid] = inst->seqNum;
493 toCommit->squashedSeqNum[tid] = inst->seqNum;
488 TheISA::PCState pc;
489 if (inst->isMemRef() && inst->isIndirectCtrl()) {
490 // If an operation is a control operation as well as a memory
491 // reference we need to use the predicted PC, not the PC+N
492 // This instruction will verify misprediction based on predPC
493 pc = inst->readPredTarg();
494 } else {
495 pc = inst->pcState();
496 TheISA::advancePC(pc, inst->staticInst);
497 }
498 toCommit->pc[tid] = pc;
494 toCommit->pc[tid] = inst->pcState();
499 toCommit->mispredictInst[tid] = NULL;
500
495 toCommit->mispredictInst[tid] = NULL;
496
501 toCommit->includeSquashInst[tid] = false;
497 // Must include the memory violator in the squash.
498 toCommit->includeSquashInst[tid] = true;
502
503 wroteToTimeBuffer = true;
504 }
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)

--- 859 unchanged lines hidden (view full) ---

1369 inst->pcState(), inst->seqNum, inst->physEffAddr);
1370
1371 fetchRedirect[tid] = true;
1372
1373 // Tell the instruction queue that a violation has occured.
1374 instQueue.violation(inst, violator);
1375
1376 // Squash.
499
500 wroteToTimeBuffer = true;
501 }
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)

--- 859 unchanged lines hidden (view full) ---

1366 inst->pcState(), inst->seqNum, inst->physEffAddr);
1367
1368 fetchRedirect[tid] = true;
1369
1370 // Tell the instruction queue that a violation has occured.
1371 instQueue.violation(inst, violator);
1372
1373 // Squash.
1377 squashDueToMemOrder(inst,tid);
1374 squashDueToMemOrder(violator, tid);
1378
1379 ++memOrderViolationEvents;
1380 } else if (ldstQueue.loadBlocked(tid) &&
1381 !ldstQueue.isLoadBlockedHandled(tid)) {
1382 fetchRedirect[tid] = true;
1383
1384 DPRINTF(IEW, "Load operation couldn't execute because the "
1385 "memory system is blocked. PC: %s [sn:%lli]\n",

--- 292 unchanged lines hidden --- 		1375
1376 ++memOrderViolationEvents;
1377 } else if (ldstQueue.loadBlocked(tid) &&
1378 !ldstQueue.isLoadBlockedHandled(tid)) {
1379 fetchRedirect[tid] = true;
1380
1381 DPRINTF(IEW, "Load operation couldn't execute because the "
1382 "memory system is blocked. PC: %s [sn:%lli]\n",

--- 292 unchanged lines hidden ---