iew_impl.hh (8073:e154b9b8e366) iew_impl.hh (8137:48371b9fb929)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 if (toCommit->squash[tid] == false ||
456 inst->seqNum < toCommit->squashedSeqNum[tid]) {
457 toCommit->squash[tid] = true;
458 toCommit->squashedSeqNum[tid] = inst->seqNum;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 442 unchanged lines hidden (view full) ---

451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 if (toCommit->squash[tid] == false ||
456 inst->seqNum < toCommit->squashedSeqNum[tid]) {
457 toCommit->squash[tid] = true;
458 toCommit->squashedSeqNum[tid] = inst->seqNum;
459 toCommit->mispredPC[tid] = inst->instAddr();
460 toCommit->branchMispredict[tid] = true;
461 toCommit->branchTaken[tid] = inst->pcState().branching();
462
463 TheISA::PCState pc = inst->pcState();
464 TheISA::advancePC(pc, inst->staticInst);
465
466 toCommit->pc[tid] = pc;
467 toCommit->mispredictInst[tid] = inst;
468 toCommit->includeSquashInst[tid] = false;

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481
482 if (toCommit->squash[tid] == false ||
483 inst->seqNum < toCommit->squashedSeqNum[tid]) {
484 toCommit->squash[tid] = true;
485 toCommit->squashedSeqNum[tid] = inst->seqNum;
486 TheISA::PCState pc = inst->pcState();
487 TheISA::advancePC(pc, inst->staticInst);
488 toCommit->pc[tid] = pc;
459 toCommit->branchTaken[tid] = inst->pcState().branching();
460
461 TheISA::PCState pc = inst->pcState();
462 TheISA::advancePC(pc, inst->staticInst);
463
464 toCommit->pc[tid] = pc;
465 toCommit->mispredictInst[tid] = inst;
466 toCommit->includeSquashInst[tid] = false;

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479
480 if (toCommit->squash[tid] == false ||
481 inst->seqNum < toCommit->squashedSeqNum[tid]) {
482 toCommit->squash[tid] = true;
483 toCommit->squashedSeqNum[tid] = inst->seqNum;
484 TheISA::PCState pc = inst->pcState();
485 TheISA::advancePC(pc, inst->staticInst);
486 toCommit->pc[tid] = pc;
489 toCommit->branchMispredict[tid] = false;
487 toCommit->mispredictInst[tid] = NULL;
490
491 toCommit->includeSquashInst[tid] = false;
492
493 wroteToTimeBuffer = true;
494 }
495}
496
497template<class Impl>
498void
499DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
500{
501 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
502 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
503 if (toCommit->squash[tid] == false ||
504 inst->seqNum < toCommit->squashedSeqNum[tid]) {
505 toCommit->squash[tid] = true;
506
507 toCommit->squashedSeqNum[tid] = inst->seqNum;
508 toCommit->pc[tid] = inst->pcState();
488
489 toCommit->includeSquashInst[tid] = false;
490
491 wroteToTimeBuffer = true;
492 }
493}
494
495template<class Impl>
496void
497DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
498{
499 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
500 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
501 if (toCommit->squash[tid] == false ||
502 inst->seqNum < toCommit->squashedSeqNum[tid]) {
503 toCommit->squash[tid] = true;
504
505 toCommit->squashedSeqNum[tid] = inst->seqNum;
506 toCommit->pc[tid] = inst->pcState();
509 toCommit->branchMispredict[tid] = false;
507 toCommit->mispredictInst[tid] = NULL;
510
511 // Must include the broadcasted SN in the squash.
512 toCommit->includeSquashInst[tid] = true;
513
514 ldstQueue.setLoadBlockedHandled(tid);
515
516 wroteToTimeBuffer = true;
517 }

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509 // Must include the broadcasted SN in the squash.
510 toCommit->includeSquashInst[tid] = true;
511
512 ldstQueue.setLoadBlockedHandled(tid);
513
514 wroteToTimeBuffer = true;
515 }

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