iew_impl.hh (7852:07ba4754ae0a) iew_impl.hh (7856:d25827665112)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1283 unchanged lines hidden (view full) ---

1292 // scheduler is used. Currently the scheduler schedules the oldest
1293 // instruction first, so the branch resolution order will be correct.
1294 ThreadID tid = inst->threadNumber;
1295
1296 if (!fetchRedirect[tid] ||
1297 !toCommit->squash[tid] ||
1298 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1299
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1283 unchanged lines hidden (view full) ---

1292 // scheduler is used. Currently the scheduler schedules the oldest
1293 // instruction first, so the branch resolution order will be correct.
1294 ThreadID tid = inst->threadNumber;
1295
1296 if (!fetchRedirect[tid] ||
1297 !toCommit->squash[tid] ||
1298 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1299
1300 if (inst->mispredicted()) {
1300 // Prevent testing for misprediction on load instructions,
1301 // that have not been executed.
1302 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1303
1304 if (inst->mispredicted() && !loadNotExecuted) {
1301 fetchRedirect[tid] = true;
1302
1303 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1304 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1305 inst->predInstAddr(), inst->predNextInstAddr());
1306 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1307 inst->pcState(), inst->nextInstAddr());
1308 // If incorrect, then signal the ROB that it must be squashed.

--- 323 unchanged lines hidden --- 		1305 fetchRedirect[tid] = true;
1306
1307 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1308 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1309 inst->predInstAddr(), inst->predNextInstAddr());
1310 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1311 inst->pcState(), inst->nextInstAddr());
1312 // If incorrect, then signal the ROB that it must be squashed.

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