iew_impl.hh (7851:bb38f0c47ade) iew_impl.hh (7852:07ba4754ae0a)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 438 unchanged lines hidden (view full) ---

447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 438 unchanged lines hidden (view full) ---

447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 toCommit->squash[tid] = true;
456 toCommit->squashedSeqNum[tid] = inst->seqNum;
457 toCommit->mispredPC[tid] = inst->instAddr();
458 toCommit->branchMispredict[tid] = true;
459 toCommit->mispredictInst[tid] = inst;
455 if (toCommit->squash[tid] == false ||
456 inst->seqNum < toCommit->squashedSeqNum[tid]) {
457 toCommit->squash[tid] = true;
458 toCommit->squashedSeqNum[tid] = inst->seqNum;
459 toCommit->mispredPC[tid] = inst->instAddr();
460 toCommit->branchMispredict[tid] = true;
461 toCommit->branchTaken[tid] = inst->pcState().branching();
460
462
461 toCommit->branchTaken[tid] = inst->pcState().branching();
462 TheISA::PCState pc = inst->pcState();
463 TheISA::advancePC(pc, inst->staticInst);
464 toCommit->pc[tid] = pc;
463 TheISA::PCState pc = inst->pcState();
464 TheISA::advancePC(pc, inst->staticInst);
465
465
466 toCommit->includeSquashInst[tid] = false;
466 toCommit->pc[tid] = pc;
467 toCommit->mispredictInst[tid] = inst;
468 toCommit->includeSquashInst[tid] = false;
467
469
468 wroteToTimeBuffer = true;
470 wroteToTimeBuffer = true;
471 }
472
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
476 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
477
473}
474
475template<class Impl>
476void
477DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
478{
479 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
480 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
481
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 TheISA::PCState pc = inst->pcState();
481 TheISA::advancePC(pc, inst->staticInst);
482 toCommit->pc[tid] = pc;
483 toCommit->branchMispredict[tid] = false;
482 if (toCommit->squash[tid] == false ||
483 inst->seqNum < toCommit->squashedSeqNum[tid]) {
484 toCommit->squash[tid] = true;
485 toCommit->squashedSeqNum[tid] = inst->seqNum;
486 TheISA::PCState pc = inst->pcState();
487 TheISA::advancePC(pc, inst->staticInst);
488 toCommit->pc[tid] = pc;
489 toCommit->branchMispredict[tid] = false;
484
490
485 toCommit->includeSquashInst[tid] = false;
491 toCommit->includeSquashInst[tid] = false;
486
492
487 wroteToTimeBuffer = true;
493 wroteToTimeBuffer = true;
494 }
488}
489
490template<class Impl>
491void
492DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
493{
494 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
495 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
495}
496
497template<class Impl>
498void
499DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
500{
501 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
502 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
503 if (toCommit->squash[tid] == false ||
504 inst->seqNum < toCommit->squashedSeqNum[tid]) {
505 toCommit->squash[tid] = true;
496
506
497 toCommit->squash[tid] = true;
498 toCommit->squashedSeqNum[tid] = inst->seqNum;
499 toCommit->pc[tid] = inst->pcState();
500 toCommit->branchMispredict[tid] = false;
507 toCommit->squashedSeqNum[tid] = inst->seqNum;
508 toCommit->pc[tid] = inst->pcState();
509 toCommit->branchMispredict[tid] = false;
501
510
502 // Must include the broadcasted SN in the squash.
503 toCommit->includeSquashInst[tid] = true;
511 // Must include the broadcasted SN in the squash.
512 toCommit->includeSquashInst[tid] = true;
504
513
505 ldstQueue.setLoadBlockedHandled(tid);
514 ldstQueue.setLoadBlockedHandled(tid);
506
515
507 wroteToTimeBuffer = true;
516 wroteToTimeBuffer = true;
517 }
508}
509
510template<class Impl>
511void
512DefaultIEW<Impl>::block(ThreadID tid)
513{
514 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
515

--- 267 unchanged lines hidden (view full) ---

783
784 if (dispatchStatus[tid] == Blocked ||
785 dispatchStatus[tid] == Unblocking) {
786 toRename->iewUnblock[tid] = true;
787 wroteToTimeBuffer = true;
788 }
789
790 dispatchStatus[tid] = Squashing;
518}
519
520template<class Impl>
521void
522DefaultIEW<Impl>::block(ThreadID tid)
523{
524 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
525

--- 267 unchanged lines hidden (view full) ---

793
794 if (dispatchStatus[tid] == Blocked ||
795 dispatchStatus[tid] == Unblocking) {
796 toRename->iewUnblock[tid] = true;
797 wroteToTimeBuffer = true;
798 }
799
800 dispatchStatus[tid] = Squashing;
791
792 fetchRedirect[tid] = false;
793 return;
794 }
795
796 if (fromCommit->commitInfo[tid].robSquashing) {
797 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
798
799 dispatchStatus[tid] = Squashing;
801 fetchRedirect[tid] = false;
802 return;
803 }
804
805 if (fromCommit->commitInfo[tid].robSquashing) {
806 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
807
808 dispatchStatus[tid] = Squashing;
800
801 emptyRenameInsts(tid);
802 wroteToTimeBuffer = true;
803 return;
804 }
805
806 if (checkStall(tid)) {
807 block(tid);
808 dispatchStatus[tid] = Blocked;

--- 472 unchanged lines hidden (view full) ---

1281 // redirects fetch in this group of instructions.
1282
1283 // This probably needs to prioritize the redirects if a different
1284 // scheduler is used. Currently the scheduler schedules the oldest
1285 // instruction first, so the branch resolution order will be correct.
1286 ThreadID tid = inst->threadNumber;
1287
1288 if (!fetchRedirect[tid] ||
809 emptyRenameInsts(tid);
810 wroteToTimeBuffer = true;
811 return;
812 }
813
814 if (checkStall(tid)) {
815 block(tid);
816 dispatchStatus[tid] = Blocked;

--- 472 unchanged lines hidden (view full) ---

1289 // redirects fetch in this group of instructions.
1290
1291 // This probably needs to prioritize the redirects if a different
1292 // scheduler is used. Currently the scheduler schedules the oldest
1293 // instruction first, so the branch resolution order will be correct.
1294 ThreadID tid = inst->threadNumber;
1295
1296 if (!fetchRedirect[tid] ||
1297 !toCommit->squash[tid] ||
1289 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1290
1291 if (inst->mispredicted()) {
1292 fetchRedirect[tid] = true;
1293
1294 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1295 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1296 inst->predInstAddr(), inst->predNextInstAddr());

--- 80 unchanged lines hidden (view full) ---

1377
1378 cpu->activityThisCycle();
1379 }
1380
1381 // Need to reset this in case a writeback event needs to write into the
1382 // iew queue. That way the writeback event will write into the correct
1383 // spot in the queue.
1384 wbNumInst = 0;
1298 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1299
1300 if (inst->mispredicted()) {
1301 fetchRedirect[tid] = true;
1302
1303 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1304 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1305 inst->predInstAddr(), inst->predNextInstAddr());

--- 80 unchanged lines hidden (view full) ---

1386
1387 cpu->activityThisCycle();
1388 }
1389
1390 // Need to reset this in case a writeback event needs to write into the
1391 // iew queue. That way the writeback event will write into the correct
1392 // spot in the queue.
1393 wbNumInst = 0;
1394
1385}
1386
1387template <class Impl>
1388void
1389DefaultIEW<Impl>::writebackInsts()
1390{
1391 // Loop through the head of the time buffer and wake any
1392 // dependents. These instructions are about to write back. Also

--- 198 unchanged lines hidden (view full) ---

1591
1592template <class Impl>
1593void
1594DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1595{
1596 ThreadID tid = inst->threadNumber;
1597
1598 if (!fetchRedirect[tid] ||
1395}
1396
1397template <class Impl>
1398void
1399DefaultIEW<Impl>::writebackInsts()
1400{
1401 // Loop through the head of the time buffer and wake any
1402 // dependents. These instructions are about to write back. Also

--- 198 unchanged lines hidden (view full) ---

1601
1602template <class Impl>
1603void
1604DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1605{
1606 ThreadID tid = inst->threadNumber;
1607
1608 if (!fetchRedirect[tid] ||
1609 !toCommit->squash[tid] ||
1599 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1600
1601 if (inst->mispredicted()) {
1602 fetchRedirect[tid] = true;
1603
1604 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1605 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1606 inst->predInstAddr(), inst->predNextInstAddr());

--- 14 unchanged lines hidden --- 		1610 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1611
1612 if (inst->mispredicted()) {
1613 fetchRedirect[tid] = true;
1614
1615 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1616 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1617 inst->predInstAddr(), inst->predNextInstAddr());

--- 14 unchanged lines hidden ---