iew_impl.hh (7813:7338bc628489) iew_impl.hh (7847:0c6613ad8f18)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1250 // Store conditionals will mark themselves as
1251 // executed, and their writeback event will add the
1252 // instruction to the queue to commit.
1253 } else {
1254 panic("Unexpected memory type!\n");
1255 }
1256
1257 } else {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1241 unchanged lines hidden (view full) ---

1250 // Store conditionals will mark themselves as
1251 // executed, and their writeback event will add the
1252 // instruction to the queue to commit.
1253 } else {
1254 panic("Unexpected memory type!\n");
1255 }
1256
1257 } else {
1258 inst->execute();
1258 // If the instruction has already faulted, then skip executing it.
1259 // Such case can happen when it faulted during ITLB translation.
1260 // If we execute the instruction (even if it's a nop) the fault
1261 // will be replaced and we will lose it.
1262 if (inst->getFault() == NoFault) {
1263 inst->execute();
1264 }
1259
1260 inst->setExecuted();
1261
1262 instToCommit(inst);
1263 }
1264
1265 updateExeInstStats(inst);
1266

--- 343 unchanged lines hidden --- 		1265
1266 inst->setExecuted();
1267
1268 instToCommit(inst);
1269 }
1270
1271 updateExeInstStats(inst);
1272

--- 343 unchanged lines hidden ---