iew_impl.hh (4329:52057dbec096) iew_impl.hh (4632:be5b8f67b8fb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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64
65 // Instruction queue needs the queue between issue and execute.
66 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
67
68 for (int i=0; i < numThreads; i++) {
69 dispatchStatus[i] = Running;
70 stalls[i].commit = false;
71 fetchRedirect[i] = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 55 unchanged lines hidden (view full) ---

64
65 // Instruction queue needs the queue between issue and execute.
66 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
67
68 for (int i=0; i < numThreads; i++) {
69 dispatchStatus[i] = Running;
70 stalls[i].commit = false;
71 fetchRedirect[i] = false;
72 bdelayDoneSeqNum[i] = 0;
73 }
74
75 wbMax = wbWidth * params->wbDepth;
76
77 updateLSQNextCycle = false;
78
79 ableToIssue = true;
80

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405{
406 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
407 tid);
408
409 // Tell the IQ to start squashing.
410 instQueue.squash(tid);
411
412 // Tell the LDSTQ to start squashing.
72 }
73
74 wbMax = wbWidth * params->wbDepth;
75
76 updateLSQNextCycle = false;
77
78 ableToIssue = true;
79

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404{
405 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
406 tid);
407
408 // Tell the IQ to start squashing.
409 instQueue.squash(tid);
410
411 // Tell the LDSTQ to start squashing.
413#if ISA_HAS_DELAY_SLOT
414 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
415#else
416 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
412 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
417#endif
418 updatedQueues = true;
419
420 // Clear the skid buffer in case it has any data in it.
421 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
413 updatedQueues = true;
414
415 // Clear the skid buffer in case it has any data in it.
416 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
422 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
417 tid, fromCommit->commitInfo[tid].doneSeqNum);
423
424 while (!skidBuffer[tid].empty()) {
418
419 while (!skidBuffer[tid].empty()) {
425#if ISA_HAS_DELAY_SLOT
426 if (skidBuffer[tid].front()->seqNum <=
427 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
428 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
429 "that occur before delay slot [sn:%i].\n",
430 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
431 tid);
432 break;
433 } else {
434 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
435 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
436 }
437#endif
438 if (skidBuffer[tid].front()->isLoad() ||
439 skidBuffer[tid].front()->isStore() ) {
440 toRename->iewInfo[tid].dispatchedToLSQ++;
441 }
442
443 toRename->iewInfo[tid].dispatched++;
444
445 skidBuffer[tid].pop();
446 }
447
420 if (skidBuffer[tid].front()->isLoad() ||
421 skidBuffer[tid].front()->isStore() ) {
422 toRename->iewInfo[tid].dispatchedToLSQ++;
423 }
424
425 toRename->iewInfo[tid].dispatched++;
426
427 skidBuffer[tid].pop();
428 }
429
448 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
449
450 emptyRenameInsts(tid);
451}
452
453template<class Impl>
454void
455DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
456{
457 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
458 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
459
460 toCommit->squash[tid] = true;
461 toCommit->squashedSeqNum[tid] = inst->seqNum;
462 toCommit->mispredPC[tid] = inst->readPC();
463 toCommit->branchMispredict[tid] = true;
464
430 emptyRenameInsts(tid);
431}
432
433template<class Impl>
434void
435DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
436{
437 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
438 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
439
440 toCommit->squash[tid] = true;
441 toCommit->squashedSeqNum[tid] = inst->seqNum;
442 toCommit->mispredPC[tid] = inst->readPC();
443 toCommit->branchMispredict[tid] = true;
444
465 int instSize = sizeof(TheISA::MachInst);
466#if ISA_HAS_DELAY_SLOT
445#if ISA_HAS_DELAY_SLOT
467 bool branch_taken =
446 int instSize = sizeof(TheISA::MachInst);
447 toCommit->branchTaken[tid] =
468 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
469 (inst->readNextPC() == inst->readPC() + instSize ||
470 inst->readNextPC() == inst->readPC() + 2 * instSize));
448 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
449 (inst->readNextPC() == inst->readPC() + instSize ||
450 inst->readNextPC() == inst->readPC() + 2 * instSize));
471 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
472 branch_taken ? "true": "false", inst->seqNum);
473
474 toCommit->branchTaken[tid] = branch_taken;
475
476 bool squashDelaySlot = true;
477// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
478 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
479 squashDelaySlot ? "true": "false", inst->seqNum);
480 toCommit->squashDelaySlot[tid] = squashDelaySlot;
481 //If we're squashing the delay slot, we need to pick back up at NextPC.
482 //Otherwise, NextPC isn't being squashed, so we should pick back up at
483 //NextNPC.
484 if (squashDelaySlot) {
485 toCommit->nextPC[tid] = inst->readNextPC();
486 toCommit->nextNPC[tid] = inst->readNextNPC();
487 } else {
488 toCommit->nextPC[tid] = inst->readNextNPC();
489 toCommit->nextNPC[tid] = inst->readNextNPC() + instSize;
490 }
491#else
492 toCommit->branchTaken[tid] = inst->readNextPC() !=
493 (inst->readPC() + sizeof(TheISA::MachInst));
451#else
452 toCommit->branchTaken[tid] = inst->readNextPC() !=
453 (inst->readPC() + sizeof(TheISA::MachInst));
494 toCommit->nextPC[tid] = inst->readNextPC();
495 toCommit->nextNPC[tid] = inst->readNextPC() + instSize;
496#endif
454#endif
455 toCommit->nextPC[tid] = inst->readNextPC();
456 toCommit->nextNPC[tid] = inst->readNextNPC();
497
498 toCommit->includeSquashInst[tid] = false;
499
500 wroteToTimeBuffer = true;
501}
502
503template<class Impl>
504void
505DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
506{
507 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
508 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
509
510 toCommit->squash[tid] = true;
511 toCommit->squashedSeqNum[tid] = inst->seqNum;
512 toCommit->nextPC[tid] = inst->readNextPC();
457
458 toCommit->includeSquashInst[tid] = false;
459
460 wroteToTimeBuffer = true;
461}
462
463template<class Impl>
464void
465DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
466{
467 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
468 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
469
470 toCommit->squash[tid] = true;
471 toCommit->squashedSeqNum[tid] = inst->seqNum;
472 toCommit->nextPC[tid] = inst->readNextPC();
513#if ISA_HAS_DELAY_SLOT
514 toCommit->nextNPC[tid] = inst->readNextNPC();
473 toCommit->nextNPC[tid] = inst->readNextNPC();
515#else
516 toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst);
517#endif
518 toCommit->branchMispredict[tid] = false;
519
520 toCommit->includeSquashInst[tid] = false;
521
522 wroteToTimeBuffer = true;
523}
524
525template<class Impl>
526void
527DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
528{
529 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
530 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
531
532 toCommit->squash[tid] = true;
533 toCommit->squashedSeqNum[tid] = inst->seqNum;
534 toCommit->nextPC[tid] = inst->readPC();
474 toCommit->branchMispredict[tid] = false;
475
476 toCommit->includeSquashInst[tid] = false;
477
478 wroteToTimeBuffer = true;
479}
480
481template<class Impl>
482void
483DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
484{
485 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
486 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
487
488 toCommit->squash[tid] = true;
489 toCommit->squashedSeqNum[tid] = inst->seqNum;
490 toCommit->nextPC[tid] = inst->readPC();
535#if ISA_HAS_DELAY_SLOT
536 toCommit->nextNPC[tid] = inst->readNextPC();
491 toCommit->nextNPC[tid] = inst->readNextPC();
537#else
538 toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst);
539#endif
540 toCommit->branchMispredict[tid] = false;
541
542 // Must include the broadcasted SN in the squash.
543 toCommit->includeSquashInst[tid] = true;
544
545 ldstQueue.setLoadBlockedHandled(tid);
546
547 wroteToTimeBuffer = true;

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875}
876
877template <class Impl>
878void
879DefaultIEW<Impl>::sortInsts()
880{
881 int insts_from_rename = fromRename->size;
882#ifdef DEBUG
492 toCommit->branchMispredict[tid] = false;
493
494 // Must include the broadcasted SN in the squash.
495 toCommit->includeSquashInst[tid] = true;
496
497 ldstQueue.setLoadBlockedHandled(tid);
498
499 wroteToTimeBuffer = true;

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827}
828
829template <class Impl>
830void
831DefaultIEW<Impl>::sortInsts()
832{
833 int insts_from_rename = fromRename->size;
834#ifdef DEBUG
883#if !ISA_HAS_DELAY_SLOT
884 for (int i = 0; i < numThreads; i++)
885 assert(insts[i].empty());
886#endif
835 for (int i = 0; i < numThreads; i++)
836 assert(insts[i].empty());
837#endif
887#endif
888 for (int i = 0; i < insts_from_rename; ++i) {
889 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
890 }
891}
892
893template <class Impl>
894void
895DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
896{
838 for (int i = 0; i < insts_from_rename; ++i) {
839 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
840 }
841}
842
843template <class Impl>
844void
845DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
846{
897 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
898 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
847 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
899
900 while (!insts[tid].empty()) {
848
849 while (!insts[tid].empty()) {
901#if ISA_HAS_DELAY_SLOT
902 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
903 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
904 " that occurs at or before delay slot [sn:%i].\n",
905 tid, bdelayDoneSeqNum[tid]);
906 break;
907 } else {
908 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
909 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
910 }
911#endif
912
913 if (insts[tid].front()->isLoad() ||
914 insts[tid].front()->isStore() ) {
915 toRename->iewInfo[tid].dispatchedToLSQ++;
916 }
917
918 toRename->iewInfo[tid].dispatched++;
919

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851 if (insts[tid].front()->isLoad() ||
852 insts[tid].front()->isStore() ) {
853 toRename->iewInfo[tid].dispatchedToLSQ++;
854 }
855
856 toRename->iewInfo[tid].dispatched++;
857

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