iew_impl.hh (3969:77957f66c1d5) iew_impl.hh (3970:d54945bab95d)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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690}
691
692template<class Impl>
693int
694DefaultIEW<Impl>::skidCount()
695{
696 int max=0;
697
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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690}
691
692template<class Impl>
693int
694DefaultIEW<Impl>::skidCount()
695{
696 int max=0;
697
698 std::list<unsigned>::iterator threads = (*activeThreads).begin();
698 std::list<unsigned>::iterator threads = activeThreads->begin();
699 std::list<unsigned>::iterator end = activeThreads->end();
699
700
700 while (threads != (*activeThreads).end()) {
701 unsigned thread_count = skidBuffer[*threads++].size();
701 while (threads != end) {
702 unsigned tid = *threads++;
703 unsigned thread_count = skidBuffer[tid].size();
702 if (max < thread_count)
703 max = thread_count;
704 }
705
706 return max;
707}
708
709template<class Impl>
710bool
711DefaultIEW<Impl>::skidsEmpty()
712{
704 if (max < thread_count)
705 max = thread_count;
706 }
707
708 return max;
709}
710
711template<class Impl>
712bool
713DefaultIEW<Impl>::skidsEmpty()
714{
713 std::list<unsigned>::iterator threads = (*activeThreads).begin();
715 std::list<unsigned>::iterator threads = activeThreads->begin();
716 std::list<unsigned>::iterator end = activeThreads->end();
714
717
715 while (threads != (*activeThreads).end()) {
716 if (!skidBuffer[*threads++].empty())
718 while (threads != end) {
719 unsigned tid = *threads++;
720
721 if (!skidBuffer[tid].empty())
717 return false;
718 }
719
720 return true;
721}
722
723template <class Impl>
724void
725DefaultIEW<Impl>::updateStatus()
726{
727 bool any_unblocking = false;
728
722 return false;
723 }
724
725 return true;
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::updateStatus()
731{
732 bool any_unblocking = false;
733
729 std::list<unsigned>::iterator threads = (*activeThreads).begin();
734 std::list<unsigned>::iterator threads = activeThreads->begin();
735 std::list<unsigned>::iterator end = activeThreads->end();
730
736
731 threads = (*activeThreads).begin();
732
733 while (threads != (*activeThreads).end()) {
737 while (threads != end) {
734 unsigned tid = *threads++;
735
736 if (dispatchStatus[tid] == Unblocking) {
737 any_unblocking = true;
738 break;
739 }
740 }
741

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1139 add_to_iq = false;
1140
1141 ++iewDispNonSpecInsts;
1142 } else {
1143 add_to_iq = true;
1144 }
1145
1146 toRename->iewInfo[tid].dispatchedToLSQ++;
738 unsigned tid = *threads++;
739
740 if (dispatchStatus[tid] == Unblocking) {
741 any_unblocking = true;
742 break;
743 }
744 }
745

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1143 add_to_iq = false;
1144
1145 ++iewDispNonSpecInsts;
1146 } else {
1147 add_to_iq = true;
1148 }
1149
1150 toRename->iewInfo[tid].dispatchedToLSQ++;
1147#if FULL_SYSTEM
1148 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1149 // Same as non-speculative stores.
1150 inst->setCanCommit();
1151 instQueue.insertBarrier(inst);
1152 add_to_iq = false;
1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1152 // Same as non-speculative stores.
1153 inst->setCanCommit();
1154 instQueue.insertBarrier(inst);
1155 add_to_iq = false;
1153#endif
1154 } else if (inst->isNonSpeculative()) {
1155 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1156 "encountered, skipping.\n", tid);
1157
1158 // Same as non-speculative stores.
1159 inst->setCanCommit();
1160
1161 // Specifically insert it as nonspeculative.

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1245
1246template <class Impl>
1247void
1248DefaultIEW<Impl>::executeInsts()
1249{
1250 wbNumInst = 0;
1251 wbCycle = 0;
1252
1156 } else if (inst->isNonSpeculative()) {
1157 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1158 "encountered, skipping.\n", tid);
1159
1160 // Same as non-speculative stores.
1161 inst->setCanCommit();
1162
1163 // Specifically insert it as nonspeculative.

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1247
1248template <class Impl>
1249void
1250DefaultIEW<Impl>::executeInsts()
1251{
1252 wbNumInst = 0;
1253 wbCycle = 0;
1254
1253 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1255 std::list<unsigned>::iterator threads = activeThreads->begin();
1256 std::list<unsigned>::iterator end = activeThreads->end();
1254
1257
1255 while (threads != (*activeThreads).end()) {
1258 while (threads != end) {
1256 unsigned tid = *threads++;
1257 fetchRedirect[tid] = false;
1258 }
1259
1260 // Uncomment this if you want to see all available instructions.
1261// printAvailableInsts();
1262
1263 // Execute/writeback any instructions that are available.

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1486 wroteToTimeBuffer = false;
1487 updatedQueues = false;
1488
1489 sortInsts();
1490
1491 // Free function units marked as being freed this cycle.
1492 fuPool->processFreeUnits();
1493
1259 unsigned tid = *threads++;
1260 fetchRedirect[tid] = false;
1261 }
1262
1263 // Uncomment this if you want to see all available instructions.
1264// printAvailableInsts();
1265
1266 // Execute/writeback any instructions that are available.

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1489 wroteToTimeBuffer = false;
1490 updatedQueues = false;
1491
1492 sortInsts();
1493
1494 // Free function units marked as being freed this cycle.
1495 fuPool->processFreeUnits();
1496
1494 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1497 std::list<unsigned>::iterator threads = activeThreads->begin();
1498 std::list<unsigned>::iterator end = activeThreads->end();
1495
1496 // Check stall and squash signals, dispatch any instructions.
1499
1500 // Check stall and squash signals, dispatch any instructions.
1497 while (threads != (*activeThreads).end()) {
1498 unsigned tid = *threads++;
1501 while (threads != end) {
1502 unsigned tid = *threads++;
1499
1500 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1501
1502 checkSignalsAndUpdate(tid);
1503 dispatch(tid);
1504 }
1505
1506 if (exeStatus != Squashing) {

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1530 // Writeback any stores using any leftover bandwidth.
1531 ldstQueue.writebackStores();
1532
1533 // Check the committed load/store signals to see if there's a load
1534 // or store to commit. Also check if it's being told to execute a
1535 // nonspeculative instruction.
1536 // This is pretty inefficient...
1537
1503
1504 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1505
1506 checkSignalsAndUpdate(tid);
1507 dispatch(tid);
1508 }
1509
1510 if (exeStatus != Squashing) {

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1534 // Writeback any stores using any leftover bandwidth.
1535 ldstQueue.writebackStores();
1536
1537 // Check the committed load/store signals to see if there's a load
1538 // or store to commit. Also check if it's being told to execute a
1539 // nonspeculative instruction.
1540 // This is pretty inefficient...
1541
1538 threads = (*activeThreads).begin();
1539 while (threads != (*activeThreads).end()) {
1542 threads = activeThreads->begin();
1543 while (threads != end) {
1540 unsigned tid = (*threads++);
1541
1542 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1543
1544 // Update structures based on instructions committed.
1545 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1546 !fromCommit->commitInfo[tid].squash &&
1547 !fromCommit->commitInfo[tid].robSquashing) {

--- 88 unchanged lines hidden --- 		1544 unsigned tid = (*threads++);
1545
1546 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1547
1548 // Update structures based on instructions committed.
1549 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1550 !fromCommit->commitInfo[tid].squash &&
1551 !fromCommit->commitInfo[tid].robSquashing) {

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