iew_impl.hh (3958:58d09260d073) iew_impl.hh (3969:77957f66c1d5)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484 int instSize = sizeof(TheISA::MachInst);
483 int instSize = sizeof(TheISA::MachInst);
484#if ISA_HAS_DELAY_SLOT
485 bool branch_taken =
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
491
492 toCommit->branchTaken[tid] = branch_taken;

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497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
501 //NextNPC.
502 if (squashDelaySlot) {
503 toCommit->nextPC[tid] = inst->readNextPC();
504 toCommit->nextNPC[tid] = inst->readNextNPC();
485 bool branch_taken =
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
491
492 toCommit->branchTaken[tid] = branch_taken;

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497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
501 //NextNPC.
502 if (squashDelaySlot) {
503 toCommit->nextPC[tid] = inst->readNextPC();
504 toCommit->nextNPC[tid] = inst->readNextNPC();
505 } else
505 } else {
506 toCommit->nextPC[tid] = inst->readNextNPC();
506 toCommit->nextPC[tid] = inst->readNextNPC();
507 toCommit->nextNPC[tid] = inst->readNextNPC() + instSize;
508 }
507#else
508 toCommit->branchTaken[tid] = inst->readNextPC() !=
509 (inst->readPC() + sizeof(TheISA::MachInst));
510 toCommit->nextPC[tid] = inst->readNextPC();
509#else
510 toCommit->branchTaken[tid] = inst->readNextPC() !=
511 (inst->readPC() + sizeof(TheISA::MachInst));
512 toCommit->nextPC[tid] = inst->readNextPC();
513 toCommit->nextNPC[tid] = inst->readNextPC() + instSize;
511#endif
512
513 toCommit->includeSquashInst[tid] = false;
514
515 wroteToTimeBuffer = true;
516}
517
518template<class Impl>
519void
520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
521{
522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
524
525 toCommit->squash[tid] = true;
526 toCommit->squashedSeqNum[tid] = inst->seqNum;
527 toCommit->nextPC[tid] = inst->readNextPC();
528#if ISA_HAS_DELAY_SLOT
529 toCommit->nextNPC[tid] = inst->readNextNPC();
514#endif
515
516 toCommit->includeSquashInst[tid] = false;
517
518 wroteToTimeBuffer = true;
519}
520
521template<class Impl>
522void
523DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
524{
525 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
526 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
527
528 toCommit->squash[tid] = true;
529 toCommit->squashedSeqNum[tid] = inst->seqNum;
530 toCommit->nextPC[tid] = inst->readNextPC();
531#if ISA_HAS_DELAY_SLOT
532 toCommit->nextNPC[tid] = inst->readNextNPC();
533#else
534 toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst);
530#endif
531 toCommit->branchMispredict[tid] = false;
532
533 toCommit->includeSquashInst[tid] = false;
534
535 wroteToTimeBuffer = true;
536}
537

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542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
543 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
544
545 toCommit->squash[tid] = true;
546 toCommit->squashedSeqNum[tid] = inst->seqNum;
547 toCommit->nextPC[tid] = inst->readPC();
548#if ISA_HAS_DELAY_SLOT
549 toCommit->nextNPC[tid] = inst->readNextPC();
535#endif
536 toCommit->branchMispredict[tid] = false;
537
538 toCommit->includeSquashInst[tid] = false;
539
540 wroteToTimeBuffer = true;
541}
542

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547 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
548 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
549
550 toCommit->squash[tid] = true;
551 toCommit->squashedSeqNum[tid] = inst->seqNum;
552 toCommit->nextPC[tid] = inst->readPC();
553#if ISA_HAS_DELAY_SLOT
554 toCommit->nextNPC[tid] = inst->readNextPC();
555#else
556 toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst);
550#endif
551 toCommit->branchMispredict[tid] = false;
552
553 // Must include the broadcasted SN in the squash.
554 toCommit->includeSquashInst[tid] = true;
555
556 ldstQueue.setLoadBlockedHandled(tid);
557

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1350
1351 if (!fetchRedirect[tid] ||
1352 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1353
1354 if (inst->mispredicted()) {
1355 fetchRedirect[tid] = true;
1356
1357 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
557#endif
558 toCommit->branchMispredict[tid] = false;
559
560 // Must include the broadcasted SN in the squash.
561 toCommit->includeSquashInst[tid] = true;
562
563 ldstQueue.setLoadBlockedHandled(tid);
564

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1357
1358 if (!fetchRedirect[tid] ||
1359 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1360
1361 if (inst->mispredicted()) {
1362 fetchRedirect[tid] = true;
1363
1364 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1358 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC);
1359#if ISA_HAS_DELAY_SLOT
1360 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1361 inst->nextNPC);
1362#else
1363 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1364 inst->nextPC);
1365#endif
1365 DPRINTF(IEW, "Predicted target was %#x, %#x.\n",
1366 inst->readPredPC(), inst->readPredNPC());
1367 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1368 " NPC: %#x.\n", inst->readNextPC(),
1369 inst->readNextNPC());
1366 // If incorrect, then signal the ROB that it must be squashed.
1367 squashDueToBranch(inst, tid);
1368
1369 if (inst->readPredTaken()) {
1370 predictedTakenIncorrect++;
1371 } else {
1372 predictedNotTakenIncorrect++;
1373 }

--- 258 unchanged lines hidden --- 		1370 // If incorrect, then signal the ROB that it must be squashed.
1371 squashDueToBranch(inst, tid);
1372
1373 if (inst->readPredTaken()) {
1374 predictedTakenIncorrect++;
1375 } else {
1376 predictedNotTakenIncorrect++;
1377 }

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