iew_impl.hh (3949:b6664282d899) iew_impl.hh (3958:58d09260d073)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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541{
542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
543 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
544
545 toCommit->squash[tid] = true;
546 toCommit->squashedSeqNum[tid] = inst->seqNum;
547 toCommit->nextPC[tid] = inst->readPC();
548#if ISA_HAS_DELAY_SLOT
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 532 unchanged lines hidden (view full) ---

541{
542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
543 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
544
545 toCommit->squash[tid] = true;
546 toCommit->squashedSeqNum[tid] = inst->seqNum;
547 toCommit->nextPC[tid] = inst->readPC();
548#if ISA_HAS_DELAY_SLOT
549 toCommit->nextNPC[tid] = inst->readNextNPC();
549 toCommit->nextNPC[tid] = inst->readNextPC();
550#endif
551 toCommit->branchMispredict[tid] = false;
552
553 // Must include the broadcasted SN in the squash.
554 toCommit->includeSquashInst[tid] = true;
555
556 ldstQueue.setLoadBlockedHandled(tid);
557

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1431void
1432DefaultIEW<Impl>::writebackInsts()
1433{
1434 // Loop through the head of the time buffer and wake any
1435 // dependents. These instructions are about to write back. Also
1436 // mark scoreboard that this instruction is finally complete.
1437 // Either have IEW have direct access to scoreboard, or have this
1438 // as part of backwards communication.
550#endif
551 toCommit->branchMispredict[tid] = false;
552
553 // Must include the broadcasted SN in the squash.
554 toCommit->includeSquashInst[tid] = true;
555
556 ldstQueue.setLoadBlockedHandled(tid);
557

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1431void
1432DefaultIEW<Impl>::writebackInsts()
1433{
1434 // Loop through the head of the time buffer and wake any
1435 // dependents. These instructions are about to write back. Also
1436 // mark scoreboard that this instruction is finally complete.
1437 // Either have IEW have direct access to scoreboard, or have this
1438 // as part of backwards communication.
1439 for (int inst_num = 0; inst_num < issueWidth &&
1439 for (int inst_num = 0; inst_num < wbWidth &&
1440 toCommit->insts[inst_num]; inst_num++) {
1441 DynInstPtr inst = toCommit->insts[inst_num];
1442 int tid = inst->threadNumber;
1443
1444 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1445 inst->seqNum, inst->readPC());
1446
1447 iewInstsToCommit[tid]++;

--- 184 unchanged lines hidden --- 		1440 toCommit->insts[inst_num]; inst_num++) {
1441 DynInstPtr inst = toCommit->insts[inst_num];
1442 int tid = inst->threadNumber;
1443
1444 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1445 inst->seqNum, inst->readPC());
1446
1447 iewInstsToCommit[tid]++;

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