iew_impl.hh (3771:808a4c19cf34) iew_impl.hh (3795:60ecc96c3cee)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484 int instSize = sizeof(TheISA::MachInst);
484 bool branch_taken =
485 bool branch_taken =
485 (inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) &&
486 inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst)));
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
487 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
488 branch_taken ? "true": "false", inst->seqNum);
489
490 toCommit->branchTaken[tid] = branch_taken;
491
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
491
492 toCommit->branchTaken[tid] = branch_taken;
493
492 bool squashDelaySlot =
493 (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
494 bool squashDelaySlot = true;
495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
494 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
495 squashDelaySlot ? "true": "false", inst->seqNum);
496 toCommit->squashDelaySlot[tid] = squashDelaySlot;
497 //If we're squashing the delay slot, we need to pick back up at NextPC.
498 //Otherwise, NextPC isn't being squashed, so we should pick back up at
499 //NextNPC.
496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
501 //NextNPC.
500 if (squashDelaySlot)
502 if (squashDelaySlot) {
501 toCommit->nextPC[tid] = inst->readNextPC();
503 toCommit->nextPC[tid] = inst->readNextPC();
502 else
504 toCommit->nextNPC[tid] = inst->readNextNPC();
505 } else
503 toCommit->nextPC[tid] = inst->readNextNPC();
504#else
505 toCommit->branchTaken[tid] = inst->readNextPC() !=
506 (inst->readPC() + sizeof(TheISA::MachInst));
507 toCommit->nextPC[tid] = inst->readNextPC();
508#endif
509
510 toCommit->includeSquashInst[tid] = false;

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517DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
518{
519 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
520 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
521
522 toCommit->squash[tid] = true;
523 toCommit->squashedSeqNum[tid] = inst->seqNum;
524 toCommit->nextPC[tid] = inst->readNextPC();
506 toCommit->nextPC[tid] = inst->readNextNPC();
507#else
508 toCommit->branchTaken[tid] = inst->readNextPC() !=
509 (inst->readPC() + sizeof(TheISA::MachInst));
510 toCommit->nextPC[tid] = inst->readNextPC();
511#endif
512
513 toCommit->includeSquashInst[tid] = false;

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520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
521{
522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
524
525 toCommit->squash[tid] = true;
526 toCommit->squashedSeqNum[tid] = inst->seqNum;
527 toCommit->nextPC[tid] = inst->readNextPC();
528#if ISA_HAS_DELAY_SLOT
529 toCommit->nextNPC[tid] = inst->readNextNPC();
530#endif
525
526 toCommit->includeSquashInst[tid] = false;
527
528 wroteToTimeBuffer = true;
529}
530
531template<class Impl>
532void
533DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
534{
535 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
536 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
537
538 toCommit->squash[tid] = true;
539 toCommit->squashedSeqNum[tid] = inst->seqNum;
540 toCommit->nextPC[tid] = inst->readPC();
531
532 toCommit->includeSquashInst[tid] = false;
533
534 wroteToTimeBuffer = true;
535}
536
537template<class Impl>
538void
539DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
540{
541 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
542 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
543
544 toCommit->squash[tid] = true;
545 toCommit->squashedSeqNum[tid] = inst->seqNum;
546 toCommit->nextPC[tid] = inst->readPC();
547#if ISA_HAS_DELAY_SLOT
548 toCommit->nextNPC[tid] = inst->readNextNPC();
549#endif
541
542 // Must include the broadcasted SN in the squash.
543 toCommit->includeSquashInst[tid] = true;
544
545 ldstQueue.setLoadBlockedHandled(tid);
546
547 wroteToTimeBuffer = true;
548}

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1337 unsigned tid = inst->threadNumber;
1338
1339 if (!fetchRedirect[tid]) {
1340
1341 if (inst->mispredicted()) {
1342 fetchRedirect[tid] = true;
1343
1344 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
550
551 // Must include the broadcasted SN in the squash.
552 toCommit->includeSquashInst[tid] = true;
553
554 ldstQueue.setLoadBlockedHandled(tid);
555
556 wroteToTimeBuffer = true;
557}

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1346 unsigned tid = inst->threadNumber;
1347
1348 if (!fetchRedirect[tid]) {
1349
1350 if (inst->mispredicted()) {
1351 fetchRedirect[tid] = true;
1352
1353 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1354 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC);
1345#if ISA_HAS_DELAY_SLOT
1346 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1347 inst->nextNPC);
1348#else
1349 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1350 inst->nextPC);
1351#endif
1352 // If incorrect, then signal the ROB that it must be squashed.
1353 squashDueToBranch(inst, tid);
1354
1355#if ISA_HAS_DELAY_SLOT
1356 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1357 inst->nextNPC);
1358#else
1359 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1360 inst->nextPC);
1361#endif
1362 // If incorrect, then signal the ROB that it must be squashed.
1363 squashDueToBranch(inst, tid);
1364
1355 if (inst->predTaken()) {
1365 if (inst->readPredTaken()) {
1356 predictedTakenIncorrect++;
1357 } else {
1358 predictedNotTakenIncorrect++;
1359 }
1360 } else if (ldstQueue.violation(tid)) {
1361 fetchRedirect[tid] = true;
1362
1363 // If there was an ordering violation, then get the

--- 248 unchanged lines hidden --- 		1366 predictedTakenIncorrect++;
1367 } else {
1368 predictedNotTakenIncorrect++;
1369 }
1370 } else if (ldstQueue.violation(tid)) {
1371 fetchRedirect[tid] = true;
1372
1373 // If there was an ordering violation, then get the

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