iew_impl.hh (3732:e84a6e9ebd3d) iew_impl.hh (3771:808a4c19cf34)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484 bool branch_taken = inst->readNextNPC() !=
485 (inst->readNextPC() + sizeof(TheISA::MachInst));
484 bool branch_taken =
485 (inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) &&
486 inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst)));
487 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
488 branch_taken ? "true": "false", inst->seqNum);
486
487 toCommit->branchTaken[tid] = branch_taken;
488
489
490 toCommit->branchTaken[tid] = branch_taken;
491
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491 if (inst->isCondDelaySlot() && branch_taken) {
492 bool squashDelaySlot =
493 (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
494 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
495 squashDelaySlot ? "true": "false", inst->seqNum);
496 toCommit->squashDelaySlot[tid] = squashDelaySlot;
497 //If we're squashing the delay slot, we need to pick back up at NextPC.
498 //Otherwise, NextPC isn't being squashed, so we should pick back up at
499 //NextNPC.
500 if (squashDelaySlot)
492 toCommit->nextPC[tid] = inst->readNextPC();
501 toCommit->nextPC[tid] = inst->readNextPC();
493 } else {
502 else
494 toCommit->nextPC[tid] = inst->readNextNPC();
503 toCommit->nextPC[tid] = inst->readNextNPC();
495 }
496#else
497 toCommit->branchTaken[tid] = inst->readNextPC() !=
498 (inst->readPC() + sizeof(TheISA::MachInst));
499 toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502 toCommit->includeSquashInst[tid] = false;
503

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509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
504#else
505 toCommit->branchTaken[tid] = inst->readNextPC() !=
506 (inst->readPC() + sizeof(TheISA::MachInst));
507 toCommit->nextPC[tid] = inst->readNextPC();
508#endif
509
510 toCommit->includeSquashInst[tid] = false;
511

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517DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
518{
519 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
520 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
521
522 toCommit->squash[tid] = true;
523 toCommit->squashedSeqNum[tid] = inst->seqNum;
524 toCommit->nextPC[tid] = inst->readNextPC();
517 toCommit->branchMispredict[tid] = false;
518
519 toCommit->includeSquashInst[tid] = false;
520
521 wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531 toCommit->squash[tid] = true;
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->nextPC[tid] = inst->readPC();
525
526 toCommit->includeSquashInst[tid] = false;
527
528 wroteToTimeBuffer = true;
529}
530
531template<class Impl>
532void
533DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
534{
535 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
536 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
537
538 toCommit->squash[tid] = true;
539 toCommit->squashedSeqNum[tid] = inst->seqNum;
540 toCommit->nextPC[tid] = inst->readPC();
534 toCommit->branchMispredict[tid] = false;
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;
542}

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1288 // If the store had a fault then it may not have a mem req
1289 if (!inst->isStoreConditional() && fault == NoFault) {
1290 inst->setExecuted();
1291
1292 instToCommit(inst);
1293 } else if (fault != NoFault) {
1294 // If the instruction faulted, then we need to send it along to commit
1295 // without the instruction completing.
541
542 // Must include the broadcasted SN in the squash.
543 toCommit->includeSquashInst[tid] = true;
544
545 ldstQueue.setLoadBlockedHandled(tid);
546
547 wroteToTimeBuffer = true;
548}

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1294 // If the store had a fault then it may not have a mem req
1295 if (!inst->isStoreConditional() && fault == NoFault) {
1296 inst->setExecuted();
1297
1298 instToCommit(inst);
1299 } else if (fault != NoFault) {
1300 // If the instruction faulted, then we need to send it along to commit
1301 // without the instruction completing.
1296 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1297 fault->name(), inst->seqNum);
1302 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
1298
1299 // Send this instruction to commit, also make sure iew stage
1300 // realizes there is activity.
1301 inst->setExecuted();
1302
1303 instToCommit(inst);
1304 activityThisCycle();
1305 }

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1326 // handle this if there hasn't already been something that
1327 // redirects fetch in this group of instructions.
1328
1329 // This probably needs to prioritize the redirects if a different
1330 // scheduler is used. Currently the scheduler schedules the oldest
1331 // instruction first, so the branch resolution order will be correct.
1332 unsigned tid = inst->threadNumber;
1333
1303
1304 // Send this instruction to commit, also make sure iew stage
1305 // realizes there is activity.
1306 inst->setExecuted();
1307
1308 instToCommit(inst);
1309 activityThisCycle();
1310 }

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1331 // handle this if there hasn't already been something that
1332 // redirects fetch in this group of instructions.
1333
1334 // This probably needs to prioritize the redirects if a different
1335 // scheduler is used. Currently the scheduler schedules the oldest
1336 // instruction first, so the branch resolution order will be correct.
1337 unsigned tid = inst->threadNumber;
1338
1334 if (!fetchRedirect[tid] ||
1335 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1339 if (!fetchRedirect[tid]) {
1336
1337 if (inst->mispredicted()) {
1338 fetchRedirect[tid] = true;
1339
1340 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1341#if ISA_HAS_DELAY_SLOT
1342 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1343 inst->nextNPC);

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1349 squashDueToBranch(inst, tid);
1350
1351 if (inst->predTaken()) {
1352 predictedTakenIncorrect++;
1353 } else {
1354 predictedNotTakenIncorrect++;
1355 }
1356 } else if (ldstQueue.violation(tid)) {
1340
1341 if (inst->mispredicted()) {
1342 fetchRedirect[tid] = true;
1343
1344 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1345#if ISA_HAS_DELAY_SLOT
1346 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1347 inst->nextNPC);

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1353 squashDueToBranch(inst, tid);
1354
1355 if (inst->predTaken()) {
1356 predictedTakenIncorrect++;
1357 } else {
1358 predictedNotTakenIncorrect++;
1359 }
1360 } else if (ldstQueue.violation(tid)) {
1361 fetchRedirect[tid] = true;
1362
1357 // If there was an ordering violation, then get the
1358 // DynInst that caused the violation. Note that this
1359 // clears the violation signal.
1360 DynInstPtr violator;
1361 violator = ldstQueue.getMemDepViolator(tid);
1362
1363 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1364 "%#x, inst PC: %#x. Addr is: %#x.\n",
1365 violator->readPC(), inst->readPC(), inst->physEffAddr);
1366
1363 // If there was an ordering violation, then get the
1364 // DynInst that caused the violation. Note that this
1365 // clears the violation signal.
1366 DynInstPtr violator;
1367 violator = ldstQueue.getMemDepViolator(tid);
1368
1369 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1370 "%#x, inst PC: %#x. Addr is: %#x.\n",
1371 violator->readPC(), inst->readPC(), inst->physEffAddr);
1372
1367 // Ensure the violating instruction is older than
1368 // current squash
1369 if (fetchRedirect[tid] &&
1370 violator->seqNum >= toCommit->squashedSeqNum[tid])
1371 continue;
1372
1373 fetchRedirect[tid] = true;
1374
1375 // Tell the instruction queue that a violation has occured.
1376 instQueue.violation(inst, violator);
1377
1378 // Squash.
1379 squashDueToMemOrder(inst,tid);
1380
1381 ++memOrderViolationEvents;
1382 } else if (ldstQueue.loadBlocked(tid) &&

--- 231 unchanged lines hidden --- 		1373 // Tell the instruction queue that a violation has occured.
1374 instQueue.violation(inst, violator);
1375
1376 // Squash.
1377 squashDueToMemOrder(inst,tid);
1378
1379 ++memOrderViolationEvents;
1380 } else if (ldstQueue.loadBlocked(tid) &&

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