iew_impl.hh (3221:669a04468c0d) iew_impl.hh (3732:e84a6e9ebd3d)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
517 toCommit->branchMispredict[tid] = false;
517
518 toCommit->includeSquashInst[tid] = false;
519
520 wroteToTimeBuffer = true;
521}
522
523template<class Impl>
524void
525DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
526{
527 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
528 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
529
530 toCommit->squash[tid] = true;
531 toCommit->squashedSeqNum[tid] = inst->seqNum;
532 toCommit->nextPC[tid] = inst->readPC();
518
519 toCommit->includeSquashInst[tid] = false;
520
521 wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531 toCommit->squash[tid] = true;
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->nextPC[tid] = inst->readPC();
534 toCommit->branchMispredict[tid] = false;
533
534 // Must include the broadcasted SN in the squash.
535 toCommit->includeSquashInst[tid] = true;
536
537 ldstQueue.setLoadBlockedHandled(tid);
538
539 wroteToTimeBuffer = true;
540}

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1286 // If the store had a fault then it may not have a mem req
1287 if (!inst->isStoreConditional() && fault == NoFault) {
1288 inst->setExecuted();
1289
1290 instToCommit(inst);
1291 } else if (fault != NoFault) {
1292 // If the instruction faulted, then we need to send it along to commit
1293 // without the instruction completing.
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;
542}

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1288 // If the store had a fault then it may not have a mem req
1289 if (!inst->isStoreConditional() && fault == NoFault) {
1290 inst->setExecuted();
1291
1292 instToCommit(inst);
1293 } else if (fault != NoFault) {
1294 // If the instruction faulted, then we need to send it along to commit
1295 // without the instruction completing.
1294 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
1296 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1297 fault->name(), inst->seqNum);
1295
1296 // Send this instruction to commit, also make sure iew stage
1297 // realizes there is activity.
1298 inst->setExecuted();
1299
1300 instToCommit(inst);
1301 activityThisCycle();
1302 }

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1323 // handle this if there hasn't already been something that
1324 // redirects fetch in this group of instructions.
1325
1326 // This probably needs to prioritize the redirects if a different
1327 // scheduler is used. Currently the scheduler schedules the oldest
1328 // instruction first, so the branch resolution order will be correct.
1329 unsigned tid = inst->threadNumber;
1330
1298
1299 // Send this instruction to commit, also make sure iew stage
1300 // realizes there is activity.
1301 inst->setExecuted();
1302
1303 instToCommit(inst);
1304 activityThisCycle();
1305 }

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1326 // handle this if there hasn't already been something that
1327 // redirects fetch in this group of instructions.
1328
1329 // This probably needs to prioritize the redirects if a different
1330 // scheduler is used. Currently the scheduler schedules the oldest
1331 // instruction first, so the branch resolution order will be correct.
1332 unsigned tid = inst->threadNumber;
1333
1331 if (!fetchRedirect[tid]) {
1334 if (!fetchRedirect[tid] ||
1335 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1332
1333 if (inst->mispredicted()) {
1334 fetchRedirect[tid] = true;
1335
1336 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1337#if ISA_HAS_DELAY_SLOT
1338 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1339 inst->nextNPC);

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1345 squashDueToBranch(inst, tid);
1346
1347 if (inst->predTaken()) {
1348 predictedTakenIncorrect++;
1349 } else {
1350 predictedNotTakenIncorrect++;
1351 }
1352 } else if (ldstQueue.violation(tid)) {
1336
1337 if (inst->mispredicted()) {
1338 fetchRedirect[tid] = true;
1339
1340 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1341#if ISA_HAS_DELAY_SLOT
1342 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1343 inst->nextNPC);

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1349 squashDueToBranch(inst, tid);
1350
1351 if (inst->predTaken()) {
1352 predictedTakenIncorrect++;
1353 } else {
1354 predictedNotTakenIncorrect++;
1355 }
1356 } else if (ldstQueue.violation(tid)) {
1353 fetchRedirect[tid] = true;
1354
1355 // If there was an ordering violation, then get the
1356 // DynInst that caused the violation. Note that this
1357 // clears the violation signal.
1358 DynInstPtr violator;
1359 violator = ldstQueue.getMemDepViolator(tid);
1360
1361 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1362 "%#x, inst PC: %#x. Addr is: %#x.\n",
1363 violator->readPC(), inst->readPC(), inst->physEffAddr);
1364
1357 // If there was an ordering violation, then get the
1358 // DynInst that caused the violation. Note that this
1359 // clears the violation signal.
1360 DynInstPtr violator;
1361 violator = ldstQueue.getMemDepViolator(tid);
1362
1363 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1364 "%#x, inst PC: %#x. Addr is: %#x.\n",
1365 violator->readPC(), inst->readPC(), inst->physEffAddr);
1366
1367 // Ensure the violating instruction is older than
1368 // current squash
1369 if (fetchRedirect[tid] &&
1370 violator->seqNum >= toCommit->squashedSeqNum[tid])
1371 continue;
1372
1373 fetchRedirect[tid] = true;
1374
1365 // Tell the instruction queue that a violation has occured.
1366 instQueue.violation(inst, violator);
1367
1368 // Squash.
1369 squashDueToMemOrder(inst,tid);
1370
1371 ++memOrderViolationEvents;
1372 } else if (ldstQueue.loadBlocked(tid) &&

--- 231 unchanged lines hidden --- 		1375 // Tell the instruction queue that a violation has occured.
1376 instQueue.violation(inst, violator);
1377
1378 // Squash.
1379 squashDueToMemOrder(inst,tid);
1380
1381 ++memOrderViolationEvents;
1382 } else if (ldstQueue.loadBlocked(tid) &&

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