iew_impl.hh (3126:756092c6383c) iew_impl.hh (3221:669a04468c0d)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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595{
596 instQueue.replayMemInst(inst);
597}
598
599template<class Impl>
600void
601DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
602{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 586 unchanged lines hidden (view full) ---

595{
596 instQueue.replayMemInst(inst);
597}
598
599template<class Impl>
600void
601DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
602{
603 // This function should not be called after writebackInsts in a
604 // single cycle. That will cause problems with an instruction
605 // being added to the queue to commit without being processed by
606 // writebackInsts prior to being sent to commit.
607
603 // First check the time slot that this instruction will write
604 // to. If there are free write ports at the time, then go ahead
605 // and write the instruction to that time. If there are not,
606 // keep looking back to see where's the first time there's a
607 // free slot.
608 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
609 ++wbNumInst;
610 if (wbNumInst == wbWidth) {

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1281 // If the store had a fault then it may not have a mem req
1282 if (!inst->isStoreConditional() && fault == NoFault) {
1283 inst->setExecuted();
1284
1285 instToCommit(inst);
1286 } else if (fault != NoFault) {
1287 // If the instruction faulted, then we need to send it along to commit
1288 // without the instruction completing.
608 // First check the time slot that this instruction will write
609 // to. If there are free write ports at the time, then go ahead
610 // and write the instruction to that time. If there are not,
611 // keep looking back to see where's the first time there's a
612 // free slot.
613 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
614 ++wbNumInst;
615 if (wbNumInst == wbWidth) {

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1286 // If the store had a fault then it may not have a mem req
1287 if (!inst->isStoreConditional() && fault == NoFault) {
1288 inst->setExecuted();
1289
1290 instToCommit(inst);
1291 } else if (fault != NoFault) {
1292 // If the instruction faulted, then we need to send it along to commit
1293 // without the instruction completing.
1294 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
1289
1290 // Send this instruction to commit, also make sure iew stage
1291 // realizes there is activity.
1292 inst->setExecuted();
1293
1294 instToCommit(inst);
1295 activityThisCycle();
1296 }

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1296 // Send this instruction to commit, also make sure iew stage
1297 // realizes there is activity.
1298 inst->setExecuted();
1299
1300 instToCommit(inst);
1301 activityThisCycle();
1302 }

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