iew_impl.hh (3093:b09c33e66bce) | iew_impl.hh (3125:febd811bccc6) |
---|---|
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 148 unchanged lines hidden (view full) --- 157 158 branchMispredicts 159 .name(name() + ".branchMispredicts") 160 .desc("Number of branch mispredicts detected at execute"); 161 162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 163 164 iewExecutedInsts | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 148 unchanged lines hidden (view full) --- 157 158 branchMispredicts 159 .name(name() + ".branchMispredicts") 160 .desc("Number of branch mispredicts detected at execute"); 161 162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 163 164 iewExecutedInsts |
165 .name(name() + ".EXEC:insts") | 165 .name(name() + ".iewExecutedInsts") |
166 .desc("Number of executed instructions"); 167 168 iewExecLoadInsts 169 .init(cpu->number_of_threads) | 166 .desc("Number of executed instructions"); 167 168 iewExecLoadInsts 169 .init(cpu->number_of_threads) |
170 .name(name() + ".EXEC:loads") | 170 .name(name() + ".iewExecLoadInsts") |
171 .desc("Number of load instructions executed") 172 .flags(total); 173 174 iewExecSquashedInsts | 171 .desc("Number of load instructions executed") 172 .flags(total); 173 174 iewExecSquashedInsts |
175 .name(name() + ".EXEC:squashedInsts") | 175 .name(name() + ".iewExecSquashedInsts") |
176 .desc("Number of squashed instructions skipped in execute"); 177 178 iewExecutedSwp 179 .init(cpu->number_of_threads) 180 .name(name() + ".EXEC:swp") 181 .desc("number of swp insts executed") 182 .flags(total); 183 --- 183 unchanged lines hidden (view full) --- 367} 368 369template <class Impl> 370void 371DefaultIEW<Impl>::switchOut() 372{ 373 // Clear any state. 374 switchedOut = true; | 176 .desc("Number of squashed instructions skipped in execute"); 177 178 iewExecutedSwp 179 .init(cpu->number_of_threads) 180 .name(name() + ".EXEC:swp") 181 .desc("number of swp insts executed") 182 .flags(total); 183 --- 183 unchanged lines hidden (view full) --- 367} 368 369template <class Impl> 370void 371DefaultIEW<Impl>::switchOut() 372{ 373 // Clear any state. 374 switchedOut = true; |
375 assert(insts[0].empty()); 376 assert(skidBuffer[0].empty()); |
|
375 376 instQueue.switchOut(); 377 ldstQueue.switchOut(); 378 fuPool->switchOut(); 379 380 for (int i = 0; i < numThreads; i++) { 381 while (!insts[i].empty()) 382 insts[i].pop(); --- 22 unchanged lines hidden (view full) --- 405 for (int i=0; i < numThreads; i++) { 406 dispatchStatus[i] = Running; 407 stalls[i].commit = false; 408 fetchRedirect[i] = false; 409 } 410 411 updateLSQNextCycle = false; 412 | 377 378 instQueue.switchOut(); 379 ldstQueue.switchOut(); 380 fuPool->switchOut(); 381 382 for (int i = 0; i < numThreads; i++) { 383 while (!insts[i].empty()) 384 insts[i].pop(); --- 22 unchanged lines hidden (view full) --- 407 for (int i=0; i < numThreads; i++) { 408 dispatchStatus[i] = Running; 409 stalls[i].commit = false; 410 fetchRedirect[i] = false; 411 } 412 413 updateLSQNextCycle = false; 414 |
413 // @todo: Fix hardcoded number | |
414 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 415 issueToExecQueue.advance(); 416 } 417} 418 419template<class Impl> 420void 421DefaultIEW<Impl>::squash(unsigned tid) --- 184 unchanged lines hidden (view full) --- 606 // free slot. 607 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 608 ++wbNumInst; 609 if (wbNumInst == wbWidth) { 610 ++wbCycle; 611 wbNumInst = 0; 612 } 613 | 415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 416 issueToExecQueue.advance(); 417 } 418} 419 420template<class Impl> 421void 422DefaultIEW<Impl>::squash(unsigned tid) --- 184 unchanged lines hidden (view full) --- 607 // free slot. 608 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 609 ++wbNumInst; 610 if (wbNumInst == wbWidth) { 611 ++wbCycle; 612 wbNumInst = 0; 613 } 614 |
614 assert((wbCycle * wbWidth + wbNumInst) < wbMax); | 615 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); |
615 } 616 | 616 } 617 |
618 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 619 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); |
|
617 // Add finished instruction to queue to commit. 618 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 619 (*iewQueue)[wbCycle].size++; 620} 621 622template <class Impl> 623unsigned 624DefaultIEW<Impl>::validInstsFromRename() --- 273 unchanged lines hidden (view full) --- 898 toRename->iewInfo[tid].dispatched++; 899 900 insts[tid].pop(); 901 } 902} 903 904template <class Impl> 905void | 620 // Add finished instruction to queue to commit. 621 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 622 (*iewQueue)[wbCycle].size++; 623} 624 625template <class Impl> 626unsigned 627DefaultIEW<Impl>::validInstsFromRename() --- 273 unchanged lines hidden (view full) --- 901 toRename->iewInfo[tid].dispatched++; 902 903 insts[tid].pop(); 904 } 905} 906 907template <class Impl> 908void |
909DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 910{ 911 while (!insts[tid].empty()) { 912 if (insts[tid].front()->isLoad() || 913 insts[tid].front()->isStore() ) { 914 toRename->iewInfo[tid].dispatchedToLSQ++; 915 } 916 917 toRename->iewInfo[tid].dispatched++; 918 919 insts[tid].pop(); 920 } 921} 922 923template <class Impl> 924void |
|
906DefaultIEW<Impl>::wakeCPU() 907{ 908 cpu->wakeCPU(); 909} 910 911template <class Impl> 912void 913DefaultIEW<Impl>::activityThisCycle() --- 354 unchanged lines hidden (view full) --- 1268 "reference.\n"); 1269 1270 // Tell the LDSTQ to execute this instruction (if it is a load). 1271 if (inst->isLoad()) { 1272 // Loads will mark themselves as executed, and their writeback 1273 // event adds the instruction to the queue to commit 1274 fault = ldstQueue.executeLoad(inst); 1275 } else if (inst->isStore()) { | 925DefaultIEW<Impl>::wakeCPU() 926{ 927 cpu->wakeCPU(); 928} 929 930template <class Impl> 931void 932DefaultIEW<Impl>::activityThisCycle() --- 354 unchanged lines hidden (view full) --- 1287 "reference.\n"); 1288 1289 // Tell the LDSTQ to execute this instruction (if it is a load). 1290 if (inst->isLoad()) { 1291 // Loads will mark themselves as executed, and their writeback 1292 // event adds the instruction to the queue to commit 1293 fault = ldstQueue.executeLoad(inst); 1294 } else if (inst->isStore()) { |
1276 ldstQueue.executeStore(inst); | 1295 fault = ldstQueue.executeStore(inst); |
1277 1278 // If the store had a fault then it may not have a mem req | 1296 1297 // If the store had a fault then it may not have a mem req |
1279 if (inst->req && !(inst->req->getFlags() & LOCKED)) { | 1298 if (!inst->isStoreConditional() && fault == NoFault) { |
1280 inst->setExecuted(); 1281 1282 instToCommit(inst); | 1299 inst->setExecuted(); 1300 1301 instToCommit(inst); |
1302 } else if (fault != NoFault) { 1303 // If the instruction faulted, then we need to send it along to commit 1304 // without the instruction completing. 1305 1306 // Send this instruction to commit, also make sure iew stage 1307 // realizes there is activity. 1308 inst->setExecuted(); 1309 1310 instToCommit(inst); 1311 activityThisCycle(); |
|
1283 } 1284 1285 // Store conditionals will mark themselves as 1286 // executed, and their writeback event will add the 1287 // instruction to the queue to commit. 1288 } else { 1289 panic("Unexpected memory type!\n"); 1290 } --- 108 unchanged lines hidden (view full) --- 1399 1400 iewInstsToCommit[tid]++; 1401 1402 // Some instructions will be sent to commit without having 1403 // executed because they need commit to handle them. 1404 // E.g. Uncached loads have not actually executed when they 1405 // are first sent to commit. Instead commit must tell the LSQ 1406 // when it's ready to execute the uncached load. | 1312 } 1313 1314 // Store conditionals will mark themselves as 1315 // executed, and their writeback event will add the 1316 // instruction to the queue to commit. 1317 } else { 1318 panic("Unexpected memory type!\n"); 1319 } --- 108 unchanged lines hidden (view full) --- 1428 1429 iewInstsToCommit[tid]++; 1430 1431 // Some instructions will be sent to commit without having 1432 // executed because they need commit to handle them. 1433 // E.g. Uncached loads have not actually executed when they 1434 // are first sent to commit. Instead commit must tell the LSQ 1435 // when it's ready to execute the uncached load. |
1407 if (!inst->isSquashed() && inst->isExecuted()) { | 1436 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { |
1408 int dependents = instQueue.wakeDependents(inst); 1409 1410 for (int i = 0; i < inst->numDestRegs(); i++) { 1411 //mark as Ready 1412 DPRINTF(IEW,"Setting Destination Register %i\n", 1413 inst->renamedDestRegIdx(i)); 1414 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1415 } --- 169 unchanged lines hidden --- | 1437 int dependents = instQueue.wakeDependents(inst); 1438 1439 for (int i = 0; i < inst->numDestRegs(); i++) { 1440 //mark as Ready 1441 DPRINTF(IEW,"Setting Destination Register %i\n", 1442 inst->renamedDestRegIdx(i)); 1443 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1444 } --- 169 unchanged lines hidden --- |