iew_impl.hh (2980:eab855f06b79) iew_impl.hh (3093:b09c33e66bce)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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422{
423 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
424 tid);
425
426 // Tell the IQ to start squashing.
427 instQueue.squash(tid);
428
429 // Tell the LDSTQ to start squashing.
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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422{
423 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
424 tid);
425
426 // Tell the IQ to start squashing.
427 instQueue.squash(tid);
428
429 // Tell the LDSTQ to start squashing.
430#if THE_ISA == ALPHA_ISA
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432#else
430#if ISA_HAS_DELAY_SLOT
433 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
431 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
432#else
433 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
434#endif
435 updatedQueues = true;
436
437 // Clear the skid buffer in case it has any data in it.
438 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
439 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
440
441 while (!skidBuffer[tid].empty()) {
434#endif
435 updatedQueues = true;
436
437 // Clear the skid buffer in case it has any data in it.
438 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
439 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
440
441 while (!skidBuffer[tid].empty()) {
442#if THE_ISA != ALPHA_ISA
442#if ISA_HAS_DELAY_SLOT
443 if (skidBuffer[tid].front()->seqNum <=
444 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
445 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
446 "that occur before delay slot [sn:%i].\n",
447 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
448 tid);
449 break;
450 } else {

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474 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
475 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
476
477 toCommit->squash[tid] = true;
478 toCommit->squashedSeqNum[tid] = inst->seqNum;
479 toCommit->mispredPC[tid] = inst->readPC();
480 toCommit->branchMispredict[tid] = true;
481
443 if (skidBuffer[tid].front()->seqNum <=
444 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
445 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
446 "that occur before delay slot [sn:%i].\n",
447 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
448 tid);
449 break;
450 } else {

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474 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
475 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
476
477 toCommit->squash[tid] = true;
478 toCommit->squashedSeqNum[tid] = inst->seqNum;
479 toCommit->mispredPC[tid] = inst->readPC();
480 toCommit->branchMispredict[tid] = true;
481
482#if THE_ISA == ALPHA_ISA
483 toCommit->branchTaken[tid] = inst->readNextPC() !=
484 (inst->readPC() + sizeof(TheISA::MachInst));
485 toCommit->nextPC[tid] = inst->readNextPC();
486#else
482#if ISA_HAS_DELAY_SLOT
487 bool branch_taken = inst->readNextNPC() !=
488 (inst->readNextPC() + sizeof(TheISA::MachInst));
489
490 toCommit->branchTaken[tid] = branch_taken;
491
492 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
493
494 if (inst->isCondDelaySlot() && branch_taken) {
495 toCommit->nextPC[tid] = inst->readNextPC();
496 } else {
497 toCommit->nextPC[tid] = inst->readNextNPC();
498 }
483 bool branch_taken = inst->readNextNPC() !=
484 (inst->readNextPC() + sizeof(TheISA::MachInst));
485
486 toCommit->branchTaken[tid] = branch_taken;
487
488 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
489
490 if (inst->isCondDelaySlot() && branch_taken) {
491 toCommit->nextPC[tid] = inst->readNextPC();
492 } else {
493 toCommit->nextPC[tid] = inst->readNextNPC();
494 }
495#else
496 toCommit->branchTaken[tid] = inst->readNextPC() !=
497 (inst->readPC() + sizeof(TheISA::MachInst));
498 toCommit->nextPC[tid] = inst->readNextPC();
499#endif
500
501 toCommit->includeSquashInst[tid] = false;
502
503 wroteToTimeBuffer = true;
504}
505
506template<class Impl>

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855}
856
857template <class Impl>
858void
859DefaultIEW<Impl>::sortInsts()
860{
861 int insts_from_rename = fromRename->size;
862#ifdef DEBUG
499#endif
500
501 toCommit->includeSquashInst[tid] = false;
502
503 wroteToTimeBuffer = true;
504}
505
506template<class Impl>

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855}
856
857template <class Impl>
858void
859DefaultIEW<Impl>::sortInsts()
860{
861 int insts_from_rename = fromRename->size;
862#ifdef DEBUG
863#if THE_ISA == ALPHA_ISA
863#if !ISA_HAS_DELAY_SLOT
864 for (int i = 0; i < numThreads; i++)
865 assert(insts[i].empty());
866#endif
867#endif
868 for (int i = 0; i < insts_from_rename; ++i) {
869 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
870 }
871}
872
873template <class Impl>
874void
875DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
876{
877 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
878 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
879
880 while (!insts[tid].empty()) {
864 for (int i = 0; i < numThreads; i++)
865 assert(insts[i].empty());
866#endif
867#endif
868 for (int i = 0; i < insts_from_rename; ++i) {
869 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
870 }
871}
872
873template <class Impl>
874void
875DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
876{
877 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
878 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
879
880 while (!insts[tid].empty()) {
881
882#if THE_ISA != ALPHA_ISA
881#if ISA_HAS_DELAY_SLOT
883 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
884 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
885 " that occurs at or before delay slot [sn:%i].\n",
886 tid, bdelayDoneSeqNum[tid]);
887 break;
888 } else {
889 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
890 "[sn:%i].\n", tid, insts[tid].front()->seqNum);

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1311 unsigned tid = inst->threadNumber;
1312
1313 if (!fetchRedirect[tid]) {
1314
1315 if (inst->mispredicted()) {
1316 fetchRedirect[tid] = true;
1317
1318 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
882 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
883 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
884 " that occurs at or before delay slot [sn:%i].\n",
885 tid, bdelayDoneSeqNum[tid]);
886 break;
887 } else {
888 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
889 "[sn:%i].\n", tid, insts[tid].front()->seqNum);

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1310 unsigned tid = inst->threadNumber;
1311
1312 if (!fetchRedirect[tid]) {
1313
1314 if (inst->mispredicted()) {
1315 fetchRedirect[tid] = true;
1316
1317 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1319#if THE_ISA == ALPHA_ISA
1318#if ISA_HAS_DELAY_SLOT
1320 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1319 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1321 inst->nextPC);
1320 inst->nextNPC);
1322#else
1323 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1321#else
1322 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1324 inst->nextNPC);
1323 inst->nextPC);
1325#endif
1326 // If incorrect, then signal the ROB that it must be squashed.
1327 squashDueToBranch(inst, tid);
1328
1329 if (inst->predTaken()) {
1330 predictedTakenIncorrect++;
1331 } else {
1332 predictedNotTakenIncorrect++;

--- 253 unchanged lines hidden --- 		1324#endif
1325 // If incorrect, then signal the ROB that it must be squashed.
1326 squashDueToBranch(inst, tid);
1327
1328 if (inst->predTaken()) {
1329 predictedTakenIncorrect++;
1330 } else {
1331 predictedNotTakenIncorrect++;

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