iew_impl.hh (2873:1377a68cd00e) iew_impl.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68
69 instQueue.setIEW(this);
70 ldstQueue.setIEW(this);
71
72 for (int i=0; i < numThreads; i++) {
73 dispatchStatus[i] = Running;
74 stalls[i].commit = false;
75 fetchRedirect[i] = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68
69 instQueue.setIEW(this);
70 ldstQueue.setIEW(this);
71
72 for (int i=0; i < numThreads; i++) {
73 dispatchStatus[i] = Running;
74 stalls[i].commit = false;
75 fetchRedirect[i] = false;
76 bdelayDoneSeqNum[i] = 0;
76 }
77
78 wbMax = wbWidth * params->wbDepth;
79
80 updateLSQNextCycle = false;
81
82 ableToIssue = true;
83

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423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
77 }
78
79 wbMax = wbWidth * params->wbDepth;
80
81 updateLSQNextCycle = false;
82
83 ableToIssue = true;
84

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424{
425 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
426 tid);
427
428 // Tell the IQ to start squashing.
429 instQueue.squash(tid);
430
431 // Tell the LDSTQ to start squashing.
432#if THE_ISA == ALPHA_ISA
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
433 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432
434#else
435 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
436#endif
433 updatedQueues = true;
434
435 // Clear the skid buffer in case it has any data in it.
437 updatedQueues = true;
438
439 // Clear the skid buffer in case it has any data in it.
436 while (!skidBuffer[tid].empty()) {
440 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
441 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
437
442
443 while (!skidBuffer[tid].empty()) {
444#if THE_ISA != ALPHA_ISA
445 if (skidBuffer[tid].front()->seqNum <=
446 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
447 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
448 "that occur before delay slot [sn:%i].\n",
449 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
450 tid);
451 break;
452 } else {
453 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
454 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
455 }
456#endif
438 if (skidBuffer[tid].front()->isLoad() ||
439 skidBuffer[tid].front()->isStore() ) {
440 toRename->iewInfo[tid].dispatchedToLSQ++;
441 }
442
443 toRename->iewInfo[tid].dispatched++;
444
445 skidBuffer[tid].pop();
446 }
447
457 if (skidBuffer[tid].front()->isLoad() ||
458 skidBuffer[tid].front()->isStore() ) {
459 toRename->iewInfo[tid].dispatchedToLSQ++;
460 }
461
462 toRename->iewInfo[tid].dispatched++;
463
464 skidBuffer[tid].pop();
465 }
466
467 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
468
448 emptyRenameInsts(tid);
449}
450
451template<class Impl>
452void
453DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
454{
455 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
456 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
457
458 toCommit->squash[tid] = true;
459 toCommit->squashedSeqNum[tid] = inst->seqNum;
460 toCommit->mispredPC[tid] = inst->readPC();
469 emptyRenameInsts(tid);
470}
471
472template<class Impl>
473void
474DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
475{
476 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
477 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
478
479 toCommit->squash[tid] = true;
480 toCommit->squashedSeqNum[tid] = inst->seqNum;
481 toCommit->mispredPC[tid] = inst->readPC();
461 toCommit->nextPC[tid] = inst->readNextPC();
462 toCommit->branchMispredict[tid] = true;
482 toCommit->branchMispredict[tid] = true;
483
484#if THE_ISA == ALPHA_ISA
463 toCommit->branchTaken[tid] = inst->readNextPC() !=
464 (inst->readPC() + sizeof(TheISA::MachInst));
485 toCommit->branchTaken[tid] = inst->readNextPC() !=
486 (inst->readPC() + sizeof(TheISA::MachInst));
487 toCommit->nextPC[tid] = inst->readNextPC();
488#else
489 bool branch_taken = inst->readNextNPC() !=
490 (inst->readNextPC() + sizeof(TheISA::MachInst));
465
491
492 toCommit->branchTaken[tid] = branch_taken;
493
494 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
495
496 if (inst->isCondDelaySlot() && branch_taken) {
497 toCommit->nextPC[tid] = inst->readNextPC();
498 } else {
499 toCommit->nextPC[tid] = inst->readNextNPC();
500 }
501#endif
502
466 toCommit->includeSquashInst[tid] = false;
467
468 wroteToTimeBuffer = true;
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)

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820}
821
822template <class Impl>
823void
824DefaultIEW<Impl>::sortInsts()
825{
826 int insts_from_rename = fromRename->size;
827#ifdef DEBUG
503 toCommit->includeSquashInst[tid] = false;
504
505 wroteToTimeBuffer = true;
506}
507
508template<class Impl>
509void
510DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)

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857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::sortInsts()
862{
863 int insts_from_rename = fromRename->size;
864#ifdef DEBUG
865#if THE_ISA == ALPHA_ISA
828 for (int i = 0; i < numThreads; i++)
829 assert(insts[i].empty());
830#endif
866 for (int i = 0; i < numThreads; i++)
867 assert(insts[i].empty());
868#endif
869#endif
831 for (int i = 0; i < insts_from_rename; ++i) {
832 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
833 }
834}
835
836template <class Impl>
837void
838DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
839{
870 for (int i = 0; i < insts_from_rename; ++i) {
871 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
872 }
873}
874
875template <class Impl>
876void
877DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
878{
879 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
880 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
881
840 while (!insts[tid].empty()) {
882 while (!insts[tid].empty()) {
883
884#if THE_ISA != ALPHA_ISA
885 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
886 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
887 " that occurs at or before delay slot [sn:%i].\n",
888 tid, bdelayDoneSeqNum[tid]);
889 break;
890 } else {
891 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
892 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
893 }
894#endif
895
841 if (insts[tid].front()->isLoad() ||
842 insts[tid].front()->isStore() ) {
843 toRename->iewInfo[tid].dispatchedToLSQ++;
844 }
845
846 toRename->iewInfo[tid].dispatched++;
847
848 insts[tid].pop();

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1115 insts_to_dispatch.pop();
1116
1117 toRename->iewInfo[tid].dispatched++;
1118
1119 ++iewDispatchedInsts;
1120 }
1121
1122 if (!insts_to_dispatch.empty()) {
896 if (insts[tid].front()->isLoad() ||
897 insts[tid].front()->isStore() ) {
898 toRename->iewInfo[tid].dispatchedToLSQ++;
899 }
900
901 toRename->iewInfo[tid].dispatched++;
902
903 insts[tid].pop();

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1170 insts_to_dispatch.pop();
1171
1172 toRename->iewInfo[tid].dispatched++;
1173
1174 ++iewDispatchedInsts;
1175 }
1176
1177 if (!insts_to_dispatch.empty()) {
1123 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1178 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1124 block(tid);
1125 toRename->iewUnblock[tid] = false;
1126 }
1127
1128 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1129 dispatchStatus[tid] = Running;
1130
1131 updatedQueues = true;

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1258 unsigned tid = inst->threadNumber;
1259
1260 if (!fetchRedirect[tid]) {
1261
1262 if (inst->mispredicted()) {
1263 fetchRedirect[tid] = true;
1264
1265 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1179 block(tid);
1180 toRename->iewUnblock[tid] = false;
1181 }
1182
1183 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1184 dispatchStatus[tid] = Running;
1185
1186 updatedQueues = true;

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1313 unsigned tid = inst->threadNumber;
1314
1315 if (!fetchRedirect[tid]) {
1316
1317 if (inst->mispredicted()) {
1318 fetchRedirect[tid] = true;
1319
1320 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1321#if THE_ISA == ALPHA_ISA
1266 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1267 inst->nextPC);
1322 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1323 inst->nextPC);
1268
1324#else
1325 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1326 inst->nextNPC);
1327#endif
1269 // If incorrect, then signal the ROB that it must be squashed.
1270 squashDueToBranch(inst, tid);
1271
1272 if (inst->predTaken()) {
1273 predictedTakenIncorrect++;
1274 } else {
1275 predictedNotTakenIncorrect++;
1276 }

--- 252 unchanged lines hidden --- 		1328 // If incorrect, then signal the ROB that it must be squashed.
1329 squashDueToBranch(inst, tid);
1330
1331 if (inst->predTaken()) {
1332 predictedTakenIncorrect++;
1333 } else {
1334 predictedNotTakenIncorrect++;
1335 }

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