iew_impl.hh (2733:e0eac8fc5774) iew_impl.hh (2820:7fde0b0f8f78)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 36 unchanged lines hidden (view full) ---

45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 issueReadWidth(params->issueWidth),
53 dispatchWidth(params->dispatchWidth),
54 issueWidth(params->issueWidth),
54 issueWidth(params->issueWidth),
55 wbOutstanding(0),
56 wbWidth(params->wbWidth),
55 numThreads(params->numberOfThreads),
56 switchedOut(false)
57{
58 _status = Active;
59 exeStatus = Running;
60 wbStatus = Idle;
61
62 // Setup wire to read instructions coming from issue.

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69 ldstQueue.setIEW(this);
70
71 for (int i=0; i < numThreads; i++) {
72 dispatchStatus[i] = Running;
73 stalls[i].commit = false;
74 fetchRedirect[i] = false;
75 }
76
57 numThreads(params->numberOfThreads),
58 switchedOut(false)
59{
60 _status = Active;
61 exeStatus = Running;
62 wbStatus = Idle;
63
64 // Setup wire to read instructions coming from issue.

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71 ldstQueue.setIEW(this);
72
73 for (int i=0; i < numThreads; i++) {
74 dispatchStatus[i] = Running;
75 stalls[i].commit = false;
76 fetchRedirect[i] = false;
77 }
78
79 wbMax = wbWidth * params->wbDepth;
80
77 updateLSQNextCycle = false;
78
81 updateLSQNextCycle = false;
82
83 ableToIssue = true;
84
79 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
80}
81
82template <class Impl>
83std::string
84DefaultIEW<Impl>::name() const
85{
86 return cpu->name() + ".iew";

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554{
555 // First check the time slot that this instruction will write
556 // to. If there are free write ports at the time, then go ahead
557 // and write the instruction to that time. If there are not,
558 // keep looking back to see where's the first time there's a
559 // free slot.
560 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
561 ++wbNumInst;
85 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
86}
87
88template <class Impl>
89std::string
90DefaultIEW<Impl>::name() const
91{
92 return cpu->name() + ".iew";

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560{
561 // First check the time slot that this instruction will write
562 // to. If there are free write ports at the time, then go ahead
563 // and write the instruction to that time. If there are not,
564 // keep looking back to see where's the first time there's a
565 // free slot.
566 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
567 ++wbNumInst;
562 if (wbNumInst == issueWidth) {
568 if (wbNumInst == wbWidth) {
563 ++wbCycle;
564 wbNumInst = 0;
565 }
566
569 ++wbCycle;
570 wbNumInst = 0;
571 }
572
567 assert(wbCycle < 5);
573 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
568 }
569
570 // Add finished instruction to queue to commit.
571 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
572 (*iewQueue)[wbCycle].size++;
573}
574
575template <class Impl>

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932
933 DynInstPtr inst;
934 bool add_to_iq = false;
935 int dis_num_inst = 0;
936
937 // Loop through the instructions, putting them in the instruction
938 // queue.
939 for ( ; dis_num_inst < insts_to_add &&
574 }
575
576 // Add finished instruction to queue to commit.
577 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
578 (*iewQueue)[wbCycle].size++;
579}
580
581template <class Impl>

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938
939 DynInstPtr inst;
940 bool add_to_iq = false;
941 int dis_num_inst = 0;
942
943 // Loop through the instructions, putting them in the instruction
944 // queue.
945 for ( ; dis_num_inst < insts_to_add &&
940 dis_num_inst < issueReadWidth;
946 dis_num_inst < dispatchWidth;
941 ++dis_num_inst)
942 {
943 inst = insts_to_dispatch.front();
944
945 if (dispatchStatus[tid] == Unblocking) {
946 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
947 "buffer\n", tid);
948 }

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1184 inst->setExecuted();
1185
1186 // Not sure if I should set this here or just let commit try to
1187 // commit any squashed instructions. I like the latter a bit more.
1188 inst->setCanCommit();
1189
1190 ++iewExecSquashedInsts;
1191
947 ++dis_num_inst)
948 {
949 inst = insts_to_dispatch.front();
950
951 if (dispatchStatus[tid] == Unblocking) {
952 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
953 "buffer\n", tid);
954 }

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1190 inst->setExecuted();
1191
1192 // Not sure if I should set this here or just let commit try to
1193 // commit any squashed instructions. I like the latter a bit more.
1194 inst->setCanCommit();
1195
1196 ++iewExecSquashedInsts;
1197
1198 decrWb(inst->seqNum);
1192 continue;
1193 }
1194
1195 Fault fault = NoFault;
1196
1197 // Execute instruction.
1198 // Note that if the instruction faults, it will be handled
1199 // at the commit stage.

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1346 }
1347
1348 if (dependents) {
1349 producerInst[tid]++;
1350 consumerInst[tid]+= dependents;
1351 }
1352 writebackCount[tid]++;
1353 }
1199 continue;
1200 }
1201
1202 Fault fault = NoFault;
1203
1204 // Execute instruction.
1205 // Note that if the instruction faults, it will be handled
1206 // at the commit stage.

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1353 }
1354
1355 if (dependents) {
1356 producerInst[tid]++;
1357 consumerInst[tid]+= dependents;
1358 }
1359 writebackCount[tid]++;
1360 }
1361
1362 decrWb(inst->seqNum);
1354 }
1355}
1356
1357template<class Impl>
1358void
1359DefaultIEW<Impl>::tick()
1360{
1361 wbNumInst = 0;

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1364}
1365
1366template<class Impl>
1367void
1368DefaultIEW<Impl>::tick()
1369{
1370 wbNumInst = 0;

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