iew_impl.hh (2674:6d4afef73a20) iew_impl.hh (2698:d5f35d41e017)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 DPRINTF(IEW, "Setting scoreboard pointer.\n");
370 scoreboard = sb_ptr;
371}
372
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 356 unchanged lines hidden (view full) ---

365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 DPRINTF(IEW, "Setting scoreboard pointer.\n");
370 scoreboard = sb_ptr;
371}
372
373#if 0
374template<class Impl>
375void
376DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
377{
378 ldstQueue.setPageTable(pt_ptr);
379}
380#endif
381
382template <class Impl>
383void
384DefaultIEW<Impl>::switchOut()
385{
386 // IEW is ready to switch out at any time.
387 cpu->signalSwitched();
388}
389

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1177
1178 list<unsigned>::iterator threads = (*activeThreads).begin();
1179
1180 while (threads != (*activeThreads).end()) {
1181 unsigned tid = *threads++;
1182 fetchRedirect[tid] = false;
1183 }
1184
373template <class Impl>
374void
375DefaultIEW<Impl>::switchOut()
376{
377 // IEW is ready to switch out at any time.
378 cpu->signalSwitched();
379}
380

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1168
1169 list<unsigned>::iterator threads = (*activeThreads).begin();
1170
1171 while (threads != (*activeThreads).end()) {
1172 unsigned tid = *threads++;
1173 fetchRedirect[tid] = false;
1174 }
1175
1185#if 0
1186 printAvailableInsts();
1187#endif
1176 // Uncomment this if you want to see all available instructions.
1177// printAvailableInsts();
1188
1189 // Execute/writeback any instructions that are available.
1190 int insts_to_execute = fromIssue->size;
1191 int inst_num = 0;
1192 for (; inst_num < insts_to_execute;
1193 ++inst_num) {
1194
1195 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");

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1344 // mark scoreboard that this instruction is finally complete.
1345 // Either have IEW have direct access to scoreboard, or have this
1346 // as part of backwards communication.
1347 for (int inst_num = 0; inst_num < issueWidth &&
1348 toCommit->insts[inst_num]; inst_num++) {
1349 DynInstPtr inst = toCommit->insts[inst_num];
1350 int tid = inst->threadNumber;
1351
1178
1179 // Execute/writeback any instructions that are available.
1180 int insts_to_execute = fromIssue->size;
1181 int inst_num = 0;
1182 for (; inst_num < insts_to_execute;
1183 ++inst_num) {
1184
1185 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");

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1334 // mark scoreboard that this instruction is finally complete.
1335 // Either have IEW have direct access to scoreboard, or have this
1336 // as part of backwards communication.
1337 for (int inst_num = 0; inst_num < issueWidth &&
1338 toCommit->insts[inst_num]; inst_num++) {
1339 DynInstPtr inst = toCommit->insts[inst_num];
1340 int tid = inst->threadNumber;
1341
1352 DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
1353 inst->readPC());
1342 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1343 inst->seqNum, inst->readPC());
1354
1355 iewInstsToCommit[tid]++;
1356
1357 // Some instructions will be sent to commit without having
1358 // executed because they need commit to handle them.
1359 // E.g. Uncached loads have not actually executed when they
1360 // are first sent to commit. Instead commit must tell the LSQ
1361 // when it's ready to execute the uncached load.

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1345 iewInstsToCommit[tid]++;
1346
1347 // Some instructions will be sent to commit without having
1348 // executed because they need commit to handle them.
1349 // E.g. Uncached loads have not actually executed when they
1350 // are first sent to commit. Instead commit must tell the LSQ
1351 // when it's ready to execute the uncached load.

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