iew_impl.hh (13652:45d94ac03a27) | iew_impl.hh (13831:4fba790d88be) |
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1/* 2 * Copyright (c) 2010-2013, 2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 448 unchanged lines hidden (view full) --- 457 issueToExecQueue.advance(); 458 } 459} 460 461template<class Impl> 462void 463DefaultIEW<Impl>::squash(ThreadID tid) 464{ | 1/* 2 * Copyright (c) 2010-2013, 2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 448 unchanged lines hidden (view full) --- 457 issueToExecQueue.advance(); 458 } 459} 460 461template<class Impl> 462void 463DefaultIEW<Impl>::squash(ThreadID tid) 464{ |
465 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); | 465 DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid); |
466 467 // Tell the IQ to start squashing. 468 instQueue.squash(tid); 469 470 // Tell the LDSTQ to start squashing. 471 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 472 updatedQueues = true; 473 474 // Clear the skid buffer in case it has any data in it. | 466 467 // Tell the IQ to start squashing. 468 instQueue.squash(tid); 469 470 // Tell the LDSTQ to start squashing. 471 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 472 updatedQueues = true; 473 474 // Clear the skid buffer in case it has any data in it. |
475 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 476 tid, fromCommit->commitInfo[tid].doneSeqNum); | 475 DPRINTF(IEW, 476 "Removing skidbuffer instructions until " 477 "[sn:%llu] [tid:%i]\n", 478 fromCommit->commitInfo[tid].doneSeqNum, tid); |
477 478 while (!skidBuffer[tid].empty()) { 479 if (skidBuffer[tid].front()->isLoad()) { 480 toRename->iewInfo[tid].dispatchedToLQ++; 481 } 482 if (skidBuffer[tid].front()->isStore() || 483 skidBuffer[tid].front()->isAtomic()) { 484 toRename->iewInfo[tid].dispatchedToSQ++; --- 6 unchanged lines hidden (view full) --- 491 492 emptyRenameInsts(tid); 493} 494 495template<class Impl> 496void 497DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 498{ | 479 480 while (!skidBuffer[tid].empty()) { 481 if (skidBuffer[tid].front()->isLoad()) { 482 toRename->iewInfo[tid].dispatchedToLQ++; 483 } 484 if (skidBuffer[tid].front()->isStore() || 485 skidBuffer[tid].front()->isAtomic()) { 486 toRename->iewInfo[tid].dispatchedToSQ++; --- 6 unchanged lines hidden (view full) --- 493 494 emptyRenameInsts(tid); 495} 496 497template<class Impl> 498void 499DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 500{ |
499 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 500 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); | 501 DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction," 502 " PC: %s " 503 "\n", tid, inst->seqNum, inst->pcState() ); |
501 502 if (!toCommit->squash[tid] || 503 inst->seqNum < toCommit->squashedSeqNum[tid]) { 504 toCommit->squash[tid] = true; 505 toCommit->squashedSeqNum[tid] = inst->seqNum; 506 toCommit->branchTaken[tid] = inst->pcState().branching(); 507 508 TheISA::PCState pc = inst->pcState(); --- 7 unchanged lines hidden (view full) --- 516 } 517 518} 519 520template<class Impl> 521void 522DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 523{ | 504 505 if (!toCommit->squash[tid] || 506 inst->seqNum < toCommit->squashedSeqNum[tid]) { 507 toCommit->squash[tid] = true; 508 toCommit->squashedSeqNum[tid] = inst->seqNum; 509 toCommit->branchTaken[tid] = inst->pcState().branching(); 510 511 TheISA::PCState pc = inst->pcState(); --- 7 unchanged lines hidden (view full) --- 519 } 520 521} 522 523template<class Impl> 524void 525DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 526{ |
524 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 525 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); | 527 DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger " 528 "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum); |
526 // Need to include inst->seqNum in the following comparison to cover the 527 // corner case when a branch misprediction and a memory violation for the 528 // same instruction (e.g. load PC) are detected in the same cycle. In this 529 // case the memory violator should take precedence over the branch 530 // misprediction because it requires the violator itself to be included in 531 // the squash. 532 if (!toCommit->squash[tid] || 533 inst->seqNum <= toCommit->squashedSeqNum[tid]) { --- 9 unchanged lines hidden (view full) --- 543 wroteToTimeBuffer = true; 544 } 545} 546 547template<class Impl> 548void 549DefaultIEW<Impl>::block(ThreadID tid) 550{ | 529 // Need to include inst->seqNum in the following comparison to cover the 530 // corner case when a branch misprediction and a memory violation for the 531 // same instruction (e.g. load PC) are detected in the same cycle. In this 532 // case the memory violator should take precedence over the branch 533 // misprediction because it requires the violator itself to be included in 534 // the squash. 535 if (!toCommit->squash[tid] || 536 inst->seqNum <= toCommit->squashedSeqNum[tid]) { --- 9 unchanged lines hidden (view full) --- 546 wroteToTimeBuffer = true; 547 } 548} 549 550template<class Impl> 551void 552DefaultIEW<Impl>::block(ThreadID tid) 553{ |
551 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); | 554 DPRINTF(IEW, "[tid:%i] Blocking.\n", tid); |
552 553 if (dispatchStatus[tid] != Blocked && 554 dispatchStatus[tid] != Unblocking) { 555 toRename->iewBlock[tid] = true; 556 wroteToTimeBuffer = true; 557 } 558 559 // Add the current inputs to the skid buffer so they can be 560 // reprocessed when this stage unblocks. 561 skidInsert(tid); 562 563 dispatchStatus[tid] = Blocked; 564} 565 566template<class Impl> 567void 568DefaultIEW<Impl>::unblock(ThreadID tid) 569{ | 555 556 if (dispatchStatus[tid] != Blocked && 557 dispatchStatus[tid] != Unblocking) { 558 toRename->iewBlock[tid] = true; 559 wroteToTimeBuffer = true; 560 } 561 562 // Add the current inputs to the skid buffer so they can be 563 // reprocessed when this stage unblocks. 564 skidInsert(tid); 565 566 dispatchStatus[tid] = Blocked; 567} 568 569template<class Impl> 570void 571DefaultIEW<Impl>::unblock(ThreadID tid) 572{ |
570 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " | 573 DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid " |
571 "buffer %u.\n",tid, tid); 572 573 // If the skid bufffer is empty, signal back to previous stages to unblock. 574 // Also switch status to running. 575 if (skidBuffer[tid].empty()) { 576 toRename->iewUnblock[tid] = true; 577 wroteToTimeBuffer = true; | 574 "buffer %u.\n",tid, tid); 575 576 // If the skid bufffer is empty, signal back to previous stages to unblock. 577 // Also switch status to running. 578 if (skidBuffer[tid].empty()) { 579 toRename->iewUnblock[tid] = true; 580 wroteToTimeBuffer = true; |
578 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); | 581 DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid); |
579 dispatchStatus[tid] = Running; 580 } 581} 582 583template<class Impl> 584void 585DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 586{ --- 77 unchanged lines hidden (view full) --- 664{ 665 DynInstPtr inst = NULL; 666 667 while (!insts[tid].empty()) { 668 inst = insts[tid].front(); 669 670 insts[tid].pop(); 671 | 582 dispatchStatus[tid] = Running; 583 } 584} 585 586template<class Impl> 587void 588DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 589{ --- 77 unchanged lines hidden (view full) --- 667{ 668 DynInstPtr inst = NULL; 669 670 while (!insts[tid].empty()) { 671 inst = insts[tid].front(); 672 673 insts[tid].pop(); 674 |
672 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " | 675 DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into " |
673 "dispatch skidBuffer %i\n",tid, inst->seqNum, 674 inst->pcState(),tid); 675 676 skidBuffer[tid].push(inst); 677 } 678 679 assert(skidBuffer[tid].size() <= skidBufferMax && 680 "Skidbuffer Exceeded Max Size"); --- 78 unchanged lines hidden (view full) --- 759 760template <class Impl> 761bool 762DefaultIEW<Impl>::checkStall(ThreadID tid) 763{ 764 bool ret_val(false); 765 766 if (fromCommit->commitInfo[tid].robSquashing) { | 676 "dispatch skidBuffer %i\n",tid, inst->seqNum, 677 inst->pcState(),tid); 678 679 skidBuffer[tid].push(inst); 680 } 681 682 assert(skidBuffer[tid].size() <= skidBufferMax && 683 "Skidbuffer Exceeded Max Size"); --- 78 unchanged lines hidden (view full) --- 762 763template <class Impl> 764bool 765DefaultIEW<Impl>::checkStall(ThreadID tid) 766{ 767 bool ret_val(false); 768 769 if (fromCommit->commitInfo[tid].robSquashing) { |
767 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); | 770 DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid); |
768 ret_val = true; 769 } else if (instQueue.isFull(tid)) { | 771 ret_val = true; 772 } else if (instQueue.isFull(tid)) { |
770 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); | 773 DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid); |
771 ret_val = true; 772 } 773 774 return ret_val; 775} 776 777template <class Impl> 778void --- 16 unchanged lines hidden (view full) --- 795 } 796 797 dispatchStatus[tid] = Squashing; 798 fetchRedirect[tid] = false; 799 return; 800 } 801 802 if (fromCommit->commitInfo[tid].robSquashing) { | 774 ret_val = true; 775 } 776 777 return ret_val; 778} 779 780template <class Impl> 781void --- 16 unchanged lines hidden (view full) --- 798 } 799 800 dispatchStatus[tid] = Squashing; 801 fetchRedirect[tid] = false; 802 return; 803 } 804 805 if (fromCommit->commitInfo[tid].robSquashing) { |
803 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); | 806 DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid); |
804 805 dispatchStatus[tid] = Squashing; 806 emptyRenameInsts(tid); 807 wroteToTimeBuffer = true; 808 } 809 810 if (checkStall(tid)) { 811 block(tid); 812 dispatchStatus[tid] = Blocked; 813 return; 814 } 815 816 if (dispatchStatus[tid] == Blocked) { 817 // Status from previous cycle was blocked, but there are no more stall 818 // conditions. Switch over to unblocking. | 807 808 dispatchStatus[tid] = Squashing; 809 emptyRenameInsts(tid); 810 wroteToTimeBuffer = true; 811 } 812 813 if (checkStall(tid)) { 814 block(tid); 815 dispatchStatus[tid] = Blocked; 816 return; 817 } 818 819 if (dispatchStatus[tid] == Blocked) { 820 // Status from previous cycle was blocked, but there are no more stall 821 // conditions. Switch over to unblocking. |
819 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", | 822 DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n", |
820 tid); 821 822 dispatchStatus[tid] = Unblocking; 823 824 unblock(tid); 825 826 return; 827 } 828 829 if (dispatchStatus[tid] == Squashing) { 830 // Switch status to running if rename isn't being told to block or 831 // squash this cycle. | 823 tid); 824 825 dispatchStatus[tid] = Unblocking; 826 827 unblock(tid); 828 829 return; 830 } 831 832 if (dispatchStatus[tid] == Squashing) { 833 // Switch status to running if rename isn't being told to block or 834 // squash this cycle. |
832 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", | 835 DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n", |
833 tid); 834 835 dispatchStatus[tid] = Running; 836 837 return; 838 } 839} 840 --- 10 unchanged lines hidden (view full) --- 851 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 852 } 853} 854 855template <class Impl> 856void 857DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 858{ | 836 tid); 837 838 dispatchStatus[tid] = Running; 839 840 return; 841 } 842} 843 --- 10 unchanged lines hidden (view full) --- 854 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 855 } 856} 857 858template <class Impl> 859void 860DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 861{ |
859 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); | 862 DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid); |
860 861 while (!insts[tid].empty()) { 862 863 if (insts[tid].front()->isLoad()) { 864 toRename->iewInfo[tid].dispatchedToLQ++; 865 } 866 if (insts[tid].front()->isStore() || 867 insts[tid].front()->isAtomic()) { --- 105 unchanged lines hidden (view full) --- 973 // queue. 974 for ( ; dis_num_inst < insts_to_add && 975 dis_num_inst < dispatchWidth; 976 ++dis_num_inst) 977 { 978 inst = insts_to_dispatch.front(); 979 980 if (dispatchStatus[tid] == Unblocking) { | 863 864 while (!insts[tid].empty()) { 865 866 if (insts[tid].front()->isLoad()) { 867 toRename->iewInfo[tid].dispatchedToLQ++; 868 } 869 if (insts[tid].front()->isStore() || 870 insts[tid].front()->isAtomic()) { --- 105 unchanged lines hidden (view full) --- 976 // queue. 977 for ( ; dis_num_inst < insts_to_add && 978 dis_num_inst < dispatchWidth; 979 ++dis_num_inst) 980 { 981 inst = insts_to_dispatch.front(); 982 983 if (dispatchStatus[tid] == Unblocking) { |
981 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " | 984 DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid " |
982 "buffer\n", tid); 983 } 984 985 // Make sure there's a valid instruction there. 986 assert(inst); 987 | 985 "buffer\n", tid); 986 } 987 988 // Make sure there's a valid instruction there. 989 assert(inst); 990 |
988 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " | 991 DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to " |
989 "IQ.\n", 990 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 991 992 // Be sure to mark these instructions as ready so that the 993 // commit stage can go ahead and execute them, and mark 994 // them as issued so the IQ doesn't reprocess them. 995 996 // Check for squashed instructions. 997 if (inst->isSquashed()) { | 992 "IQ.\n", 993 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 994 995 // Be sure to mark these instructions as ready so that the 996 // commit stage can go ahead and execute them, and mark 997 // them as issued so the IQ doesn't reprocess them. 998 999 // Check for squashed instructions. 1000 if (inst->isSquashed()) { |
998 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " | 1001 DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, " |
999 "not adding to IQ.\n", tid); 1000 1001 ++iewDispSquashedInsts; 1002 1003 insts_to_dispatch.pop(); 1004 1005 //Tell Rename That An Instruction has been processed 1006 if (inst->isLoad()) { --- 5 unchanged lines hidden (view full) --- 1012 1013 toRename->iewInfo[tid].dispatched++; 1014 1015 continue; 1016 } 1017 1018 // Check for full conditions. 1019 if (instQueue.isFull(tid)) { | 1002 "not adding to IQ.\n", tid); 1003 1004 ++iewDispSquashedInsts; 1005 1006 insts_to_dispatch.pop(); 1007 1008 //Tell Rename That An Instruction has been processed 1009 if (inst->isLoad()) { --- 5 unchanged lines hidden (view full) --- 1015 1016 toRename->iewInfo[tid].dispatched++; 1017 1018 continue; 1019 } 1020 1021 // Check for full conditions. 1022 if (instQueue.isFull(tid)) { |
1020 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); | 1023 DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid); |
1021 1022 // Call function to start blocking. 1023 block(tid); 1024 1025 // Set unblock to false. Special case where we are using 1026 // skidbuffer (unblocking) instructions but then we still 1027 // get full in the IQ. 1028 toRename->iewUnblock[tid] = false; 1029 1030 ++iewIQFullEvents; 1031 break; 1032 } 1033 1034 // Check LSQ if inst is LD/ST 1035 if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 1036 (inst->isLoad() && ldstQueue.lqFull(tid)) || 1037 (inst->isStore() && ldstQueue.sqFull(tid))) { | 1024 1025 // Call function to start blocking. 1026 block(tid); 1027 1028 // Set unblock to false. Special case where we are using 1029 // skidbuffer (unblocking) instructions but then we still 1030 // get full in the IQ. 1031 toRename->iewUnblock[tid] = false; 1032 1033 ++iewIQFullEvents; 1034 break; 1035 } 1036 1037 // Check LSQ if inst is LD/ST 1038 if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 1039 (inst->isLoad() && ldstQueue.lqFull(tid)) || 1040 (inst->isStore() && ldstQueue.sqFull(tid))) { |
1038 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, | 1041 DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid, |
1039 inst->isLoad() ? "LQ" : "SQ"); 1040 1041 // Call function to start blocking. 1042 block(tid); 1043 1044 // Set unblock to false. Special case where we are using 1045 // skidbuffer (unblocking) instructions but then we still 1046 // get full in the IQ. 1047 toRename->iewUnblock[tid] = false; 1048 1049 ++iewLSQFullEvents; 1050 break; 1051 } 1052 1053 // Otherwise issue the instruction just fine. 1054 if (inst->isAtomic()) { | 1042 inst->isLoad() ? "LQ" : "SQ"); 1043 1044 // Call function to start blocking. 1045 block(tid); 1046 1047 // Set unblock to false. Special case where we are using 1048 // skidbuffer (unblocking) instructions but then we still 1049 // get full in the IQ. 1050 toRename->iewUnblock[tid] = false; 1051 1052 ++iewLSQFullEvents; 1053 break; 1054 } 1055 1056 // Otherwise issue the instruction just fine. 1057 if (inst->isAtomic()) { |
1055 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " | 1058 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " |
1056 "encountered, adding to LSQ.\n", tid); 1057 1058 ldstQueue.insertStore(inst); 1059 1060 ++iewDispStoreInsts; 1061 1062 // AMOs need to be set as "canCommit()" 1063 // so that commit can process them when they reach the 1064 // head of commit. 1065 inst->setCanCommit(); 1066 instQueue.insertNonSpec(inst); 1067 add_to_iq = false; 1068 1069 ++iewDispNonSpecInsts; 1070 1071 toRename->iewInfo[tid].dispatchedToSQ++; 1072 } else if (inst->isLoad()) { | 1059 "encountered, adding to LSQ.\n", tid); 1060 1061 ldstQueue.insertStore(inst); 1062 1063 ++iewDispStoreInsts; 1064 1065 // AMOs need to be set as "canCommit()" 1066 // so that commit can process them when they reach the 1067 // head of commit. 1068 inst->setCanCommit(); 1069 instQueue.insertNonSpec(inst); 1070 add_to_iq = false; 1071 1072 ++iewDispNonSpecInsts; 1073 1074 toRename->iewInfo[tid].dispatchedToSQ++; 1075 } else if (inst->isLoad()) { |
1073 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " | 1076 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " |
1074 "encountered, adding to LSQ.\n", tid); 1075 1076 // Reserve a spot in the load store queue for this 1077 // memory access. 1078 ldstQueue.insertLoad(inst); 1079 1080 ++iewDispLoadInsts; 1081 1082 add_to_iq = true; 1083 1084 toRename->iewInfo[tid].dispatchedToLQ++; 1085 } else if (inst->isStore()) { | 1077 "encountered, adding to LSQ.\n", tid); 1078 1079 // Reserve a spot in the load store queue for this 1080 // memory access. 1081 ldstQueue.insertLoad(inst); 1082 1083 ++iewDispLoadInsts; 1084 1085 add_to_iq = true; 1086 1087 toRename->iewInfo[tid].dispatchedToLQ++; 1088 } else if (inst->isStore()) { |
1086 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " | 1089 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " |
1087 "encountered, adding to LSQ.\n", tid); 1088 1089 ldstQueue.insertStore(inst); 1090 1091 ++iewDispStoreInsts; 1092 1093 if (inst->isStoreConditional()) { 1094 // Store conditionals need to be set as "canCommit()" --- 11 unchanged lines hidden (view full) --- 1106 1107 toRename->iewInfo[tid].dispatchedToSQ++; 1108 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1109 // Same as non-speculative stores. 1110 inst->setCanCommit(); 1111 instQueue.insertBarrier(inst); 1112 add_to_iq = false; 1113 } else if (inst->isNop()) { | 1090 "encountered, adding to LSQ.\n", tid); 1091 1092 ldstQueue.insertStore(inst); 1093 1094 ++iewDispStoreInsts; 1095 1096 if (inst->isStoreConditional()) { 1097 // Store conditionals need to be set as "canCommit()" --- 11 unchanged lines hidden (view full) --- 1109 1110 toRename->iewInfo[tid].dispatchedToSQ++; 1111 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1112 // Same as non-speculative stores. 1113 inst->setCanCommit(); 1114 instQueue.insertBarrier(inst); 1115 add_to_iq = false; 1116 } else if (inst->isNop()) { |
1114 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " | 1117 DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, " |
1115 "skipping.\n", tid); 1116 1117 inst->setIssued(); 1118 inst->setExecuted(); 1119 inst->setCanCommit(); 1120 1121 instQueue.recordProducer(inst); 1122 1123 iewExecutedNop[tid]++; 1124 1125 add_to_iq = false; 1126 } else { 1127 assert(!inst->isExecuted()); 1128 add_to_iq = true; 1129 } 1130 1131 if (add_to_iq && inst->isNonSpeculative()) { | 1118 "skipping.\n", tid); 1119 1120 inst->setIssued(); 1121 inst->setExecuted(); 1122 inst->setCanCommit(); 1123 1124 instQueue.recordProducer(inst); 1125 1126 iewExecutedNop[tid]++; 1127 1128 add_to_iq = false; 1129 } else { 1130 assert(!inst->isExecuted()); 1131 add_to_iq = true; 1132 } 1133 1134 if (add_to_iq && inst->isNonSpeculative()) { |
1132 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " | 1135 DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction " |
1133 "encountered, skipping.\n", tid); 1134 1135 // Same as non-speculative stores. 1136 inst->setCanCommit(); 1137 1138 // Specifically insert it as nonspeculative. 1139 instQueue.insertNonSpec(inst); 1140 --- 16 unchanged lines hidden (view full) --- 1157 1158#if TRACING_ON 1159 inst->dispatchTick = curTick() - inst->fetchTick; 1160#endif 1161 ppDispatch->notify(inst); 1162 } 1163 1164 if (!insts_to_dispatch.empty()) { | 1136 "encountered, skipping.\n", tid); 1137 1138 // Same as non-speculative stores. 1139 inst->setCanCommit(); 1140 1141 // Specifically insert it as nonspeculative. 1142 instQueue.insertNonSpec(inst); 1143 --- 16 unchanged lines hidden (view full) --- 1160 1161#if TRACING_ON 1162 inst->dispatchTick = curTick() - inst->fetchTick; 1163#endif 1164 ppDispatch->notify(inst); 1165 } 1166 1167 if (!insts_to_dispatch.empty()) { |
1165 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); | 1168 DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid); |
1166 block(tid); 1167 toRename->iewUnblock[tid] = false; 1168 } 1169 1170 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1171 dispatchStatus[tid] = Running; 1172 1173 updatedQueues = true; --- 49 unchanged lines hidden (view full) --- 1223 int inst_num = 0; 1224 for (; inst_num < insts_to_execute; 1225 ++inst_num) { 1226 1227 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1228 1229 DynInstPtr inst = instQueue.getInstToExecute(); 1230 | 1169 block(tid); 1170 toRename->iewUnblock[tid] = false; 1171 } 1172 1173 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1174 dispatchStatus[tid] = Running; 1175 1176 updatedQueues = true; --- 49 unchanged lines hidden (view full) --- 1226 int inst_num = 0; 1227 for (; inst_num < insts_to_execute; 1228 ++inst_num) { 1229 1230 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1231 1232 DynInstPtr inst = instQueue.getInstToExecute(); 1233 |
1231 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", | 1234 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n", |
1232 inst->pcState(), inst->threadNumber,inst->seqNum); 1233 1234 // Notify potential listeners that this instruction has started 1235 // executing 1236 ppExecute->notify(inst); 1237 1238 // Check if the instruction is squashed; if so then skip it 1239 if (inst->isSquashed()) { 1240 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" | 1235 inst->pcState(), inst->threadNumber,inst->seqNum); 1236 1237 // Notify potential listeners that this instruction has started 1238 // executing 1239 ppExecute->notify(inst); 1240 1241 // Check if the instruction is squashed; if so then skip it 1242 if (inst->isSquashed()) { 1243 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" |
1241 " [sn:%i]\n", inst->pcState(), inst->threadNumber, | 1244 " [sn:%llu]\n", inst->pcState(), inst->threadNumber, |
1242 inst->seqNum); 1243 1244 // Consider this instruction executed so that commit can go 1245 // ahead and retire the instruction. 1246 inst->setExecuted(); 1247 1248 // Not sure if I should set this here or just let commit try to 1249 // commit any squashed instructions. I like the latter a bit more. --- 111 unchanged lines hidden (view full) --- 1361 1362 // Prevent testing for misprediction on load instructions, 1363 // that have not been executed. 1364 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1365 1366 if (inst->mispredicted() && !loadNotExecuted) { 1367 fetchRedirect[tid] = true; 1368 | 1245 inst->seqNum); 1246 1247 // Consider this instruction executed so that commit can go 1248 // ahead and retire the instruction. 1249 inst->setExecuted(); 1250 1251 // Not sure if I should set this here or just let commit try to 1252 // commit any squashed instructions. I like the latter a bit more. --- 111 unchanged lines hidden (view full) --- 1364 1365 // Prevent testing for misprediction on load instructions, 1366 // that have not been executed. 1367 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1368 1369 if (inst->mispredicted() && !loadNotExecuted) { 1370 fetchRedirect[tid] = true; 1371 |
1369 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1370 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1371 inst->readPredTarg()); 1372 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1373 inst->pcState()); | 1372 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1373 "Branch mispredict detected.\n", 1374 tid,inst->seqNum); 1375 DPRINTF(IEW, "[tid:%i] [sn:%llu] " 1376 "Predicted target was PC: %s\n", 1377 tid,inst->seqNum,inst->readPredTarg()); 1378 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1379 "Redirecting fetch to PC: %s\n", 1380 tid,inst->seqNum,inst->pcState()); |
1374 // If incorrect, then signal the ROB that it must be squashed. 1375 squashDueToBranch(inst, tid); 1376 1377 ppMispredict->notify(inst); 1378 1379 if (inst->readPredTaken()) { 1380 predictedTakenIncorrect++; 1381 } else { --- 277 unchanged lines hidden (view full) --- 1659 1660 if (!fetchRedirect[tid] || 1661 !toCommit->squash[tid] || 1662 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1663 1664 if (inst->mispredicted()) { 1665 fetchRedirect[tid] = true; 1666 | 1381 // If incorrect, then signal the ROB that it must be squashed. 1382 squashDueToBranch(inst, tid); 1383 1384 ppMispredict->notify(inst); 1385 1386 if (inst->readPredTaken()) { 1387 predictedTakenIncorrect++; 1388 } else { --- 277 unchanged lines hidden (view full) --- 1666 1667 if (!fetchRedirect[tid] || 1668 !toCommit->squash[tid] || 1669 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1670 1671 if (inst->mispredicted()) { 1672 fetchRedirect[tid] = true; 1673 |
1667 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1668 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", | 1674 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1675 "Branch mispredict detected.\n", 1676 tid,inst->seqNum); 1677 DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target " 1678 "was PC:%#x, NPC:%#x\n", 1679 tid,inst->seqNum, |
1669 inst->predInstAddr(), inst->predNextInstAddr()); | 1680 inst->predInstAddr(), inst->predNextInstAddr()); |
1670 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1671 " NPC: %#x.\n", inst->nextInstAddr(), | 1681 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1682 "Redirecting fetch to PC: %#x, " 1683 "NPC: %#x.\n", 1684 tid,inst->seqNum, 1685 inst->nextInstAddr(), |
1672 inst->nextInstAddr()); 1673 // If incorrect, then signal the ROB that it must be squashed. 1674 squashDueToBranch(inst, tid); 1675 1676 if (inst->readPredTaken()) { 1677 predictedTakenIncorrect++; 1678 } else { 1679 predictedNotTakenIncorrect++; 1680 } 1681 } 1682 } 1683} 1684 1685#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ | 1686 inst->nextInstAddr()); 1687 // If incorrect, then signal the ROB that it must be squashed. 1688 squashDueToBranch(inst, tid); 1689 1690 if (inst->readPredTaken()) { 1691 predictedTakenIncorrect++; 1692 } else { 1693 predictedNotTakenIncorrect++; 1694 } 1695 } 1696 } 1697} 1698 1699#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ |