iew_impl.hh (13641:648f3106ebdf) iew_impl.hh (13652:45d94ac03a27)
1/*
2 * Copyright (c) 2010-2013, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 465 unchanged lines hidden (view full) ---

474 // Clear the skid buffer in case it has any data in it.
475 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
476 tid, fromCommit->commitInfo[tid].doneSeqNum);
477
478 while (!skidBuffer[tid].empty()) {
479 if (skidBuffer[tid].front()->isLoad()) {
480 toRename->iewInfo[tid].dispatchedToLQ++;
481 }
1/*
2 * Copyright (c) 2010-2013, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 465 unchanged lines hidden (view full) ---

474 // Clear the skid buffer in case it has any data in it.
475 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
476 tid, fromCommit->commitInfo[tid].doneSeqNum);
477
478 while (!skidBuffer[tid].empty()) {
479 if (skidBuffer[tid].front()->isLoad()) {
480 toRename->iewInfo[tid].dispatchedToLQ++;
481 }
482 if (skidBuffer[tid].front()->isStore()) {
482 if (skidBuffer[tid].front()->isStore() ||
483 skidBuffer[tid].front()->isAtomic()) {
483 toRename->iewInfo[tid].dispatchedToSQ++;
484 }
485
486 toRename->iewInfo[tid].dispatched++;
487
488 skidBuffer[tid].pop();
489 }
490

--- 366 unchanged lines hidden (view full) ---

857{
858 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
859
860 while (!insts[tid].empty()) {
861
862 if (insts[tid].front()->isLoad()) {
863 toRename->iewInfo[tid].dispatchedToLQ++;
864 }
484 toRename->iewInfo[tid].dispatchedToSQ++;
485 }
486
487 toRename->iewInfo[tid].dispatched++;
488
489 skidBuffer[tid].pop();
490 }
491

--- 366 unchanged lines hidden (view full) ---

858{
859 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
860
861 while (!insts[tid].empty()) {
862
863 if (insts[tid].front()->isLoad()) {
864 toRename->iewInfo[tid].dispatchedToLQ++;
865 }
865 if (insts[tid].front()->isStore()) {
866 if (insts[tid].front()->isStore() ||
867 insts[tid].front()->isAtomic()) {
866 toRename->iewInfo[tid].dispatchedToSQ++;
867 }
868
869 toRename->iewInfo[tid].dispatched++;
870
871 insts[tid].pop();
872 }
873}

--- 125 unchanged lines hidden (view full) ---

999 ++iewDispSquashedInsts;
1000
1001 insts_to_dispatch.pop();
1002
1003 //Tell Rename That An Instruction has been processed
1004 if (inst->isLoad()) {
1005 toRename->iewInfo[tid].dispatchedToLQ++;
1006 }
868 toRename->iewInfo[tid].dispatchedToSQ++;
869 }
870
871 toRename->iewInfo[tid].dispatched++;
872
873 insts[tid].pop();
874 }
875}

--- 125 unchanged lines hidden (view full) ---

1001 ++iewDispSquashedInsts;
1002
1003 insts_to_dispatch.pop();
1004
1005 //Tell Rename That An Instruction has been processed
1006 if (inst->isLoad()) {
1007 toRename->iewInfo[tid].dispatchedToLQ++;
1008 }
1007 if (inst->isStore()) {
1009 if (inst->isStore() || inst->isAtomic()) {
1008 toRename->iewInfo[tid].dispatchedToSQ++;
1009 }
1010
1011 toRename->iewInfo[tid].dispatched++;
1012
1013 continue;
1014 }
1015

--- 9 unchanged lines hidden (view full) ---

1025 // get full in the IQ.
1026 toRename->iewUnblock[tid] = false;
1027
1028 ++iewIQFullEvents;
1029 break;
1030 }
1031
1032 // Check LSQ if inst is LD/ST
1010 toRename->iewInfo[tid].dispatchedToSQ++;
1011 }
1012
1013 toRename->iewInfo[tid].dispatched++;
1014
1015 continue;
1016 }
1017

--- 9 unchanged lines hidden (view full) ---

1027 // get full in the IQ.
1028 toRename->iewUnblock[tid] = false;
1029
1030 ++iewIQFullEvents;
1031 break;
1032 }
1033
1034 // Check LSQ if inst is LD/ST
1033 if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
1035 if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
1036 (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1034 (inst->isStore() && ldstQueue.sqFull(tid))) {
1035 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1036 inst->isLoad() ? "LQ" : "SQ");
1037
1038 // Call function to start blocking.
1039 block(tid);
1040
1041 // Set unblock to false. Special case where we are using
1042 // skidbuffer (unblocking) instructions but then we still
1043 // get full in the IQ.
1044 toRename->iewUnblock[tid] = false;
1045
1046 ++iewLSQFullEvents;
1047 break;
1048 }
1049
1050 // Otherwise issue the instruction just fine.
1037 (inst->isStore() && ldstQueue.sqFull(tid))) {
1038 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1039 inst->isLoad() ? "LQ" : "SQ");
1040
1041 // Call function to start blocking.
1042 block(tid);
1043
1044 // Set unblock to false. Special case where we are using
1045 // skidbuffer (unblocking) instructions but then we still
1046 // get full in the IQ.
1047 toRename->iewUnblock[tid] = false;
1048
1049 ++iewLSQFullEvents;
1050 break;
1051 }
1052
1053 // Otherwise issue the instruction just fine.
1051 if (inst->isLoad()) {
1054 if (inst->isAtomic()) {
1052 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1053 "encountered, adding to LSQ.\n", tid);
1054
1055 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1056 "encountered, adding to LSQ.\n", tid);
1057
1058 ldstQueue.insertStore(inst);
1059
1060 ++iewDispStoreInsts;
1061
1062 // AMOs need to be set as "canCommit()"
1063 // so that commit can process them when they reach the
1064 // head of commit.
1065 inst->setCanCommit();
1066 instQueue.insertNonSpec(inst);
1067 add_to_iq = false;
1068
1069 ++iewDispNonSpecInsts;
1070
1071 toRename->iewInfo[tid].dispatchedToSQ++;
1072 } else if (inst->isLoad()) {
1073 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1074 "encountered, adding to LSQ.\n", tid);
1075
1055 // Reserve a spot in the load store queue for this
1056 // memory access.
1057 ldstQueue.insertLoad(inst);
1058
1059 ++iewDispLoadInsts;
1060
1061 add_to_iq = true;
1062

--- 175 unchanged lines hidden (view full) ---

1238 // Execute instruction.
1239 // Note that if the instruction faults, it will be handled
1240 // at the commit stage.
1241 if (inst->isMemRef()) {
1242 DPRINTF(IEW, "Execute: Calculating address for memory "
1243 "reference.\n");
1244
1245 // Tell the LDSTQ to execute this instruction (if it is a load).
1076 // Reserve a spot in the load store queue for this
1077 // memory access.
1078 ldstQueue.insertLoad(inst);
1079
1080 ++iewDispLoadInsts;
1081
1082 add_to_iq = true;
1083

--- 175 unchanged lines hidden (view full) ---

1259 // Execute instruction.
1260 // Note that if the instruction faults, it will be handled
1261 // at the commit stage.
1262 if (inst->isMemRef()) {
1263 DPRINTF(IEW, "Execute: Calculating address for memory "
1264 "reference.\n");
1265
1266 // Tell the LDSTQ to execute this instruction (if it is a load).
1246 if (inst->isLoad()) {
1267 if (inst->isAtomic()) {
1268 // AMOs are treated like store requests
1269 fault = ldstQueue.executeStore(inst);
1270
1271 if (inst->isTranslationDelayed() &&
1272 fault == NoFault) {
1273 // A hw page table walk is currently going on; the
1274 // instruction must be deferred.
1275 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1276 "store.\n");
1277 instQueue.deferMemInst(inst);
1278 continue;
1279 }
1280 } else if (inst->isLoad()) {
1247 // Loads will mark themselves as executed, and their writeback
1248 // event adds the instruction to the queue to commit
1249 fault = ldstQueue.executeLoad(inst);
1250
1251 if (inst->isTranslationDelayed() &&
1252 fault == NoFault) {
1253 // A hw page table walk is currently going on; the
1254 // instruction must be deferred.

--- 397 unchanged lines hidden --- 		1281 // Loads will mark themselves as executed, and their writeback
1282 // event adds the instruction to the queue to commit
1283 fault = ldstQueue.executeLoad(inst);
1284
1285 if (inst->isTranslationDelayed() &&
1286 fault == NoFault) {
1287 // A hw page table walk is currently going on; the
1288 // instruction must be deferred.

--- 397 unchanged lines hidden ---