iew_impl.hh (12537:aeff8f3d80c9) iew_impl.hh (13429:a1e199fd8122)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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473 skidBuffer[tid].pop();
474 }
475
476 emptyRenameInsts(tid);
477}
478
479template<class Impl>
480void
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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473 skidBuffer[tid].pop();
474 }
475
476 emptyRenameInsts(tid);
477}
478
479template<class Impl>
480void
481DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
481DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
482{
483 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
484 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
485
486 if (!toCommit->squash[tid] ||
487 inst->seqNum < toCommit->squashedSeqNum[tid]) {
488 toCommit->squash[tid] = true;
489 toCommit->squashedSeqNum[tid] = inst->seqNum;

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498
499 wroteToTimeBuffer = true;
500 }
501
502}
503
504template<class Impl>
505void
482{
483 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
484 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
485
486 if (!toCommit->squash[tid] ||
487 inst->seqNum < toCommit->squashedSeqNum[tid]) {
488 toCommit->squash[tid] = true;
489 toCommit->squashedSeqNum[tid] = inst->seqNum;

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498
499 wroteToTimeBuffer = true;
500 }
501
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
506DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
507{
508 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
509 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
510 // Need to include inst->seqNum in the following comparison to cover the
511 // corner case when a branch misprediction and a memory violation for the
512 // same instruction (e.g. load PC) are detected in the same cycle. In this
513 // case the memory violator should take precedence over the branch
514 // misprediction because it requires the violator itself to be included in

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561 wroteToTimeBuffer = true;
562 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
563 dispatchStatus[tid] = Running;
564 }
565}
566
567template<class Impl>
568void
507{
508 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
509 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
510 // Need to include inst->seqNum in the following comparison to cover the
511 // corner case when a branch misprediction and a memory violation for the
512 // same instruction (e.g. load PC) are detected in the same cycle. In this
513 // case the memory violator should take precedence over the branch
514 // misprediction because it requires the violator itself to be included in

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561 wroteToTimeBuffer = true;
562 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
563 dispatchStatus[tid] = Running;
564 }
565}
566
567template<class Impl>
568void
569DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
569DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
570{
571 instQueue.wakeDependents(inst);
572}
573
574template<class Impl>
575void
570{
571 instQueue.wakeDependents(inst);
572}
573
574template<class Impl>
575void
576DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
576DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
577{
578 instQueue.rescheduleMemInst(inst);
579}
580
581template<class Impl>
582void
577{
578 instQueue.rescheduleMemInst(inst);
579}
580
581template<class Impl>
582void
583DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
583DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
584{
585 instQueue.replayMemInst(inst);
586}
587
588template<class Impl>
589void
584{
585 instQueue.replayMemInst(inst);
586}
587
588template<class Impl>
589void
590DefaultIEW::blockMemInst(DynInstPtr& inst)
590DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
591{
592 instQueue.blockMemInst(inst);
593}
594
595template<class Impl>
596void
597DefaultIEW<Impl>::cacheUnblocked()
598{
599 instQueue.cacheUnblocked();
600}
601
602template<class Impl>
603void
591{
592 instQueue.blockMemInst(inst);
593}
594
595template<class Impl>
596void
597DefaultIEW<Impl>::cacheUnblocked()
598{
599 instQueue.cacheUnblocked();
600}
601
602template<class Impl>
603void
604DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
605{
606 // This function should not be called after writebackInsts in a
607 // single cycle. That will cause problems with an instruction
608 // being added to the queue to commit without being processed by
609 // writebackInsts prior to being sent to commit.
610
611 // First check the time slot that this instruction will write
612 // to. If there are free write ports at the time, then go ahead

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1573 if (wroteToTimeBuffer) {
1574 DPRINTF(Activity, "Activity this cycle.\n");
1575 cpu->activityThisCycle();
1576 }
1577}
1578
1579template <class Impl>
1580void
605{
606 // This function should not be called after writebackInsts in a
607 // single cycle. That will cause problems with an instruction
608 // being added to the queue to commit without being processed by
609 // writebackInsts prior to being sent to commit.
610
611 // First check the time slot that this instruction will write
612 // to. If there are free write ports at the time, then go ahead

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1573 if (wroteToTimeBuffer) {
1574 DPRINTF(Activity, "Activity this cycle.\n");
1575 cpu->activityThisCycle();
1576 }
1577}
1578
1579template <class Impl>
1580void
1581DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1581DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1582{
1583 ThreadID tid = inst->threadNumber;
1584
1585 iewExecutedInsts++;
1586
1587#if TRACING_ON
1588 if (DTRACE(O3PipeView)) {
1589 inst->completeTick = curTick() - inst->fetchTick;

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1605 if (inst->isLoad()) {
1606 iewExecLoadInsts[tid]++;
1607 }
1608 }
1609}
1610
1611template <class Impl>
1612void
1582{
1583 ThreadID tid = inst->threadNumber;
1584
1585 iewExecutedInsts++;
1586
1587#if TRACING_ON
1588 if (DTRACE(O3PipeView)) {
1589 inst->completeTick = curTick() - inst->fetchTick;

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1605 if (inst->isLoad()) {
1606 iewExecLoadInsts[tid]++;
1607 }
1608 }
1609}
1610
1611template <class Impl>
1612void
1613DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1613DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1614{
1615 ThreadID tid = inst->threadNumber;
1616
1617 if (!fetchRedirect[tid] ||
1618 !toCommit->squash[tid] ||
1619 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1620
1621 if (inst->mispredicted()) {

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1615 ThreadID tid = inst->threadNumber;
1616
1617 if (!fetchRedirect[tid] ||
1618 !toCommit->squash[tid] ||
1619 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1620
1621 if (inst->mispredicted()) {

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