iew_impl.hh (11650:fe601d7bd955) iew_impl.hh (12105:742d80361989)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1428 // E.g. Strictly ordered loads have not actually executed when they
1429 // are first sent to commit. Instead commit must tell the LSQ
1430 // when it's ready to execute the strictly ordered load.
1431 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1432 int dependents = instQueue.wakeDependents(inst);
1433
1434 for (int i = 0; i < inst->numDestRegs(); i++) {
1435 //mark as Ready
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 1419 unchanged lines hidden (view full) ---

1428 // E.g. Strictly ordered loads have not actually executed when they
1429 // are first sent to commit. Instead commit must tell the LSQ
1430 // when it's ready to execute the strictly ordered load.
1431 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1432 int dependents = instQueue.wakeDependents(inst);
1433
1434 for (int i = 0; i < inst->numDestRegs(); i++) {
1435 //mark as Ready
1436 DPRINTF(IEW,"Setting Destination Register %i\n",
1437 inst->renamedDestRegIdx(i));
1436 DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1437 inst->renamedDestRegIdx(i)->regIdx,
1438 RegClassStrings[inst->renamedDestRegIdx(i)->regClass]);
1438 scoreboard->setReg(inst->renamedDestRegIdx(i));
1439 }
1440
1441 if (dependents) {
1442 producerInst[tid]++;
1443 consumerInst[tid]+= dependents;
1444 }
1445 writebackCount[tid]++;

--- 196 unchanged lines hidden --- 		1439 scoreboard->setReg(inst->renamedDestRegIdx(i));
1440 }
1441
1442 if (dependents) {
1443 producerInst[tid]++;
1444 consumerInst[tid]+= dependents;
1445 }
1446 writebackCount[tid]++;

--- 196 unchanged lines hidden ---