iew_impl.hh (10328:867b536a68be) iew_impl.hh (10333:6be8945d226b)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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525 toCommit->includeSquashInst[tid] = true;
526
527 wroteToTimeBuffer = true;
528 }
529}
530
531template<class Impl>
532void
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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525 toCommit->includeSquashInst[tid] = true;
526
527 wroteToTimeBuffer = true;
528 }
529}
530
531template<class Impl>
532void
533DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
534{
535 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
536 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
537 if (!toCommit->squash[tid] ||
538 inst->seqNum < toCommit->squashedSeqNum[tid]) {
539 toCommit->squash[tid] = true;
540
541 toCommit->squashedSeqNum[tid] = inst->seqNum;
542 toCommit->pc[tid] = inst->pcState();
543 toCommit->mispredictInst[tid] = NULL;
544
545 // Must include the broadcasted SN in the squash.
546 toCommit->includeSquashInst[tid] = true;
547
548 ldstQueue.setLoadBlockedHandled(tid);
549
550 wroteToTimeBuffer = true;
551 }
552}
553
554template<class Impl>
555void
556DefaultIEW<Impl>::block(ThreadID tid)
557{
558 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
559
560 if (dispatchStatus[tid] != Blocked &&
561 dispatchStatus[tid] != Unblocking) {
562 toRename->iewBlock[tid] = true;
563 wroteToTimeBuffer = true;

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605void
606DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
607{
608 instQueue.replayMemInst(inst);
609}
610
611template<class Impl>
612void
533DefaultIEW<Impl>::block(ThreadID tid)
534{
535 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
536
537 if (dispatchStatus[tid] != Blocked &&
538 dispatchStatus[tid] != Unblocking) {
539 toRename->iewBlock[tid] = true;
540 wroteToTimeBuffer = true;

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582void
583DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
584{
585 instQueue.replayMemInst(inst);
586}
587
588template<class Impl>
589void
590DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst)
591{
592 instQueue.blockMemInst(inst);
593}
594
595template<class Impl>
596void
597DefaultIEW<Impl>::cacheUnblocked()
598{
599 instQueue.cacheUnblocked();
600}
601
602template<class Impl>
603void
613DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
614{
615 // This function should not be called after writebackInsts in a
616 // single cycle. That will cause problems with an instruction
617 // being added to the queue to commit without being processed by
618 // writebackInsts prior to being sent to commit.
619
620 // First check the time slot that this instruction will write

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1371
1372 // Tell the instruction queue that a violation has occured.
1373 instQueue.violation(inst, violator);
1374
1375 // Squash.
1376 squashDueToMemOrder(violator, tid);
1377
1378 ++memOrderViolationEvents;
604DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
605{
606 // This function should not be called after writebackInsts in a
607 // single cycle. That will cause problems with an instruction
608 // being added to the queue to commit without being processed by
609 // writebackInsts prior to being sent to commit.
610
611 // First check the time slot that this instruction will write

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1362
1363 // Tell the instruction queue that a violation has occured.
1364 instQueue.violation(inst, violator);
1365
1366 // Squash.
1367 squashDueToMemOrder(violator, tid);
1368
1369 ++memOrderViolationEvents;
1379 } else if (ldstQueue.loadBlocked(tid) &&
1380 !ldstQueue.isLoadBlockedHandled(tid)) {
1381 fetchRedirect[tid] = true;
1382
1383 DPRINTF(IEW, "Load operation couldn't execute because the "
1384 "memory system is blocked. PC: %s [sn:%lli]\n",
1385 inst->pcState(), inst->seqNum);
1386
1387 squashDueToMemBlocked(inst, tid);
1388 }
1389 } else {
1390 // Reset any state associated with redirects that will not
1391 // be used.
1392 if (ldstQueue.violation(tid)) {
1393 assert(inst->isMemRef());
1394
1395 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1396
1397 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1398 "%s, inst PC: %s. Addr is: %#x.\n",
1399 violator->pcState(), inst->pcState(),
1400 inst->physEffAddr);
1401 DPRINTF(IEW, "Violation will not be handled because "
1402 "already squashing\n");
1403
1404 ++memOrderViolationEvents;
1405 }
1370 }
1371 } else {
1372 // Reset any state associated with redirects that will not
1373 // be used.
1374 if (ldstQueue.violation(tid)) {
1375 assert(inst->isMemRef());
1376
1377 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1378
1379 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1380 "%s, inst PC: %s. Addr is: %#x.\n",
1381 violator->pcState(), inst->pcState(),
1382 inst->physEffAddr);
1383 DPRINTF(IEW, "Violation will not be handled because "
1384 "already squashing\n");
1385
1386 ++memOrderViolationEvents;
1387 }
1406 if (ldstQueue.loadBlocked(tid) &&
1407 !ldstQueue.isLoadBlockedHandled(tid)) {
1408 DPRINTF(IEW, "Load operation couldn't execute because the "
1409 "memory system is blocked. PC: %s [sn:%lli]\n",
1410 inst->pcState(), inst->seqNum);
1411 DPRINTF(IEW, "Blocked load will not be handled because "
1412 "already squashing\n");
1413
1414 ldstQueue.setLoadBlockedHandled(tid);
1415 }
1416
1417 }
1418 }
1419
1420 // Update and record activity if we processed any instructions.
1421 if (inst_num) {
1422 if (exeStatus == Idle) {
1423 exeStatus = Running;
1424 }

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1389 }
1390
1391 // Update and record activity if we processed any instructions.
1392 if (inst_num) {
1393 if (exeStatus == Idle) {
1394 exeStatus = Running;
1395 }

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