iew_impl.hh (10327:5b6279635c49) iew_impl.hh (10328:867b536a68be)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
101
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
104
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
101
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
104
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
107 stalls[tid].commit = false;
108 fetchRedirect[tid] = false;
109 }
110
111 updateLSQNextCycle = false;
112
107 fetchRedirect[tid] = false;
108 }
109
110 updateLSQNextCycle = false;
111
113 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
114}
115
116template <class Impl>
117std::string
118DefaultIEW<Impl>::name() const
119{
120 return cpu->name() + ".iew";
121}

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429 ldstQueue.takeOverFrom();
430 fuPool->takeOverFrom();
431
432 startupStage();
433 cpu->activityThisCycle();
434
435 for (ThreadID tid = 0; tid < numThreads; tid++) {
436 dispatchStatus[tid] = Running;
113}
114
115template <class Impl>
116std::string
117DefaultIEW<Impl>::name() const
118{
119 return cpu->name() + ".iew";
120}

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428 ldstQueue.takeOverFrom();
429 fuPool->takeOverFrom();
430
431 startupStage();
432 cpu->activityThisCycle();
433
434 for (ThreadID tid = 0; tid < numThreads; tid++) {
435 dispatchStatus[tid] = Running;
437 stalls[tid].commit = false;
438 fetchRedirect[tid] = false;
439 }
440
441 updateLSQNextCycle = false;
442
443 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
444 issueToExecQueue.advance();
445 }

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756void
757DefaultIEW<Impl>::resetEntries()
758{
759 instQueue.resetEntries();
760 ldstQueue.resetEntries();
761}
762
763template <class Impl>
436 fetchRedirect[tid] = false;
437 }
438
439 updateLSQNextCycle = false;
440
441 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
442 issueToExecQueue.advance();
443 }

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754void
755DefaultIEW<Impl>::resetEntries()
756{
757 instQueue.resetEntries();
758 ldstQueue.resetEntries();
759}
760
761template <class Impl>
764void
765DefaultIEW<Impl>::readStallSignals(ThreadID tid)
766{
767 if (fromCommit->commitBlock[tid]) {
768 stalls[tid].commit = true;
769 }
770
771 if (fromCommit->commitUnblock[tid]) {
772 assert(stalls[tid].commit);
773 stalls[tid].commit = false;
774 }
775}
776
777template <class Impl>
778bool
779DefaultIEW<Impl>::checkStall(ThreadID tid)
780{
781 bool ret_val(false);
782
762bool
763DefaultIEW<Impl>::checkStall(ThreadID tid)
764{
765 bool ret_val(false);
766
783 if (stalls[tid].commit) {
767 if (fromCommit->commitInfo[tid].robSquashing) {
784 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
785 ret_val = true;
786 } else if (instQueue.isFull(tid)) {
787 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
788 ret_val = true;
789 }
790
791 return ret_val;

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797{
798 // Check if there's a squash signal, squash if there is
799 // Check stall signals, block if there is.
800 // If status was Blocked
801 // if so then go to unblocking
802 // If status was Squashing
803 // check if squashing is not high. Switch to running this cycle.
804
768 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
769 ret_val = true;
770 } else if (instQueue.isFull(tid)) {
771 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
772 ret_val = true;
773 }
774
775 return ret_val;

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781{
782 // Check if there's a squash signal, squash if there is
783 // Check stall signals, block if there is.
784 // If status was Blocked
785 // if so then go to unblocking
786 // If status was Squashing
787 // check if squashing is not high. Switch to running this cycle.
788
805 readStallSignals(tid);
806
807 if (fromCommit->commitInfo[tid].squash) {
808 squash(tid);
809
810 if (dispatchStatus[tid] == Blocked ||
811 dispatchStatus[tid] == Unblocking) {
812 toRename->iewUnblock[tid] = true;
813 wroteToTimeBuffer = true;
814 }

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819 }
820
821 if (fromCommit->commitInfo[tid].robSquashing) {
822 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
823
824 dispatchStatus[tid] = Squashing;
825 emptyRenameInsts(tid);
826 wroteToTimeBuffer = true;
789 if (fromCommit->commitInfo[tid].squash) {
790 squash(tid);
791
792 if (dispatchStatus[tid] == Blocked ||
793 dispatchStatus[tid] == Unblocking) {
794 toRename->iewUnblock[tid] = true;
795 wroteToTimeBuffer = true;
796 }

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801 }
802
803 if (fromCommit->commitInfo[tid].robSquashing) {
804 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
805
806 dispatchStatus[tid] = Squashing;
807 emptyRenameInsts(tid);
808 wroteToTimeBuffer = true;
827 return;
828 }
829
830 if (checkStall(tid)) {
831 block(tid);
832 dispatchStatus[tid] = Blocked;
833 return;
834 }
835

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810
811 if (checkStall(tid)) {
812 block(tid);
813 dispatchStatus[tid] = Blocked;
814 return;
815 }
816

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