iew_impl.hh (10172:790a214be1f4) iew_impl.hh (10231:cb2e6950956d)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
488 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
488 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489
490 if (toCommit->squash[tid] == false ||
490 if (!toCommit->squash[tid] ||
491 inst->seqNum < toCommit->squashedSeqNum[tid]) {
492 toCommit->squash[tid] = true;
493 toCommit->squashedSeqNum[tid] = inst->seqNum;
494 toCommit->branchTaken[tid] = inst->pcState().branching();
495
496 TheISA::PCState pc = inst->pcState();
497 TheISA::advancePC(pc, inst->staticInst);
498

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512 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
513 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
514 // Need to include inst->seqNum in the following comparison to cover the
515 // corner case when a branch misprediction and a memory violation for the
516 // same instruction (e.g. load PC) are detected in the same cycle. In this
517 // case the memory violator should take precedence over the branch
518 // misprediction because it requires the violator itself to be included in
519 // the squash.
491 inst->seqNum < toCommit->squashedSeqNum[tid]) {
492 toCommit->squash[tid] = true;
493 toCommit->squashedSeqNum[tid] = inst->seqNum;
494 toCommit->branchTaken[tid] = inst->pcState().branching();
495
496 TheISA::PCState pc = inst->pcState();
497 TheISA::advancePC(pc, inst->staticInst);
498

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512 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
513 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
514 // Need to include inst->seqNum in the following comparison to cover the
515 // corner case when a branch misprediction and a memory violation for the
516 // same instruction (e.g. load PC) are detected in the same cycle. In this
517 // case the memory violator should take precedence over the branch
518 // misprediction because it requires the violator itself to be included in
519 // the squash.
520 if (toCommit->squash[tid] == false ||
520 if (!toCommit->squash[tid] ||
521 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
522 toCommit->squash[tid] = true;
523
524 toCommit->squashedSeqNum[tid] = inst->seqNum;
525 toCommit->pc[tid] = inst->pcState();
526 toCommit->mispredictInst[tid] = NULL;
527
528 // Must include the memory violator in the squash.

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533}
534
535template<class Impl>
536void
537DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
538{
539 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
540 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
521 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
522 toCommit->squash[tid] = true;
523
524 toCommit->squashedSeqNum[tid] = inst->seqNum;
525 toCommit->pc[tid] = inst->pcState();
526 toCommit->mispredictInst[tid] = NULL;
527
528 // Must include the memory violator in the squash.

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533}
534
535template<class Impl>
536void
537DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
538{
539 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
540 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
541 if (toCommit->squash[tid] == false ||
541 if (!toCommit->squash[tid] ||
542 inst->seqNum < toCommit->squashedSeqNum[tid]) {
543 toCommit->squash[tid] = true;
544
545 toCommit->squashedSeqNum[tid] = inst->seqNum;
546 toCommit->pc[tid] = inst->pcState();
547 toCommit->mispredictInst[tid] = NULL;
548
549 // Must include the broadcasted SN in the squash.

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1309 // instruction must be deferred.
1310 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1311 "store.\n");
1312 instQueue.deferMemInst(inst);
1313 continue;
1314 }
1315
1316 // If the store had a fault then it may not have a mem req
542 inst->seqNum < toCommit->squashedSeqNum[tid]) {
543 toCommit->squash[tid] = true;
544
545 toCommit->squashedSeqNum[tid] = inst->seqNum;
546 toCommit->pc[tid] = inst->pcState();
547 toCommit->mispredictInst[tid] = NULL;
548
549 // Must include the broadcasted SN in the squash.

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1309 // instruction must be deferred.
1310 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1311 "store.\n");
1312 instQueue.deferMemInst(inst);
1313 continue;
1314 }
1315
1316 // If the store had a fault then it may not have a mem req
1317 if (fault != NoFault || inst->readPredicate() == false ||
1317 if (fault != NoFault || !inst->readPredicate() ||
1318 !inst->isStoreConditional()) {
1319 // If the instruction faulted, then we need to send it along
1320 // to commit without the instruction completing.
1321 // Send this instruction to commit, also make sure iew stage
1322 // realizes there is activity.
1323 inst->setExecuted();
1324 instToCommit(inst);
1325 activityThisCycle();

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1334
1335 } else {
1336 // If the instruction has already faulted, then skip executing it.
1337 // Such case can happen when it faulted during ITLB translation.
1338 // If we execute the instruction (even if it's a nop) the fault
1339 // will be replaced and we will lose it.
1340 if (inst->getFault() == NoFault) {
1341 inst->execute();
1318 !inst->isStoreConditional()) {
1319 // If the instruction faulted, then we need to send it along
1320 // to commit without the instruction completing.
1321 // Send this instruction to commit, also make sure iew stage
1322 // realizes there is activity.
1323 inst->setExecuted();
1324 instToCommit(inst);
1325 activityThisCycle();

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1334
1335 } else {
1336 // If the instruction has already faulted, then skip executing it.
1337 // Such case can happen when it faulted during ITLB translation.
1338 // If we execute the instruction (even if it's a nop) the fault
1339 // will be replaced and we will lose it.
1340 if (inst->getFault() == NoFault) {
1341 inst->execute();
1342 if (inst->readPredicate() == false)
1342 if (!inst->readPredicate())
1343 inst->forwardOldRegs();
1344 }
1345
1346 inst->setExecuted();
1347
1348 instToCommit(inst);
1349 }
1350

--- 352 unchanged lines hidden --- 		1343 inst->forwardOldRegs();
1344 }
1345
1346 inst->setExecuted();
1347
1348 instToCommit(inst);
1349 }
1350

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