1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31// @todo: Fix the instantaneous communication among all the stages within 32// iew. There's a clear delay between issue and execute, yet backwards 33// communication happens simultaneously. 34 35#include <queue> 36 37#include "base/timebuf.hh" 38#include "cpu/o3/fu_pool.hh" 39#include "cpu/o3/iew.hh" 40 41template<class Impl> 42DefaultIEW<Impl>::DefaultIEW(Params *params) 43 : issueToExecQueue(params->backComSize, params->forwardComSize), 44 instQueue(params), 45 ldstQueue(params), 46 fuPool(params->fuPool), 47 commitToIEWDelay(params->commitToIEWDelay), 48 renameToIEWDelay(params->renameToIEWDelay), 49 issueToExecuteDelay(params->issueToExecuteDelay), 50 dispatchWidth(params->dispatchWidth), 51 issueWidth(params->issueWidth), 52 wbOutstanding(0), 53 wbWidth(params->wbWidth), 54 numThreads(params->numberOfThreads), 55 switchedOut(false) 56{ 57 _status = Active; 58 exeStatus = Running; 59 wbStatus = Idle; 60 61 // Setup wire to read instructions coming from issue. 62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 63 64 // Instruction queue needs the queue between issue and execute. 65 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 66 67 instQueue.setIEW(this); 68 ldstQueue.setIEW(this); 69 70 for (int i=0; i < numThreads; i++) { 71 dispatchStatus[i] = Running; 72 stalls[i].commit = false; 73 fetchRedirect[i] = false; 74 bdelayDoneSeqNum[i] = 0; 75 } 76 77 wbMax = wbWidth * params->wbDepth; 78 79 updateLSQNextCycle = false; 80 81 ableToIssue = true; 82 83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 84} 85 86template <class Impl> 87std::string 88DefaultIEW<Impl>::name() const 89{ 90 return cpu->name() + ".iew"; 91} 92 93template <class Impl> 94void 95DefaultIEW<Impl>::regStats() 96{ 97 using namespace Stats; 98 99 instQueue.regStats(); 100 ldstQueue.regStats(); 101 102 iewIdleCycles 103 .name(name() + ".iewIdleCycles") 104 .desc("Number of cycles IEW is idle"); 105 106 iewSquashCycles 107 .name(name() + ".iewSquashCycles") 108 .desc("Number of cycles IEW is squashing"); 109 110 iewBlockCycles 111 .name(name() + ".iewBlockCycles") 112 .desc("Number of cycles IEW is blocking"); 113 114 iewUnblockCycles 115 .name(name() + ".iewUnblockCycles") 116 .desc("Number of cycles IEW is unblocking"); 117 118 iewDispatchedInsts 119 .name(name() + ".iewDispatchedInsts") 120 .desc("Number of instructions dispatched to IQ"); 121 122 iewDispSquashedInsts 123 .name(name() + ".iewDispSquashedInsts") 124 .desc("Number of squashed instructions skipped by dispatch"); 125 126 iewDispLoadInsts 127 .name(name() + ".iewDispLoadInsts") 128 .desc("Number of dispatched load instructions"); 129 130 iewDispStoreInsts 131 .name(name() + ".iewDispStoreInsts") 132 .desc("Number of dispatched store instructions"); 133 134 iewDispNonSpecInsts 135 .name(name() + ".iewDispNonSpecInsts") 136 .desc("Number of dispatched non-speculative instructions"); 137 138 iewIQFullEvents 139 .name(name() + ".iewIQFullEvents") 140 .desc("Number of times the IQ has become full, causing a stall"); 141 142 iewLSQFullEvents 143 .name(name() + ".iewLSQFullEvents") 144 .desc("Number of times the LSQ has become full, causing a stall"); 145 146 memOrderViolationEvents 147 .name(name() + ".memOrderViolationEvents") 148 .desc("Number of memory order violations"); 149 150 predictedTakenIncorrect 151 .name(name() + ".predictedTakenIncorrect") 152 .desc("Number of branches that were predicted taken incorrectly"); 153 154 predictedNotTakenIncorrect 155 .name(name() + ".predictedNotTakenIncorrect") 156 .desc("Number of branches that were predicted not taken incorrectly"); 157 158 branchMispredicts 159 .name(name() + ".branchMispredicts") 160 .desc("Number of branch mispredicts detected at execute"); 161 162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 163 164 iewExecutedInsts 165 .name(name() + ".iewExecutedInsts") 166 .desc("Number of executed instructions"); 167 168 iewExecLoadInsts 169 .init(cpu->number_of_threads) 170 .name(name() + ".iewExecLoadInsts") 171 .desc("Number of load instructions executed") 172 .flags(total); 173 174 iewExecSquashedInsts 175 .name(name() + ".iewExecSquashedInsts") 176 .desc("Number of squashed instructions skipped in execute"); 177 178 iewExecutedSwp 179 .init(cpu->number_of_threads) 180 .name(name() + ".EXEC:swp") 181 .desc("number of swp insts executed") 182 .flags(total); 183 184 iewExecutedNop 185 .init(cpu->number_of_threads) 186 .name(name() + ".EXEC:nop") 187 .desc("number of nop insts executed") 188 .flags(total); 189 190 iewExecutedRefs 191 .init(cpu->number_of_threads) 192 .name(name() + ".EXEC:refs") 193 .desc("number of memory reference insts executed") 194 .flags(total); 195 196 iewExecutedBranches 197 .init(cpu->number_of_threads) 198 .name(name() + ".EXEC:branches") 199 .desc("Number of branches executed") 200 .flags(total); 201 202 iewExecStoreInsts 203 .name(name() + ".EXEC:stores") 204 .desc("Number of stores executed") 205 .flags(total); 206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 207 208 iewExecRate 209 .name(name() + ".EXEC:rate") 210 .desc("Inst execution rate") 211 .flags(total); 212 213 iewExecRate = iewExecutedInsts / cpu->numCycles; 214 215 iewInstsToCommit 216 .init(cpu->number_of_threads) 217 .name(name() + ".WB:sent") 218 .desc("cumulative count of insts sent to commit") 219 .flags(total); 220 221 writebackCount 222 .init(cpu->number_of_threads) 223 .name(name() + ".WB:count") 224 .desc("cumulative count of insts written-back") 225 .flags(total); 226 227 producerInst 228 .init(cpu->number_of_threads) 229 .name(name() + ".WB:producers") 230 .desc("num instructions producing a value") 231 .flags(total); 232 233 consumerInst 234 .init(cpu->number_of_threads) 235 .name(name() + ".WB:consumers") 236 .desc("num instructions consuming a value") 237 .flags(total); 238 239 wbPenalized 240 .init(cpu->number_of_threads) 241 .name(name() + ".WB:penalized") 242 .desc("number of instrctions required to write to 'other' IQ") 243 .flags(total); 244 245 wbPenalizedRate 246 .name(name() + ".WB:penalized_rate") 247 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 248 .flags(total); 249 250 wbPenalizedRate = wbPenalized / writebackCount; 251 252 wbFanout 253 .name(name() + ".WB:fanout") 254 .desc("average fanout of values written-back") 255 .flags(total); 256 257 wbFanout = producerInst / consumerInst; 258 259 wbRate 260 .name(name() + ".WB:rate") 261 .desc("insts written-back per cycle") 262 .flags(total); 263 wbRate = writebackCount / cpu->numCycles; 264} 265 266template<class Impl> 267void 268DefaultIEW<Impl>::initStage() 269{ 270 for (int tid=0; tid < numThreads; tid++) { 271 toRename->iewInfo[tid].usedIQ = true; 272 toRename->iewInfo[tid].freeIQEntries = 273 instQueue.numFreeEntries(tid); 274 275 toRename->iewInfo[tid].usedLSQ = true; 276 toRename->iewInfo[tid].freeLSQEntries = 277 ldstQueue.numFreeEntries(tid); 278 } 279} 280 281template<class Impl> 282void 283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 284{ 285 DPRINTF(IEW, "Setting CPU pointer.\n"); 286 cpu = cpu_ptr; 287 288 instQueue.setCPU(cpu_ptr); 289 ldstQueue.setCPU(cpu_ptr); 290 291 cpu->activateStage(O3CPU::IEWIdx); 292} 293 294template<class Impl> 295void 296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 297{ 298 DPRINTF(IEW, "Setting time buffer pointer.\n"); 299 timeBuffer = tb_ptr; 300 301 // Setup wire to read information from time buffer, from commit. 302 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 303 304 // Setup wire to write information back to previous stages. 305 toRename = timeBuffer->getWire(0); 306 307 toFetch = timeBuffer->getWire(0); 308 309 // Instruction queue also needs main time buffer. 310 instQueue.setTimeBuffer(tb_ptr); 311} 312 313template<class Impl> 314void 315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 316{ 317 DPRINTF(IEW, "Setting rename queue pointer.\n"); 318 renameQueue = rq_ptr; 319 320 // Setup wire to read information from rename queue. 321 fromRename = renameQueue->getWire(-renameToIEWDelay); 322} 323 324template<class Impl> 325void 326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 327{ 328 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 329 iewQueue = iq_ptr; 330 331 // Setup wire to write instructions to commit. 332 toCommit = iewQueue->getWire(0); 333} 334 335template<class Impl> 336void 337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 338{ 339 DPRINTF(IEW, "Setting active threads list pointer.\n"); 340 activeThreads = at_ptr; 341 342 ldstQueue.setActiveThreads(at_ptr); 343 instQueue.setActiveThreads(at_ptr); 344} 345 346template<class Impl> 347void 348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 349{ 350 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 351 scoreboard = sb_ptr; 352} 353 354template <class Impl> 355bool 356DefaultIEW<Impl>::drain() 357{ 358 // IEW is ready to drain at any time. 359 cpu->signalDrained(); 360 return true; 361} 362 363template <class Impl> 364void 365DefaultIEW<Impl>::resume() 366{ 367} 368 369template <class Impl> 370void 371DefaultIEW<Impl>::switchOut() 372{ 373 // Clear any state. 374 switchedOut = true; 375 assert(insts[0].empty()); 376 assert(skidBuffer[0].empty()); 377 378 instQueue.switchOut(); 379 ldstQueue.switchOut(); 380 fuPool->switchOut(); 381 382 for (int i = 0; i < numThreads; i++) { 383 while (!insts[i].empty()) 384 insts[i].pop(); 385 while (!skidBuffer[i].empty()) 386 skidBuffer[i].pop(); 387 } 388} 389 390template <class Impl> 391void 392DefaultIEW<Impl>::takeOverFrom() 393{ 394 // Reset all state. 395 _status = Active; 396 exeStatus = Running; 397 wbStatus = Idle; 398 switchedOut = false; 399 400 instQueue.takeOverFrom(); 401 ldstQueue.takeOverFrom(); 402 fuPool->takeOverFrom(); 403 404 initStage(); 405 cpu->activityThisCycle(); 406 407 for (int i=0; i < numThreads; i++) { 408 dispatchStatus[i] = Running; 409 stalls[i].commit = false; 410 fetchRedirect[i] = false; 411 } 412 413 updateLSQNextCycle = false; 414 415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 416 issueToExecQueue.advance(); 417 } 418} 419 420template<class Impl> 421void 422DefaultIEW<Impl>::squash(unsigned tid) 423{ 424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 425 tid); 426 427 // Tell the IQ to start squashing. 428 instQueue.squash(tid); 429 430 // Tell the LDSTQ to start squashing. 431#if ISA_HAS_DELAY_SLOT 432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); 433#else 434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 435#endif 436 updatedQueues = true; 437 438 // Clear the skid buffer in case it has any data in it. 439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); 441 442 while (!skidBuffer[tid].empty()) { 443#if ISA_HAS_DELAY_SLOT 444 if (skidBuffer[tid].front()->seqNum <= 445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) { 446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " 447 "that occur before delay slot [sn:%i].\n", 448 fromCommit->commitInfo[tid].bdelayDoneSeqNum, 449 tid); 450 break; 451 } else { 452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from " 453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum); 454 } 455#endif 456 if (skidBuffer[tid].front()->isLoad() || 457 skidBuffer[tid].front()->isStore() ) { 458 toRename->iewInfo[tid].dispatchedToLSQ++; 459 } 460 461 toRename->iewInfo[tid].dispatched++; 462 463 skidBuffer[tid].pop(); 464 } 465 466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 467 468 emptyRenameInsts(tid); 469} 470 471template<class Impl> 472void 473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 474{ 475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483 int instSize = sizeof(TheISA::MachInst); 484#if ISA_HAS_DELAY_SLOT 485 bool branch_taken = 486 !(inst->readNextPC() + instSize == inst->readNextNPC() && 487 (inst->readNextPC() == inst->readPC() + instSize || 488 inst->readNextPC() == inst->readPC() + 2 * instSize)); 489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 490 branch_taken ? "true": "false", inst->seqNum); 491 492 toCommit->branchTaken[tid] = branch_taken; 493 494 bool squashDelaySlot = true; 495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 497 squashDelaySlot ? "true": "false", inst->seqNum); 498 toCommit->squashDelaySlot[tid] = squashDelaySlot; 499 //If we're squashing the delay slot, we need to pick back up at NextPC. 500 //Otherwise, NextPC isn't being squashed, so we should pick back up at 501 //NextNPC. 502 if (squashDelaySlot) { 503 toCommit->nextPC[tid] = inst->readNextPC(); 504 toCommit->nextNPC[tid] = inst->readNextNPC(); 505 } else { 506 toCommit->nextPC[tid] = inst->readNextNPC(); 507 toCommit->nextNPC[tid] = inst->readNextNPC() + instSize; 508 } 509#else 510 toCommit->branchTaken[tid] = inst->readNextPC() != 511 (inst->readPC() + sizeof(TheISA::MachInst)); 512 toCommit->nextPC[tid] = inst->readNextPC(); 513 toCommit->nextNPC[tid] = inst->readNextPC() + instSize; 514#endif 515 516 toCommit->includeSquashInst[tid] = false; 517 518 wroteToTimeBuffer = true; 519} 520 521template<class Impl> 522void 523DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 524{ 525 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 526 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 527 528 toCommit->squash[tid] = true; 529 toCommit->squashedSeqNum[tid] = inst->seqNum; 530 toCommit->nextPC[tid] = inst->readNextPC(); 531#if ISA_HAS_DELAY_SLOT 532 toCommit->nextNPC[tid] = inst->readNextNPC(); 533#else 534 toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst); 535#endif 536 toCommit->branchMispredict[tid] = false; 537 538 toCommit->includeSquashInst[tid] = false; 539 540 wroteToTimeBuffer = true; 541} 542 543template<class Impl> 544void 545DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 546{ 547 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 548 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 549 550 toCommit->squash[tid] = true; 551 toCommit->squashedSeqNum[tid] = inst->seqNum; 552 toCommit->nextPC[tid] = inst->readPC(); 553#if ISA_HAS_DELAY_SLOT 554 toCommit->nextNPC[tid] = inst->readNextPC(); 555#else 556 toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst); 557#endif 558 toCommit->branchMispredict[tid] = false; 559 560 // Must include the broadcasted SN in the squash. 561 toCommit->includeSquashInst[tid] = true; 562 563 ldstQueue.setLoadBlockedHandled(tid); 564 565 wroteToTimeBuffer = true; 566} 567 568template<class Impl> 569void 570DefaultIEW<Impl>::block(unsigned tid) 571{ 572 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 573 574 if (dispatchStatus[tid] != Blocked && 575 dispatchStatus[tid] != Unblocking) { 576 toRename->iewBlock[tid] = true; 577 wroteToTimeBuffer = true; 578 } 579 580 // Add the current inputs to the skid buffer so they can be 581 // reprocessed when this stage unblocks. 582 skidInsert(tid); 583 584 dispatchStatus[tid] = Blocked; 585} 586 587template<class Impl> 588void 589DefaultIEW<Impl>::unblock(unsigned tid) 590{ 591 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 592 "buffer %u.\n",tid, tid); 593 594 // If the skid bufffer is empty, signal back to previous stages to unblock. 595 // Also switch status to running. 596 if (skidBuffer[tid].empty()) { 597 toRename->iewUnblock[tid] = true; 598 wroteToTimeBuffer = true; 599 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 600 dispatchStatus[tid] = Running; 601 } 602} 603 604template<class Impl> 605void 606DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 607{ 608 instQueue.wakeDependents(inst); 609} 610 611template<class Impl> 612void 613DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 614{ 615 instQueue.rescheduleMemInst(inst); 616} 617 618template<class Impl> 619void 620DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 621{ 622 instQueue.replayMemInst(inst); 623} 624 625template<class Impl> 626void 627DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 628{ 629 // This function should not be called after writebackInsts in a 630 // single cycle. That will cause problems with an instruction 631 // being added to the queue to commit without being processed by 632 // writebackInsts prior to being sent to commit. 633 634 // First check the time slot that this instruction will write 635 // to. If there are free write ports at the time, then go ahead 636 // and write the instruction to that time. If there are not, 637 // keep looking back to see where's the first time there's a 638 // free slot. 639 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 640 ++wbNumInst; 641 if (wbNumInst == wbWidth) { 642 ++wbCycle; 643 wbNumInst = 0; 644 } 645 646 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 647 } 648 649 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 650 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 651 // Add finished instruction to queue to commit. 652 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 653 (*iewQueue)[wbCycle].size++; 654} 655 656template <class Impl> 657unsigned 658DefaultIEW<Impl>::validInstsFromRename() 659{ 660 unsigned inst_count = 0; 661 662 for (int i=0; i<fromRename->size; i++) { 663 if (!fromRename->insts[i]->isSquashed()) 664 inst_count++; 665 } 666 667 return inst_count; 668} 669 670template<class Impl> 671void 672DefaultIEW<Impl>::skidInsert(unsigned tid) 673{ 674 DynInstPtr inst = NULL; 675 676 while (!insts[tid].empty()) { 677 inst = insts[tid].front(); 678 679 insts[tid].pop(); 680 681 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 682 "dispatch skidBuffer %i\n",tid, inst->seqNum, 683 inst->readPC(),tid); 684 685 skidBuffer[tid].push(inst); 686 } 687 688 assert(skidBuffer[tid].size() <= skidBufferMax && 689 "Skidbuffer Exceeded Max Size"); 690} 691 692template<class Impl> 693int 694DefaultIEW<Impl>::skidCount() 695{ 696 int max=0; 697
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698 std::list<unsigned>::iterator threads = (*activeThreads).begin();
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698 std::list<unsigned>::iterator threads = activeThreads->begin(); 699 std::list<unsigned>::iterator end = activeThreads->end(); |
700
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700 while (threads != (*activeThreads).end()) {
701 unsigned thread_count = skidBuffer[*threads++].size();
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701 while (threads != end) { 702 unsigned tid = *threads++; 703 unsigned thread_count = skidBuffer[tid].size(); |
704 if (max < thread_count) 705 max = thread_count; 706 } 707 708 return max; 709} 710 711template<class Impl> 712bool 713DefaultIEW<Impl>::skidsEmpty() 714{
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713 std::list<unsigned>::iterator threads = (*activeThreads).begin();
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715 std::list<unsigned>::iterator threads = activeThreads->begin(); 716 std::list<unsigned>::iterator end = activeThreads->end(); |
717
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715 while (threads != (*activeThreads).end()) {
716 if (!skidBuffer[*threads++].empty())
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718 while (threads != end) { 719 unsigned tid = *threads++; 720 721 if (!skidBuffer[tid].empty()) |
722 return false; 723 } 724 725 return true; 726} 727 728template <class Impl> 729void 730DefaultIEW<Impl>::updateStatus() 731{ 732 bool any_unblocking = false; 733
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729 std::list<unsigned>::iterator threads = (*activeThreads).begin();
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734 std::list<unsigned>::iterator threads = activeThreads->begin(); 735 std::list<unsigned>::iterator end = activeThreads->end(); |
736
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731 threads = (*activeThreads).begin();
732
733 while (threads != (*activeThreads).end()) {
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737 while (threads != end) { |
738 unsigned tid = *threads++; 739 740 if (dispatchStatus[tid] == Unblocking) { 741 any_unblocking = true; 742 break; 743 } 744 } 745 746 // If there are no ready instructions waiting to be scheduled by the IQ, 747 // and there's no stores waiting to write back, and dispatch is not 748 // unblocking, then there is no internal activity for the IEW stage. 749 if (_status == Active && !instQueue.hasReadyInsts() && 750 !ldstQueue.willWB() && !any_unblocking) { 751 DPRINTF(IEW, "IEW switching to idle\n"); 752 753 deactivateStage(); 754 755 _status = Inactive; 756 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 757 ldstQueue.willWB() || 758 any_unblocking)) { 759 // Otherwise there is internal activity. Set to active. 760 DPRINTF(IEW, "IEW switching to active\n"); 761 762 activateStage(); 763 764 _status = Active; 765 } 766} 767 768template <class Impl> 769void 770DefaultIEW<Impl>::resetEntries() 771{ 772 instQueue.resetEntries(); 773 ldstQueue.resetEntries(); 774} 775 776template <class Impl> 777void 778DefaultIEW<Impl>::readStallSignals(unsigned tid) 779{ 780 if (fromCommit->commitBlock[tid]) { 781 stalls[tid].commit = true; 782 } 783 784 if (fromCommit->commitUnblock[tid]) { 785 assert(stalls[tid].commit); 786 stalls[tid].commit = false; 787 } 788} 789 790template <class Impl> 791bool 792DefaultIEW<Impl>::checkStall(unsigned tid) 793{ 794 bool ret_val(false); 795 796 if (stalls[tid].commit) { 797 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 798 ret_val = true; 799 } else if (instQueue.isFull(tid)) { 800 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 801 ret_val = true; 802 } else if (ldstQueue.isFull(tid)) { 803 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 804 805 if (ldstQueue.numLoads(tid) > 0 ) { 806 807 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 808 tid,ldstQueue.getLoadHeadSeqNum(tid)); 809 } 810 811 if (ldstQueue.numStores(tid) > 0) { 812 813 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 814 tid,ldstQueue.getStoreHeadSeqNum(tid)); 815 } 816 817 ret_val = true; 818 } else if (ldstQueue.isStalled(tid)) { 819 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 820 ret_val = true; 821 } 822 823 return ret_val; 824} 825 826template <class Impl> 827void 828DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 829{ 830 // Check if there's a squash signal, squash if there is 831 // Check stall signals, block if there is. 832 // If status was Blocked 833 // if so then go to unblocking 834 // If status was Squashing 835 // check if squashing is not high. Switch to running this cycle. 836 837 readStallSignals(tid); 838 839 if (fromCommit->commitInfo[tid].squash) { 840 squash(tid); 841 842 if (dispatchStatus[tid] == Blocked || 843 dispatchStatus[tid] == Unblocking) { 844 toRename->iewUnblock[tid] = true; 845 wroteToTimeBuffer = true; 846 } 847 848 dispatchStatus[tid] = Squashing; 849 850 fetchRedirect[tid] = false; 851 return; 852 } 853 854 if (fromCommit->commitInfo[tid].robSquashing) { 855 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 856 857 dispatchStatus[tid] = Squashing; 858 859 emptyRenameInsts(tid); 860 wroteToTimeBuffer = true; 861 return; 862 } 863 864 if (checkStall(tid)) { 865 block(tid); 866 dispatchStatus[tid] = Blocked; 867 return; 868 } 869 870 if (dispatchStatus[tid] == Blocked) { 871 // Status from previous cycle was blocked, but there are no more stall 872 // conditions. Switch over to unblocking. 873 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 874 tid); 875 876 dispatchStatus[tid] = Unblocking; 877 878 unblock(tid); 879 880 return; 881 } 882 883 if (dispatchStatus[tid] == Squashing) { 884 // Switch status to running if rename isn't being told to block or 885 // squash this cycle. 886 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 887 tid); 888 889 dispatchStatus[tid] = Running; 890 891 return; 892 } 893} 894 895template <class Impl> 896void 897DefaultIEW<Impl>::sortInsts() 898{ 899 int insts_from_rename = fromRename->size; 900#ifdef DEBUG 901#if !ISA_HAS_DELAY_SLOT 902 for (int i = 0; i < numThreads; i++) 903 assert(insts[i].empty()); 904#endif 905#endif 906 for (int i = 0; i < insts_from_rename; ++i) { 907 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 908 } 909} 910 911template <class Impl> 912void 913DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 914{ 915 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until " 916 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); 917 918 while (!insts[tid].empty()) { 919#if ISA_HAS_DELAY_SLOT 920 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { 921 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" 922 " that occurs at or before delay slot [sn:%i].\n", 923 tid, bdelayDoneSeqNum[tid]); 924 break; 925 } else { 926 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction " 927 "[sn:%i].\n", tid, insts[tid].front()->seqNum); 928 } 929#endif 930 931 if (insts[tid].front()->isLoad() || 932 insts[tid].front()->isStore() ) { 933 toRename->iewInfo[tid].dispatchedToLSQ++; 934 } 935 936 toRename->iewInfo[tid].dispatched++; 937 938 insts[tid].pop(); 939 } 940} 941 942template <class Impl> 943void 944DefaultIEW<Impl>::wakeCPU() 945{ 946 cpu->wakeCPU(); 947} 948 949template <class Impl> 950void 951DefaultIEW<Impl>::activityThisCycle() 952{ 953 DPRINTF(Activity, "Activity this cycle.\n"); 954 cpu->activityThisCycle(); 955} 956 957template <class Impl> 958inline void 959DefaultIEW<Impl>::activateStage() 960{ 961 DPRINTF(Activity, "Activating stage.\n"); 962 cpu->activateStage(O3CPU::IEWIdx); 963} 964 965template <class Impl> 966inline void 967DefaultIEW<Impl>::deactivateStage() 968{ 969 DPRINTF(Activity, "Deactivating stage.\n"); 970 cpu->deactivateStage(O3CPU::IEWIdx); 971} 972 973template<class Impl> 974void 975DefaultIEW<Impl>::dispatch(unsigned tid) 976{ 977 // If status is Running or idle, 978 // call dispatchInsts() 979 // If status is Unblocking, 980 // buffer any instructions coming from rename 981 // continue trying to empty skid buffer 982 // check if stall conditions have passed 983 984 if (dispatchStatus[tid] == Blocked) { 985 ++iewBlockCycles; 986 987 } else if (dispatchStatus[tid] == Squashing) { 988 ++iewSquashCycles; 989 } 990 991 // Dispatch should try to dispatch as many instructions as its bandwidth 992 // will allow, as long as it is not currently blocked. 993 if (dispatchStatus[tid] == Running || 994 dispatchStatus[tid] == Idle) { 995 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 996 "dispatch.\n", tid); 997 998 dispatchInsts(tid); 999 } else if (dispatchStatus[tid] == Unblocking) { 1000 // Make sure that the skid buffer has something in it if the 1001 // status is unblocking. 1002 assert(!skidsEmpty()); 1003 1004 // If the status was unblocking, then instructions from the skid 1005 // buffer were used. Remove those instructions and handle 1006 // the rest of unblocking. 1007 dispatchInsts(tid); 1008 1009 ++iewUnblockCycles; 1010 1011 if (validInstsFromRename() && dispatchedAllInsts) { 1012 // Add the current inputs to the skid buffer so they can be 1013 // reprocessed when this stage unblocks. 1014 skidInsert(tid); 1015 } 1016 1017 unblock(tid); 1018 } 1019} 1020 1021template <class Impl> 1022void 1023DefaultIEW<Impl>::dispatchInsts(unsigned tid) 1024{ 1025 dispatchedAllInsts = true; 1026 1027 // Obtain instructions from skid buffer if unblocking, or queue from rename 1028 // otherwise. 1029 std::queue<DynInstPtr> &insts_to_dispatch = 1030 dispatchStatus[tid] == Unblocking ? 1031 skidBuffer[tid] : insts[tid]; 1032 1033 int insts_to_add = insts_to_dispatch.size(); 1034 1035 DynInstPtr inst; 1036 bool add_to_iq = false; 1037 int dis_num_inst = 0; 1038 1039 // Loop through the instructions, putting them in the instruction 1040 // queue. 1041 for ( ; dis_num_inst < insts_to_add && 1042 dis_num_inst < dispatchWidth; 1043 ++dis_num_inst) 1044 { 1045 inst = insts_to_dispatch.front(); 1046 1047 if (dispatchStatus[tid] == Unblocking) { 1048 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 1049 "buffer\n", tid); 1050 } 1051 1052 // Make sure there's a valid instruction there. 1053 assert(inst); 1054 1055 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 1056 "IQ.\n", 1057 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 1058 1059 // Be sure to mark these instructions as ready so that the 1060 // commit stage can go ahead and execute them, and mark 1061 // them as issued so the IQ doesn't reprocess them. 1062 1063 // Check for squashed instructions. 1064 if (inst->isSquashed()) { 1065 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1066 "not adding to IQ.\n", tid); 1067 1068 ++iewDispSquashedInsts; 1069 1070 insts_to_dispatch.pop(); 1071 1072 //Tell Rename That An Instruction has been processed 1073 if (inst->isLoad() || inst->isStore()) { 1074 toRename->iewInfo[tid].dispatchedToLSQ++; 1075 } 1076 toRename->iewInfo[tid].dispatched++; 1077 1078 continue; 1079 } 1080 1081 // Check for full conditions. 1082 if (instQueue.isFull(tid)) { 1083 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1084 1085 // Call function to start blocking. 1086 block(tid); 1087 1088 // Set unblock to false. Special case where we are using 1089 // skidbuffer (unblocking) instructions but then we still 1090 // get full in the IQ. 1091 toRename->iewUnblock[tid] = false; 1092 1093 dispatchedAllInsts = false; 1094 1095 ++iewIQFullEvents; 1096 break; 1097 } else if (ldstQueue.isFull(tid)) { 1098 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1099 1100 // Call function to start blocking. 1101 block(tid); 1102 1103 // Set unblock to false. Special case where we are using 1104 // skidbuffer (unblocking) instructions but then we still 1105 // get full in the IQ. 1106 toRename->iewUnblock[tid] = false; 1107 1108 dispatchedAllInsts = false; 1109 1110 ++iewLSQFullEvents; 1111 break; 1112 } 1113 1114 // Otherwise issue the instruction just fine. 1115 if (inst->isLoad()) { 1116 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1117 "encountered, adding to LSQ.\n", tid); 1118 1119 // Reserve a spot in the load store queue for this 1120 // memory access. 1121 ldstQueue.insertLoad(inst); 1122 1123 ++iewDispLoadInsts; 1124 1125 add_to_iq = true; 1126 1127 toRename->iewInfo[tid].dispatchedToLSQ++; 1128 } else if (inst->isStore()) { 1129 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1130 "encountered, adding to LSQ.\n", tid); 1131 1132 ldstQueue.insertStore(inst); 1133 1134 ++iewDispStoreInsts; 1135 1136 if (inst->isStoreConditional()) { 1137 // Store conditionals need to be set as "canCommit()" 1138 // so that commit can process them when they reach the 1139 // head of commit. 1140 // @todo: This is somewhat specific to Alpha. 1141 inst->setCanCommit(); 1142 instQueue.insertNonSpec(inst); 1143 add_to_iq = false; 1144 1145 ++iewDispNonSpecInsts; 1146 } else { 1147 add_to_iq = true; 1148 } 1149 1150 toRename->iewInfo[tid].dispatchedToLSQ++;
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1147#if FULL_SYSTEM
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1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1152 // Same as non-speculative stores. 1153 inst->setCanCommit(); 1154 instQueue.insertBarrier(inst); 1155 add_to_iq = false;
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1153#endif
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1156 } else if (inst->isNonSpeculative()) { 1157 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1158 "encountered, skipping.\n", tid); 1159 1160 // Same as non-speculative stores. 1161 inst->setCanCommit(); 1162 1163 // Specifically insert it as nonspeculative. 1164 instQueue.insertNonSpec(inst); 1165 1166 ++iewDispNonSpecInsts; 1167 1168 add_to_iq = false; 1169 } else if (inst->isNop()) { 1170 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1171 "skipping.\n", tid); 1172 1173 inst->setIssued(); 1174 inst->setExecuted(); 1175 inst->setCanCommit(); 1176 1177 instQueue.recordProducer(inst); 1178 1179 iewExecutedNop[tid]++; 1180 1181 add_to_iq = false; 1182 } else if (inst->isExecuted()) { 1183 assert(0 && "Instruction shouldn't be executed.\n"); 1184 DPRINTF(IEW, "Issue: Executed branch encountered, " 1185 "skipping.\n"); 1186 1187 inst->setIssued(); 1188 inst->setCanCommit(); 1189 1190 instQueue.recordProducer(inst); 1191 1192 add_to_iq = false; 1193 } else { 1194 add_to_iq = true; 1195 } 1196 1197 // If the instruction queue is not full, then add the 1198 // instruction. 1199 if (add_to_iq) { 1200 instQueue.insert(inst); 1201 } 1202 1203 insts_to_dispatch.pop(); 1204 1205 toRename->iewInfo[tid].dispatched++; 1206 1207 ++iewDispatchedInsts; 1208 } 1209 1210 if (!insts_to_dispatch.empty()) { 1211 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1212 block(tid); 1213 toRename->iewUnblock[tid] = false; 1214 } 1215 1216 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1217 dispatchStatus[tid] = Running; 1218 1219 updatedQueues = true; 1220 } 1221 1222 dis_num_inst = 0; 1223} 1224 1225template <class Impl> 1226void 1227DefaultIEW<Impl>::printAvailableInsts() 1228{ 1229 int inst = 0; 1230 1231 std::cout << "Available Instructions: "; 1232 1233 while (fromIssue->insts[inst]) { 1234 1235 if (inst%3==0) std::cout << "\n\t"; 1236 1237 std::cout << "PC: " << fromIssue->insts[inst]->readPC() 1238 << " TN: " << fromIssue->insts[inst]->threadNumber 1239 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1240 1241 inst++; 1242 1243 } 1244 1245 std::cout << "\n"; 1246} 1247 1248template <class Impl> 1249void 1250DefaultIEW<Impl>::executeInsts() 1251{ 1252 wbNumInst = 0; 1253 wbCycle = 0; 1254
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1253 std::list<unsigned>::iterator threads = (*activeThreads).begin();
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1255 std::list<unsigned>::iterator threads = activeThreads->begin(); 1256 std::list<unsigned>::iterator end = activeThreads->end(); |
1257
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1255 while (threads != (*activeThreads).end()) {
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1258 while (threads != end) { |
1259 unsigned tid = *threads++; 1260 fetchRedirect[tid] = false; 1261 } 1262 1263 // Uncomment this if you want to see all available instructions. 1264// printAvailableInsts(); 1265 1266 // Execute/writeback any instructions that are available. 1267 int insts_to_execute = fromIssue->size; 1268 int inst_num = 0; 1269 for (; inst_num < insts_to_execute; 1270 ++inst_num) { 1271 1272 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1273 1274 DynInstPtr inst = instQueue.getInstToExecute(); 1275 1276 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1277 inst->readPC(), inst->threadNumber,inst->seqNum); 1278 1279 // Check if the instruction is squashed; if so then skip it 1280 if (inst->isSquashed()) { 1281 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1282 1283 // Consider this instruction executed so that commit can go 1284 // ahead and retire the instruction. 1285 inst->setExecuted(); 1286 1287 // Not sure if I should set this here or just let commit try to 1288 // commit any squashed instructions. I like the latter a bit more. 1289 inst->setCanCommit(); 1290 1291 ++iewExecSquashedInsts; 1292 1293 decrWb(inst->seqNum); 1294 continue; 1295 } 1296 1297 Fault fault = NoFault; 1298 1299 // Execute instruction. 1300 // Note that if the instruction faults, it will be handled 1301 // at the commit stage. 1302 if (inst->isMemRef() && 1303 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1304 DPRINTF(IEW, "Execute: Calculating address for memory " 1305 "reference.\n"); 1306 1307 // Tell the LDSTQ to execute this instruction (if it is a load). 1308 if (inst->isLoad()) { 1309 // Loads will mark themselves as executed, and their writeback 1310 // event adds the instruction to the queue to commit 1311 fault = ldstQueue.executeLoad(inst); 1312 } else if (inst->isStore()) { 1313 fault = ldstQueue.executeStore(inst); 1314 1315 // If the store had a fault then it may not have a mem req 1316 if (!inst->isStoreConditional() && fault == NoFault) { 1317 inst->setExecuted(); 1318 1319 instToCommit(inst); 1320 } else if (fault != NoFault) { 1321 // If the instruction faulted, then we need to send it along to commit 1322 // without the instruction completing. 1323 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 1324 fault->name(), inst->seqNum); 1325 1326 // Send this instruction to commit, also make sure iew stage 1327 // realizes there is activity. 1328 inst->setExecuted(); 1329 1330 instToCommit(inst); 1331 activityThisCycle(); 1332 } 1333 1334 // Store conditionals will mark themselves as 1335 // executed, and their writeback event will add the 1336 // instruction to the queue to commit. 1337 } else { 1338 panic("Unexpected memory type!\n"); 1339 } 1340 1341 } else { 1342 inst->execute(); 1343 1344 inst->setExecuted(); 1345 1346 instToCommit(inst); 1347 } 1348 1349 updateExeInstStats(inst); 1350 1351 // Check if branch prediction was correct, if not then we need 1352 // to tell commit to squash in flight instructions. Only 1353 // handle this if there hasn't already been something that 1354 // redirects fetch in this group of instructions. 1355 1356 // This probably needs to prioritize the redirects if a different 1357 // scheduler is used. Currently the scheduler schedules the oldest 1358 // instruction first, so the branch resolution order will be correct. 1359 unsigned tid = inst->threadNumber; 1360 1361 if (!fetchRedirect[tid] || 1362 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1363 1364 if (inst->mispredicted()) { 1365 fetchRedirect[tid] = true; 1366 1367 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1368 DPRINTF(IEW, "Predicted target was %#x, %#x.\n", 1369 inst->readPredPC(), inst->readPredNPC()); 1370 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1371 " NPC: %#x.\n", inst->readNextPC(), 1372 inst->readNextNPC()); 1373 // If incorrect, then signal the ROB that it must be squashed. 1374 squashDueToBranch(inst, tid); 1375 1376 if (inst->readPredTaken()) { 1377 predictedTakenIncorrect++; 1378 } else { 1379 predictedNotTakenIncorrect++; 1380 } 1381 } else if (ldstQueue.violation(tid)) { 1382 // If there was an ordering violation, then get the 1383 // DynInst that caused the violation. Note that this 1384 // clears the violation signal. 1385 DynInstPtr violator; 1386 violator = ldstQueue.getMemDepViolator(tid); 1387 1388 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1389 "%#x, inst PC: %#x. Addr is: %#x.\n", 1390 violator->readPC(), inst->readPC(), inst->physEffAddr); 1391 1392 // Ensure the violating instruction is older than 1393 // current squash 1394 if (fetchRedirect[tid] && 1395 violator->seqNum >= toCommit->squashedSeqNum[tid]) 1396 continue; 1397 1398 fetchRedirect[tid] = true; 1399 1400 // Tell the instruction queue that a violation has occured. 1401 instQueue.violation(inst, violator); 1402 1403 // Squash. 1404 squashDueToMemOrder(inst,tid); 1405 1406 ++memOrderViolationEvents; 1407 } else if (ldstQueue.loadBlocked(tid) && 1408 !ldstQueue.isLoadBlockedHandled(tid)) { 1409 fetchRedirect[tid] = true; 1410 1411 DPRINTF(IEW, "Load operation couldn't execute because the " 1412 "memory system is blocked. PC: %#x [sn:%lli]\n", 1413 inst->readPC(), inst->seqNum); 1414 1415 squashDueToMemBlocked(inst, tid); 1416 } 1417 } 1418 } 1419 1420 // Update and record activity if we processed any instructions. 1421 if (inst_num) { 1422 if (exeStatus == Idle) { 1423 exeStatus = Running; 1424 } 1425 1426 updatedQueues = true; 1427 1428 cpu->activityThisCycle(); 1429 } 1430 1431 // Need to reset this in case a writeback event needs to write into the 1432 // iew queue. That way the writeback event will write into the correct 1433 // spot in the queue. 1434 wbNumInst = 0; 1435} 1436 1437template <class Impl> 1438void 1439DefaultIEW<Impl>::writebackInsts() 1440{ 1441 // Loop through the head of the time buffer and wake any 1442 // dependents. These instructions are about to write back. Also 1443 // mark scoreboard that this instruction is finally complete. 1444 // Either have IEW have direct access to scoreboard, or have this 1445 // as part of backwards communication. 1446 for (int inst_num = 0; inst_num < wbWidth && 1447 toCommit->insts[inst_num]; inst_num++) { 1448 DynInstPtr inst = toCommit->insts[inst_num]; 1449 int tid = inst->threadNumber; 1450 1451 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1452 inst->seqNum, inst->readPC()); 1453 1454 iewInstsToCommit[tid]++; 1455 1456 // Some instructions will be sent to commit without having 1457 // executed because they need commit to handle them. 1458 // E.g. Uncached loads have not actually executed when they 1459 // are first sent to commit. Instead commit must tell the LSQ 1460 // when it's ready to execute the uncached load. 1461 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1462 int dependents = instQueue.wakeDependents(inst); 1463 1464 for (int i = 0; i < inst->numDestRegs(); i++) { 1465 //mark as Ready 1466 DPRINTF(IEW,"Setting Destination Register %i\n", 1467 inst->renamedDestRegIdx(i)); 1468 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1469 } 1470 1471 if (dependents) { 1472 producerInst[tid]++; 1473 consumerInst[tid]+= dependents; 1474 } 1475 writebackCount[tid]++; 1476 } 1477 1478 decrWb(inst->seqNum); 1479 } 1480} 1481 1482template<class Impl> 1483void 1484DefaultIEW<Impl>::tick() 1485{ 1486 wbNumInst = 0; 1487 wbCycle = 0; 1488 1489 wroteToTimeBuffer = false; 1490 updatedQueues = false; 1491 1492 sortInsts(); 1493 1494 // Free function units marked as being freed this cycle. 1495 fuPool->processFreeUnits(); 1496
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1494 std::list<unsigned>::iterator threads = (*activeThreads).begin();
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1497 std::list<unsigned>::iterator threads = activeThreads->begin(); 1498 std::list<unsigned>::iterator end = activeThreads->end(); |
1499 1500 // Check stall and squash signals, dispatch any instructions.
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1497 while (threads != (*activeThreads).end()) {
1498 unsigned tid = *threads++;
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1501 while (threads != end) { 1502 unsigned tid = *threads++; |
1503 1504 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1505 1506 checkSignalsAndUpdate(tid); 1507 dispatch(tid); 1508 } 1509 1510 if (exeStatus != Squashing) { 1511 executeInsts(); 1512 1513 writebackInsts(); 1514 1515 // Have the instruction queue try to schedule any ready instructions. 1516 // (In actuality, this scheduling is for instructions that will 1517 // be executed next cycle.) 1518 instQueue.scheduleReadyInsts(); 1519 1520 // Also should advance its own time buffers if the stage ran. 1521 // Not the best place for it, but this works (hopefully). 1522 issueToExecQueue.advance(); 1523 } 1524 1525 bool broadcast_free_entries = false; 1526 1527 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1528 exeStatus = Idle; 1529 updateLSQNextCycle = false; 1530 1531 broadcast_free_entries = true; 1532 } 1533 1534 // Writeback any stores using any leftover bandwidth. 1535 ldstQueue.writebackStores(); 1536 1537 // Check the committed load/store signals to see if there's a load 1538 // or store to commit. Also check if it's being told to execute a 1539 // nonspeculative instruction. 1540 // This is pretty inefficient... 1541
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1538 threads = (*activeThreads).begin();
1539 while (threads != (*activeThreads).end()) {
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1542 threads = activeThreads->begin(); 1543 while (threads != end) { |
1544 unsigned tid = (*threads++); 1545 1546 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1547 1548 // Update structures based on instructions committed. 1549 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1550 !fromCommit->commitInfo[tid].squash && 1551 !fromCommit->commitInfo[tid].robSquashing) { 1552 1553 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1554 1555 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1556 1557 updateLSQNextCycle = true; 1558 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1559 } 1560 1561 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1562 1563 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1564 if (fromCommit->commitInfo[tid].uncached) { 1565 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1566 } else { 1567 instQueue.scheduleNonSpec( 1568 fromCommit->commitInfo[tid].nonSpecSeqNum); 1569 } 1570 } 1571 1572 if (broadcast_free_entries) { 1573 toFetch->iewInfo[tid].iqCount = 1574 instQueue.getCount(tid); 1575 toFetch->iewInfo[tid].ldstqCount = 1576 ldstQueue.getCount(tid); 1577 1578 toRename->iewInfo[tid].usedIQ = true; 1579 toRename->iewInfo[tid].freeIQEntries = 1580 instQueue.numFreeEntries(); 1581 toRename->iewInfo[tid].usedLSQ = true; 1582 toRename->iewInfo[tid].freeLSQEntries = 1583 ldstQueue.numFreeEntries(tid); 1584 1585 wroteToTimeBuffer = true; 1586 } 1587 1588 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1589 tid, toRename->iewInfo[tid].dispatched); 1590 } 1591 1592 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1593 "LSQ has %i free entries.\n", 1594 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1595 ldstQueue.numFreeEntries()); 1596 1597 updateStatus(); 1598 1599 if (wroteToTimeBuffer) { 1600 DPRINTF(Activity, "Activity this cycle.\n"); 1601 cpu->activityThisCycle(); 1602 } 1603} 1604 1605template <class Impl> 1606void 1607DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1608{ 1609 int thread_number = inst->threadNumber; 1610 1611 // 1612 // Pick off the software prefetches 1613 // 1614#ifdef TARGET_ALPHA 1615 if (inst->isDataPrefetch()) 1616 iewExecutedSwp[thread_number]++; 1617 else 1618 iewIewExecutedcutedInsts++; 1619#else 1620 iewExecutedInsts++; 1621#endif 1622 1623 // 1624 // Control operations 1625 // 1626 if (inst->isControl()) 1627 iewExecutedBranches[thread_number]++; 1628 1629 // 1630 // Memory operations 1631 // 1632 if (inst->isMemRef()) { 1633 iewExecutedRefs[thread_number]++; 1634 1635 if (inst->isLoad()) { 1636 iewExecLoadInsts[thread_number]++; 1637 } 1638 } 1639}
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