1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 issueReadWidth(params->issueWidth),
54 issueWidth(params->issueWidth),
55 numThreads(params->numberOfThreads),
56 switchedOut(false)
57{
58 _status = Active;
59 exeStatus = Running;
60 wbStatus = Idle;
61
62 // Setup wire to read instructions coming from issue.
63 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
64
65 // Instruction queue needs the queue between issue and execute.
66 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
67
68 instQueue.setIEW(this);
69 ldstQueue.setIEW(this);
70
71 for (int i=0; i < numThreads; i++) {
72 dispatchStatus[i] = Running;
73 stalls[i].commit = false;
74 fetchRedirect[i] = false;
75 }
76
77 updateLSQNextCycle = false;
78
79 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
80}
81
82template <class Impl>
83std::string
84DefaultIEW<Impl>::name() const
85{
86 return cpu->name() + ".iew";
87}
88
89template <class Impl>
90void
91DefaultIEW<Impl>::regStats()
92{
93 using namespace Stats;
94
95 instQueue.regStats();
96 ldstQueue.regStats();
97
98 iewIdleCycles
99 .name(name() + ".iewIdleCycles")
100 .desc("Number of cycles IEW is idle");
101
102 iewSquashCycles
103 .name(name() + ".iewSquashCycles")
104 .desc("Number of cycles IEW is squashing");
105
106 iewBlockCycles
107 .name(name() + ".iewBlockCycles")
108 .desc("Number of cycles IEW is blocking");
109
110 iewUnblockCycles
111 .name(name() + ".iewUnblockCycles")
112 .desc("Number of cycles IEW is unblocking");
113
114 iewDispatchedInsts
115 .name(name() + ".iewDispatchedInsts")
116 .desc("Number of instructions dispatched to IQ");
117
118 iewDispSquashedInsts
119 .name(name() + ".iewDispSquashedInsts")
120 .desc("Number of squashed instructions skipped by dispatch");
121
122 iewDispLoadInsts
123 .name(name() + ".iewDispLoadInsts")
124 .desc("Number of dispatched load instructions");
125
126 iewDispStoreInsts
127 .name(name() + ".iewDispStoreInsts")
128 .desc("Number of dispatched store instructions");
129
130 iewDispNonSpecInsts
131 .name(name() + ".iewDispNonSpecInsts")
132 .desc("Number of dispatched non-speculative instructions");
133
134 iewIQFullEvents
135 .name(name() + ".iewIQFullEvents")
136 .desc("Number of times the IQ has become full, causing a stall");
137
138 iewLSQFullEvents
139 .name(name() + ".iewLSQFullEvents")
140 .desc("Number of times the LSQ has become full, causing a stall");
141
141 iewExecutedInsts
142 .name(name() + ".iewExecutedInsts")
143 .desc("Number of executed instructions");
144
145 iewExecLoadInsts
146 .init(cpu->number_of_threads)
147 .name(name() + ".iewExecLoadInsts")
148 .desc("Number of load instructions executed")
149 .flags(total);
150
151 iewExecSquashedInsts
152 .name(name() + ".iewExecSquashedInsts")
153 .desc("Number of squashed instructions skipped in execute");
154
142 memOrderViolationEvents
143 .name(name() + ".memOrderViolationEvents")
144 .desc("Number of memory order violations");
145
146 predictedTakenIncorrect
147 .name(name() + ".predictedTakenIncorrect")
148 .desc("Number of branches that were predicted taken incorrectly");
149
150 predictedNotTakenIncorrect
151 .name(name() + ".predictedNotTakenIncorrect")
152 .desc("Number of branches that were predicted not taken incorrectly");
153
154 branchMispredicts
155 .name(name() + ".branchMispredicts")
156 .desc("Number of branch mispredicts detected at execute");
157
158 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
159
173 exeSwp
160 iewExecutedInsts
161 .name(name() + ".EXEC:insts")
162 .desc("Number of executed instructions");
163
164 iewExecLoadInsts
165 .init(cpu->number_of_threads)
166 .name(name() + ".EXEC:loads")
167 .desc("Number of load instructions executed")
168 .flags(total);
169
170 iewExecSquashedInsts
171 .name(name() + ".EXEC:squashedInsts")
172 .desc("Number of squashed instructions skipped in execute");
173
174 iewExecutedSwp
175 .init(cpu->number_of_threads)
176 .name(name() + ".EXEC:swp")
177 .desc("number of swp insts executed")
177 .flags(total)
178 ;
178 .flags(total);
179
180 exeNop
180 iewExecutedNop
181 .init(cpu->number_of_threads)
182 .name(name() + ".EXEC:nop")
183 .desc("number of nop insts executed")
184 .flags(total)
185 ;
184 .flags(total);
185
187 exeRefs
186 iewExecutedRefs
187 .init(cpu->number_of_threads)
188 .name(name() + ".EXEC:refs")
189 .desc("number of memory reference insts executed")
191 .flags(total)
192 ;
190 .flags(total);
191
194 exeBranches
192 iewExecutedBranches
193 .init(cpu->number_of_threads)
194 .name(name() + ".EXEC:branches")
195 .desc("Number of branches executed")
198 .flags(total)
199 ;
196 .flags(total);
197
201 issueRate
202 .name(name() + ".EXEC:rate")
203 .desc("Inst execution rate")
204 .flags(total)
205 ;
206 issueRate = iewExecutedInsts / cpu->numCycles;
207
198 iewExecStoreInsts
199 .name(name() + ".EXEC:stores")
200 .desc("Number of stores executed")
211 .flags(total)
212 ;
213 iewExecStoreInsts = exeRefs - iewExecLoadInsts;
214/*
215 for (int i=0; i<Num_OpClasses; ++i) {
216 stringstream subname;
217 subname << opClassStrings[i] << "_delay";
218 issue_delay_dist.subname(i, subname.str());
219 }
220*/
221 //
222 // Other stats
223 //
201 .flags(total);
202 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
203
204 iewExecRate
205 .name(name() + ".EXEC:rate")
206 .desc("Inst execution rate")
207 .flags(total);
208
209 iewExecRate = iewExecutedInsts / cpu->numCycles;
210
211 iewInstsToCommit
212 .init(cpu->number_of_threads)
213 .name(name() + ".WB:sent")
214 .desc("cumulative count of insts sent to commit")
229 .flags(total)
230 ;
215 .flags(total);
216
217 writebackCount
218 .init(cpu->number_of_threads)
219 .name(name() + ".WB:count")
220 .desc("cumulative count of insts written-back")
236 .flags(total)
237 ;
221 .flags(total);
222
223 producerInst
224 .init(cpu->number_of_threads)
225 .name(name() + ".WB:producers")
226 .desc("num instructions producing a value")
243 .flags(total)
244 ;
227 .flags(total);
228
229 consumerInst
230 .init(cpu->number_of_threads)
231 .name(name() + ".WB:consumers")
232 .desc("num instructions consuming a value")
250 .flags(total)
251 ;
233 .flags(total);
234
235 wbPenalized
236 .init(cpu->number_of_threads)
237 .name(name() + ".WB:penalized")
238 .desc("number of instrctions required to write to 'other' IQ")
257 .flags(total)
258 ;
239 .flags(total);
240
241 wbPenalizedRate
242 .name(name() + ".WB:penalized_rate")
243 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
263 .flags(total)
264 ;
244 .flags(total);
245
246 wbPenalizedRate = wbPenalized / writebackCount;
247
248 wbFanout
249 .name(name() + ".WB:fanout")
250 .desc("average fanout of values written-back")
271 .flags(total)
272 ;
251 .flags(total);
252
253 wbFanout = producerInst / consumerInst;
254
255 wbRate
256 .name(name() + ".WB:rate")
257 .desc("insts written-back per cycle")
279 .flags(total)
280 ;
258 .flags(total);
259 wbRate = writebackCount / cpu->numCycles;
260}
261
262template<class Impl>
263void
264DefaultIEW<Impl>::initStage()
265{
266 for (int tid=0; tid < numThreads; tid++) {
267 toRename->iewInfo[tid].usedIQ = true;
268 toRename->iewInfo[tid].freeIQEntries =
269 instQueue.numFreeEntries(tid);
270
271 toRename->iewInfo[tid].usedLSQ = true;
272 toRename->iewInfo[tid].freeLSQEntries =
273 ldstQueue.numFreeEntries(tid);
274 }
275}
276
277template<class Impl>
278void
279DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
280{
281 DPRINTF(IEW, "Setting CPU pointer.\n");
282 cpu = cpu_ptr;
283
284 instQueue.setCPU(cpu_ptr);
285 ldstQueue.setCPU(cpu_ptr);
286
287 cpu->activateStage(FullCPU::IEWIdx);
288}
289
290template<class Impl>
291void
292DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
293{
294 DPRINTF(IEW, "Setting time buffer pointer.\n");
295 timeBuffer = tb_ptr;
296
297 // Setup wire to read information from time buffer, from commit.
298 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
299
300 // Setup wire to write information back to previous stages.
301 toRename = timeBuffer->getWire(0);
302
303 toFetch = timeBuffer->getWire(0);
304
305 // Instruction queue also needs main time buffer.
306 instQueue.setTimeBuffer(tb_ptr);
307}
308
309template<class Impl>
310void
311DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
312{
313 DPRINTF(IEW, "Setting rename queue pointer.\n");
314 renameQueue = rq_ptr;
315
316 // Setup wire to read information from rename queue.
317 fromRename = renameQueue->getWire(-renameToIEWDelay);
318}
319
320template<class Impl>
321void
322DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
323{
324 DPRINTF(IEW, "Setting IEW queue pointer.\n");
325 iewQueue = iq_ptr;
326
327 // Setup wire to write instructions to commit.
328 toCommit = iewQueue->getWire(0);
329}
330
331template<class Impl>
332void
333DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
334{
335 DPRINTF(IEW, "Setting active threads list pointer.\n");
336 activeThreads = at_ptr;
337
338 ldstQueue.setActiveThreads(at_ptr);
339 instQueue.setActiveThreads(at_ptr);
340}
341
342template<class Impl>
343void
344DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
345{
346 DPRINTF(IEW, "Setting scoreboard pointer.\n");
347 scoreboard = sb_ptr;
348}
349
350template <class Impl>
351void
352DefaultIEW<Impl>::switchOut()
353{
354 // IEW is ready to switch out at any time.
355 cpu->signalSwitched();
356}
357
358template <class Impl>
359void
360DefaultIEW<Impl>::doSwitchOut()
361{
362 // Clear any state.
363 switchedOut = true;
364
365 instQueue.switchOut();
366 ldstQueue.switchOut();
367 fuPool->switchOut();
368
369 for (int i = 0; i < numThreads; i++) {
370 while (!insts[i].empty())
371 insts[i].pop();
372 while (!skidBuffer[i].empty())
373 skidBuffer[i].pop();
374 }
375}
376
377template <class Impl>
378void
379DefaultIEW<Impl>::takeOverFrom()
380{
381 // Reset all state.
382 _status = Active;
383 exeStatus = Running;
384 wbStatus = Idle;
385 switchedOut = false;
386
387 instQueue.takeOverFrom();
388 ldstQueue.takeOverFrom();
389 fuPool->takeOverFrom();
390
391 initStage();
392 cpu->activityThisCycle();
393
394 for (int i=0; i < numThreads; i++) {
395 dispatchStatus[i] = Running;
396 stalls[i].commit = false;
397 fetchRedirect[i] = false;
398 }
399
400 updateLSQNextCycle = false;
401
402 // @todo: Fix hardcoded number
403 for (int i = 0; i < 6; ++i) {
404 issueToExecQueue.advance();
405 }
406}
407
408template<class Impl>
409void
410DefaultIEW<Impl>::squash(unsigned tid)
411{
412 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
413 tid);
414
415 // Tell the IQ to start squashing.
416 instQueue.squash(tid);
417
418 // Tell the LDSTQ to start squashing.
419 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
420
421 updatedQueues = true;
422
423 // Clear the skid buffer in case it has any data in it.
424 while (!skidBuffer[tid].empty()) {
425
426 if (skidBuffer[tid].front()->isLoad() ||
427 skidBuffer[tid].front()->isStore() ) {
428 toRename->iewInfo[tid].dispatchedToLSQ++;
429 }
430
431 toRename->iewInfo[tid].dispatched++;
432
433 skidBuffer[tid].pop();
434 }
435
436 emptyRenameInsts(tid);
437}
438
439template<class Impl>
440void
441DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
442{
443 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
444 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
445
446 toCommit->squash[tid] = true;
447 toCommit->squashedSeqNum[tid] = inst->seqNum;
448 toCommit->mispredPC[tid] = inst->readPC();
449 toCommit->nextPC[tid] = inst->readNextPC();
450 toCommit->branchMispredict[tid] = true;
451 toCommit->branchTaken[tid] = inst->readNextPC() !=
452 (inst->readPC() + sizeof(TheISA::MachInst));
453
454 toCommit->includeSquashInst[tid] = false;
455
456 wroteToTimeBuffer = true;
457}
458
459template<class Impl>
460void
461DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
462{
463 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
464 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
465
466 toCommit->squash[tid] = true;
467 toCommit->squashedSeqNum[tid] = inst->seqNum;
468 toCommit->nextPC[tid] = inst->readNextPC();
469
470 toCommit->includeSquashInst[tid] = false;
471
472 wroteToTimeBuffer = true;
473}
474
475template<class Impl>
476void
477DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
478{
479 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
480 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
481
482 toCommit->squash[tid] = true;
483 toCommit->squashedSeqNum[tid] = inst->seqNum;
484 toCommit->nextPC[tid] = inst->readPC();
485
486 // Must include the broadcasted SN in the squash.
487 toCommit->includeSquashInst[tid] = true;
488
489 ldstQueue.setLoadBlockedHandled(tid);
490
491 wroteToTimeBuffer = true;
492}
493
494template<class Impl>
495void
496DefaultIEW<Impl>::block(unsigned tid)
497{
498 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
499
500 if (dispatchStatus[tid] != Blocked &&
501 dispatchStatus[tid] != Unblocking) {
502 toRename->iewBlock[tid] = true;
503 wroteToTimeBuffer = true;
504 }
505
506 // Add the current inputs to the skid buffer so they can be
507 // reprocessed when this stage unblocks.
508 skidInsert(tid);
509
510 dispatchStatus[tid] = Blocked;
511}
512
513template<class Impl>
514void
515DefaultIEW<Impl>::unblock(unsigned tid)
516{
517 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
518 "buffer %u.\n",tid, tid);
519
520 // If the skid bufffer is empty, signal back to previous stages to unblock.
521 // Also switch status to running.
522 if (skidBuffer[tid].empty()) {
523 toRename->iewUnblock[tid] = true;
524 wroteToTimeBuffer = true;
525 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
526 dispatchStatus[tid] = Running;
527 }
528}
529
530template<class Impl>
531void
532DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
533{
534 instQueue.wakeDependents(inst);
535}
536
537template<class Impl>
538void
539DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
540{
541 instQueue.rescheduleMemInst(inst);
542}
543
544template<class Impl>
545void
546DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
547{
548 instQueue.replayMemInst(inst);
549}
550
551template<class Impl>
552void
553DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
554{
555 // First check the time slot that this instruction will write
556 // to. If there are free write ports at the time, then go ahead
557 // and write the instruction to that time. If there are not,
558 // keep looking back to see where's the first time there's a
559 // free slot.
560 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
561 ++wbNumInst;
562 if (wbNumInst == issueWidth) {
563 ++wbCycle;
564 wbNumInst = 0;
565 }
566
567 assert(wbCycle < 5);
568 }
569
570 // Add finished instruction to queue to commit.
571 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
572 (*iewQueue)[wbCycle].size++;
573}
574
575template <class Impl>
576unsigned
577DefaultIEW<Impl>::validInstsFromRename()
578{
579 unsigned inst_count = 0;
580
581 for (int i=0; i<fromRename->size; i++) {
582 if (!fromRename->insts[i]->squashed)
583 inst_count++;
584 }
585
586 return inst_count;
587}
588
589template<class Impl>
590void
591DefaultIEW<Impl>::skidInsert(unsigned tid)
592{
593 DynInstPtr inst = NULL;
594
595 while (!insts[tid].empty()) {
596 inst = insts[tid].front();
597
598 insts[tid].pop();
599
600 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
601 "dispatch skidBuffer %i\n",tid, inst->seqNum,
602 inst->readPC(),tid);
603
604 skidBuffer[tid].push(inst);
605 }
606
607 assert(skidBuffer[tid].size() <= skidBufferMax &&
608 "Skidbuffer Exceeded Max Size");
609}
610
611template<class Impl>
612int
613DefaultIEW<Impl>::skidCount()
614{
615 int max=0;
616
617 list<unsigned>::iterator threads = (*activeThreads).begin();
618
619 while (threads != (*activeThreads).end()) {
620 unsigned thread_count = skidBuffer[*threads++].size();
621 if (max < thread_count)
622 max = thread_count;
623 }
624
625 return max;
626}
627
628template<class Impl>
629bool
630DefaultIEW<Impl>::skidsEmpty()
631{
632 list<unsigned>::iterator threads = (*activeThreads).begin();
633
634 while (threads != (*activeThreads).end()) {
635 if (!skidBuffer[*threads++].empty())
636 return false;
637 }
638
639 return true;
640}
641
642template <class Impl>
643void
644DefaultIEW<Impl>::updateStatus()
645{
646 bool any_unblocking = false;
647
648 list<unsigned>::iterator threads = (*activeThreads).begin();
649
650 threads = (*activeThreads).begin();
651
652 while (threads != (*activeThreads).end()) {
653 unsigned tid = *threads++;
654
655 if (dispatchStatus[tid] == Unblocking) {
656 any_unblocking = true;
657 break;
658 }
659 }
660
661 // If there are no ready instructions waiting to be scheduled by the IQ,
662 // and there's no stores waiting to write back, and dispatch is not
663 // unblocking, then there is no internal activity for the IEW stage.
664 if (_status == Active && !instQueue.hasReadyInsts() &&
665 !ldstQueue.willWB() && !any_unblocking) {
666 DPRINTF(IEW, "IEW switching to idle\n");
667
668 deactivateStage();
669
670 _status = Inactive;
671 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
672 ldstQueue.willWB() ||
673 any_unblocking)) {
674 // Otherwise there is internal activity. Set to active.
675 DPRINTF(IEW, "IEW switching to active\n");
676
677 activateStage();
678
679 _status = Active;
680 }
681}
682
683template <class Impl>
684void
685DefaultIEW<Impl>::resetEntries()
686{
687 instQueue.resetEntries();
688 ldstQueue.resetEntries();
689}
690
691template <class Impl>
692void
693DefaultIEW<Impl>::readStallSignals(unsigned tid)
694{
695 if (fromCommit->commitBlock[tid]) {
696 stalls[tid].commit = true;
697 }
698
699 if (fromCommit->commitUnblock[tid]) {
700 assert(stalls[tid].commit);
701 stalls[tid].commit = false;
702 }
703}
704
705template <class Impl>
706bool
707DefaultIEW<Impl>::checkStall(unsigned tid)
708{
709 bool ret_val(false);
710
711 if (stalls[tid].commit) {
712 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
713 ret_val = true;
714 } else if (instQueue.isFull(tid)) {
715 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
716 ret_val = true;
717 } else if (ldstQueue.isFull(tid)) {
718 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
719
720 if (ldstQueue.numLoads(tid) > 0 ) {
721
722 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
723 tid,ldstQueue.getLoadHeadSeqNum(tid));
724 }
725
726 if (ldstQueue.numStores(tid) > 0) {
727
728 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
729 tid,ldstQueue.getStoreHeadSeqNum(tid));
730 }
731
732 ret_val = true;
733 } else if (ldstQueue.isStalled(tid)) {
734 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
735 ret_val = true;
736 }
737
738 return ret_val;
739}
740
741template <class Impl>
742void
743DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
744{
745 // Check if there's a squash signal, squash if there is
746 // Check stall signals, block if there is.
747 // If status was Blocked
748 // if so then go to unblocking
749 // If status was Squashing
750 // check if squashing is not high. Switch to running this cycle.
751
752 readStallSignals(tid);
753
754 if (fromCommit->commitInfo[tid].squash) {
755 squash(tid);
756
757 if (dispatchStatus[tid] == Blocked ||
758 dispatchStatus[tid] == Unblocking) {
759 toRename->iewUnblock[tid] = true;
760 wroteToTimeBuffer = true;
761 }
762
763 dispatchStatus[tid] = Squashing;
764
765 fetchRedirect[tid] = false;
766 return;
767 }
768
769 if (fromCommit->commitInfo[tid].robSquashing) {
770 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
771
772 dispatchStatus[tid] = Squashing;
773
774 emptyRenameInsts(tid);
775 wroteToTimeBuffer = true;
776 return;
777 }
778
779 if (checkStall(tid)) {
780 block(tid);
781 dispatchStatus[tid] = Blocked;
782 return;
783 }
784
785 if (dispatchStatus[tid] == Blocked) {
786 // Status from previous cycle was blocked, but there are no more stall
787 // conditions. Switch over to unblocking.
788 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
789 tid);
790
791 dispatchStatus[tid] = Unblocking;
792
793 unblock(tid);
794
795 return;
796 }
797
798 if (dispatchStatus[tid] == Squashing) {
799 // Switch status to running if rename isn't being told to block or
800 // squash this cycle.
801 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
802 tid);
803
804 dispatchStatus[tid] = Running;
805
806 return;
807 }
808}
809
810template <class Impl>
811void
812DefaultIEW<Impl>::sortInsts()
813{
814 int insts_from_rename = fromRename->size;
815#ifdef DEBUG
816 for (int i = 0; i < numThreads; i++)
817 assert(insts[i].empty());
818#endif
819 for (int i = 0; i < insts_from_rename; ++i) {
820 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
821 }
822}
823
824template <class Impl>
825void
826DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
827{
828 while (!insts[tid].empty()) {
829 if (insts[tid].front()->isLoad() ||
830 insts[tid].front()->isStore() ) {
831 toRename->iewInfo[tid].dispatchedToLSQ++;
832 }
833
834 toRename->iewInfo[tid].dispatched++;
835
836 insts[tid].pop();
837 }
838}
839
840template <class Impl>
841void
842DefaultIEW<Impl>::wakeCPU()
843{
844 cpu->wakeCPU();
845}
846
847template <class Impl>
848void
849DefaultIEW<Impl>::activityThisCycle()
850{
851 DPRINTF(Activity, "Activity this cycle.\n");
852 cpu->activityThisCycle();
853}
854
855template <class Impl>
856inline void
857DefaultIEW<Impl>::activateStage()
858{
859 DPRINTF(Activity, "Activating stage.\n");
860 cpu->activateStage(FullCPU::IEWIdx);
861}
862
863template <class Impl>
864inline void
865DefaultIEW<Impl>::deactivateStage()
866{
867 DPRINTF(Activity, "Deactivating stage.\n");
868 cpu->deactivateStage(FullCPU::IEWIdx);
869}
870
871template<class Impl>
872void
873DefaultIEW<Impl>::dispatch(unsigned tid)
874{
875 // If status is Running or idle,
876 // call dispatchInsts()
877 // If status is Unblocking,
878 // buffer any instructions coming from rename
879 // continue trying to empty skid buffer
880 // check if stall conditions have passed
881
882 if (dispatchStatus[tid] == Blocked) {
883 ++iewBlockCycles;
884
885 } else if (dispatchStatus[tid] == Squashing) {
886 ++iewSquashCycles;
887 }
888
889 // Dispatch should try to dispatch as many instructions as its bandwidth
890 // will allow, as long as it is not currently blocked.
891 if (dispatchStatus[tid] == Running ||
892 dispatchStatus[tid] == Idle) {
893 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
894 "dispatch.\n", tid);
895
896 dispatchInsts(tid);
897 } else if (dispatchStatus[tid] == Unblocking) {
898 // Make sure that the skid buffer has something in it if the
899 // status is unblocking.
900 assert(!skidsEmpty());
901
902 // If the status was unblocking, then instructions from the skid
903 // buffer were used. Remove those instructions and handle
904 // the rest of unblocking.
905 dispatchInsts(tid);
906
907 ++iewUnblockCycles;
908
909 if (validInstsFromRename() && dispatchedAllInsts) {
910 // Add the current inputs to the skid buffer so they can be
911 // reprocessed when this stage unblocks.
912 skidInsert(tid);
913 }
914
915 unblock(tid);
916 }
917}
918
919template <class Impl>
920void
921DefaultIEW<Impl>::dispatchInsts(unsigned tid)
922{
923 dispatchedAllInsts = true;
924
925 // Obtain instructions from skid buffer if unblocking, or queue from rename
926 // otherwise.
927 std::queue<DynInstPtr> &insts_to_dispatch =
928 dispatchStatus[tid] == Unblocking ?
929 skidBuffer[tid] : insts[tid];
930
931 int insts_to_add = insts_to_dispatch.size();
932
933 DynInstPtr inst;
934 bool add_to_iq = false;
935 int dis_num_inst = 0;
936
937 // Loop through the instructions, putting them in the instruction
938 // queue.
939 for ( ; dis_num_inst < insts_to_add &&
940 dis_num_inst < issueReadWidth;
941 ++dis_num_inst)
942 {
943 inst = insts_to_dispatch.front();
944
945 if (dispatchStatus[tid] == Unblocking) {
946 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
947 "buffer\n", tid);
948 }
949
950 // Make sure there's a valid instruction there.
951 assert(inst);
952
953 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
954 "IQ.\n",
955 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
956
957 // Be sure to mark these instructions as ready so that the
958 // commit stage can go ahead and execute them, and mark
959 // them as issued so the IQ doesn't reprocess them.
960
961 // Check for squashed instructions.
962 if (inst->isSquashed()) {
963 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
964 "not adding to IQ.\n", tid);
965
966 ++iewDispSquashedInsts;
967
968 insts_to_dispatch.pop();
969
970 //Tell Rename That An Instruction has been processed
971 if (inst->isLoad() || inst->isStore()) {
972 toRename->iewInfo[tid].dispatchedToLSQ++;
973 }
974 toRename->iewInfo[tid].dispatched++;
975
976 continue;
977 }
978
979 // Check for full conditions.
980 if (instQueue.isFull(tid)) {
981 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
982
983 // Call function to start blocking.
984 block(tid);
985
986 // Set unblock to false. Special case where we are using
987 // skidbuffer (unblocking) instructions but then we still
988 // get full in the IQ.
989 toRename->iewUnblock[tid] = false;
990
991 dispatchedAllInsts = false;
992
993 ++iewIQFullEvents;
994 break;
995 } else if (ldstQueue.isFull(tid)) {
996 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
997
998 // Call function to start blocking.
999 block(tid);
1000
1001 // Set unblock to false. Special case where we are using
1002 // skidbuffer (unblocking) instructions but then we still
1003 // get full in the IQ.
1004 toRename->iewUnblock[tid] = false;
1005
1006 dispatchedAllInsts = false;
1007
1008 ++iewLSQFullEvents;
1009 break;
1010 }
1011
1012 // Otherwise issue the instruction just fine.
1013 if (inst->isLoad()) {
1014 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1015 "encountered, adding to LSQ.\n", tid);
1016
1017 // Reserve a spot in the load store queue for this
1018 // memory access.
1019 ldstQueue.insertLoad(inst);
1020
1021 ++iewDispLoadInsts;
1022
1023 add_to_iq = true;
1024
1025 toRename->iewInfo[tid].dispatchedToLSQ++;
1026 } else if (inst->isStore()) {
1027 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1028 "encountered, adding to LSQ.\n", tid);
1029
1030 ldstQueue.insertStore(inst);
1031
1032 ++iewDispStoreInsts;
1033
1034 if (inst->isStoreConditional()) {
1035 // Store conditionals need to be set as "canCommit()"
1036 // so that commit can process them when they reach the
1037 // head of commit.
1038 // @todo: This is somewhat specific to Alpha.
1039 inst->setCanCommit();
1040 instQueue.insertNonSpec(inst);
1041 add_to_iq = false;
1042
1043 ++iewDispNonSpecInsts;
1044 } else {
1045 add_to_iq = true;
1046 }
1047
1048 toRename->iewInfo[tid].dispatchedToLSQ++;
1049#if FULL_SYSTEM
1050 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1051 // Same as non-speculative stores.
1052 inst->setCanCommit();
1053 instQueue.insertBarrier(inst);
1054 add_to_iq = false;
1055#endif
1056 } else if (inst->isNonSpeculative()) {
1057 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1058 "encountered, skipping.\n", tid);
1059
1060 // Same as non-speculative stores.
1061 inst->setCanCommit();
1062
1063 // Specifically insert it as nonspeculative.
1064 instQueue.insertNonSpec(inst);
1065
1066 ++iewDispNonSpecInsts;
1067
1068 add_to_iq = false;
1069 } else if (inst->isNop()) {
1070 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1071 "skipping.\n", tid);
1072
1073 inst->setIssued();
1074 inst->setExecuted();
1075 inst->setCanCommit();
1076
1077 instQueue.recordProducer(inst);
1078
1101 exeNop[tid]++;
1079 iewExecutedNop[tid]++;
1080
1081 add_to_iq = false;
1082 } else if (inst->isExecuted()) {
1083 assert(0 && "Instruction shouldn't be executed.\n");
1084 DPRINTF(IEW, "Issue: Executed branch encountered, "
1085 "skipping.\n");
1086
1087 inst->setIssued();
1088 inst->setCanCommit();
1089
1090 instQueue.recordProducer(inst);
1091
1092 add_to_iq = false;
1093 } else {
1094 add_to_iq = true;
1095 }
1096
1097 // If the instruction queue is not full, then add the
1098 // instruction.
1099 if (add_to_iq) {
1100 instQueue.insert(inst);
1101 }
1102
1103 insts_to_dispatch.pop();
1104
1105 toRename->iewInfo[tid].dispatched++;
1106
1107 ++iewDispatchedInsts;
1108 }
1109
1110 if (!insts_to_dispatch.empty()) {
1111 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1112 block(tid);
1113 toRename->iewUnblock[tid] = false;
1114 }
1115
1116 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1117 dispatchStatus[tid] = Running;
1118
1119 updatedQueues = true;
1120 }
1121
1122 dis_num_inst = 0;
1123}
1124
1125template <class Impl>
1126void
1127DefaultIEW<Impl>::printAvailableInsts()
1128{
1129 int inst = 0;
1130
1131 cout << "Available Instructions: ";
1132
1133 while (fromIssue->insts[inst]) {
1134
1135 if (inst%3==0) cout << "\n\t";
1136
1137 cout << "PC: " << fromIssue->insts[inst]->readPC()
1138 << " TN: " << fromIssue->insts[inst]->threadNumber
1139 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1140
1141 inst++;
1142
1143 }
1144
1145 cout << "\n";
1146}
1147
1148template <class Impl>
1149void
1150DefaultIEW<Impl>::executeInsts()
1151{
1152 wbNumInst = 0;
1153 wbCycle = 0;
1154
1155 list<unsigned>::iterator threads = (*activeThreads).begin();
1156
1157 while (threads != (*activeThreads).end()) {
1158 unsigned tid = *threads++;
1159 fetchRedirect[tid] = false;
1160 }
1161
1162 // Uncomment this if you want to see all available instructions.
1163// printAvailableInsts();
1164
1165 // Execute/writeback any instructions that are available.
1166 int insts_to_execute = fromIssue->size;
1167 int inst_num = 0;
1168 for (; inst_num < insts_to_execute;
1169 ++inst_num) {
1170
1171 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1172
1173 DynInstPtr inst = instQueue.getInstToExecute();
1174
1175 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1176 inst->readPC(), inst->threadNumber,inst->seqNum);
1177
1178 // Check if the instruction is squashed; if so then skip it
1179 if (inst->isSquashed()) {
1180 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1181
1182 // Consider this instruction executed so that commit can go
1183 // ahead and retire the instruction.
1184 inst->setExecuted();
1185
1186 // Not sure if I should set this here or just let commit try to
1187 // commit any squashed instructions. I like the latter a bit more.
1188 inst->setCanCommit();
1189
1190 ++iewExecSquashedInsts;
1191
1192 continue;
1193 }
1194
1195 Fault fault = NoFault;
1196
1197 // Execute instruction.
1198 // Note that if the instruction faults, it will be handled
1199 // at the commit stage.
1200 if (inst->isMemRef() &&
1201 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1202 DPRINTF(IEW, "Execute: Calculating address for memory "
1203 "reference.\n");
1204
1205 // Tell the LDSTQ to execute this instruction (if it is a load).
1206 if (inst->isLoad()) {
1207 // Loads will mark themselves as executed, and their writeback
1208 // event adds the instruction to the queue to commit
1209 fault = ldstQueue.executeLoad(inst);
1210 } else if (inst->isStore()) {
1211 ldstQueue.executeStore(inst);
1212
1213 // If the store had a fault then it may not have a mem req
1214 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1215 inst->setExecuted();
1216
1217 instToCommit(inst);
1218 }
1219
1220 // Store conditionals will mark themselves as
1221 // executed, and their writeback event will add the
1222 // instruction to the queue to commit.
1223 } else {
1224 panic("Unexpected memory type!\n");
1225 }
1226
1227 } else {
1228 inst->execute();
1229
1230 inst->setExecuted();
1231
1232 instToCommit(inst);
1233 }
1234
1235 updateExeInstStats(inst);
1236
1237 // Check if branch prediction was correct, if not then we need
1238 // to tell commit to squash in flight instructions. Only
1239 // handle this if there hasn't already been something that
1240 // redirects fetch in this group of instructions.
1241
1242 // This probably needs to prioritize the redirects if a different
1243 // scheduler is used. Currently the scheduler schedules the oldest
1244 // instruction first, so the branch resolution order will be correct.
1245 unsigned tid = inst->threadNumber;
1246
1247 if (!fetchRedirect[tid]) {
1248
1249 if (inst->mispredicted()) {
1250 fetchRedirect[tid] = true;
1251
1252 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1253 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1254 inst->nextPC);
1255
1256 // If incorrect, then signal the ROB that it must be squashed.
1257 squashDueToBranch(inst, tid);
1258
1259 if (inst->predTaken()) {
1260 predictedTakenIncorrect++;
1261 } else {
1262 predictedNotTakenIncorrect++;
1263 }
1264 } else if (ldstQueue.violation(tid)) {
1265 fetchRedirect[tid] = true;
1266
1267 // If there was an ordering violation, then get the
1268 // DynInst that caused the violation. Note that this
1269 // clears the violation signal.
1270 DynInstPtr violator;
1271 violator = ldstQueue.getMemDepViolator(tid);
1272
1273 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1274 "%#x, inst PC: %#x. Addr is: %#x.\n",
1275 violator->readPC(), inst->readPC(), inst->physEffAddr);
1276
1277 // Tell the instruction queue that a violation has occured.
1278 instQueue.violation(inst, violator);
1279
1280 // Squash.
1281 squashDueToMemOrder(inst,tid);
1282
1283 ++memOrderViolationEvents;
1284 } else if (ldstQueue.loadBlocked(tid) &&
1285 !ldstQueue.isLoadBlockedHandled(tid)) {
1286 fetchRedirect[tid] = true;
1287
1288 DPRINTF(IEW, "Load operation couldn't execute because the "
1289 "memory system is blocked. PC: %#x [sn:%lli]\n",
1290 inst->readPC(), inst->seqNum);
1291
1292 squashDueToMemBlocked(inst, tid);
1293 }
1294 }
1295 }
1296
1297 // Update and record activity if we processed any instructions.
1298 if (inst_num) {
1299 if (exeStatus == Idle) {
1300 exeStatus = Running;
1301 }
1302
1303 updatedQueues = true;
1304
1305 cpu->activityThisCycle();
1306 }
1307
1308 // Need to reset this in case a writeback event needs to write into the
1309 // iew queue. That way the writeback event will write into the correct
1310 // spot in the queue.
1311 wbNumInst = 0;
1312}
1313
1314template <class Impl>
1315void
1316DefaultIEW<Impl>::writebackInsts()
1317{
1318 // Loop through the head of the time buffer and wake any
1319 // dependents. These instructions are about to write back. Also
1320 // mark scoreboard that this instruction is finally complete.
1321 // Either have IEW have direct access to scoreboard, or have this
1322 // as part of backwards communication.
1323 for (int inst_num = 0; inst_num < issueWidth &&
1324 toCommit->insts[inst_num]; inst_num++) {
1325 DynInstPtr inst = toCommit->insts[inst_num];
1326 int tid = inst->threadNumber;
1327
1328 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1329 inst->seqNum, inst->readPC());
1330
1331 iewInstsToCommit[tid]++;
1332
1333 // Some instructions will be sent to commit without having
1334 // executed because they need commit to handle them.
1335 // E.g. Uncached loads have not actually executed when they
1336 // are first sent to commit. Instead commit must tell the LSQ
1337 // when it's ready to execute the uncached load.
1338 if (!inst->isSquashed() && inst->isExecuted()) {
1339 int dependents = instQueue.wakeDependents(inst);
1340
1341 for (int i = 0; i < inst->numDestRegs(); i++) {
1342 //mark as Ready
1343 DPRINTF(IEW,"Setting Destination Register %i\n",
1344 inst->renamedDestRegIdx(i));
1345 scoreboard->setReg(inst->renamedDestRegIdx(i));
1346 }
1347
1348 if (dependents) {
1349 producerInst[tid]++;
1350 consumerInst[tid]+= dependents;
1351 }
1352 writebackCount[tid]++;
1353 }
1354 }
1355}
1356
1357template<class Impl>
1358void
1359DefaultIEW<Impl>::tick()
1360{
1361 wbNumInst = 0;
1362 wbCycle = 0;
1363
1364 wroteToTimeBuffer = false;
1365 updatedQueues = false;
1366
1367 sortInsts();
1368
1369 // Free function units marked as being freed this cycle.
1370 fuPool->processFreeUnits();
1371
1372 list<unsigned>::iterator threads = (*activeThreads).begin();
1373
1374 // Check stall and squash signals, dispatch any instructions.
1375 while (threads != (*activeThreads).end()) {
1376 unsigned tid = *threads++;
1377
1378 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1379
1380 checkSignalsAndUpdate(tid);
1381 dispatch(tid);
1382 }
1383
1384 if (exeStatus != Squashing) {
1385 executeInsts();
1386
1387 writebackInsts();
1388
1389 // Have the instruction queue try to schedule any ready instructions.
1390 // (In actuality, this scheduling is for instructions that will
1391 // be executed next cycle.)
1392 instQueue.scheduleReadyInsts();
1393
1394 // Also should advance its own time buffers if the stage ran.
1395 // Not the best place for it, but this works (hopefully).
1396 issueToExecQueue.advance();
1397 }
1398
1399 bool broadcast_free_entries = false;
1400
1401 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1402 exeStatus = Idle;
1403 updateLSQNextCycle = false;
1404
1405 broadcast_free_entries = true;
1406 }
1407
1408 // Writeback any stores using any leftover bandwidth.
1409 ldstQueue.writebackStores();
1410
1411 // Check the committed load/store signals to see if there's a load
1412 // or store to commit. Also check if it's being told to execute a
1413 // nonspeculative instruction.
1414 // This is pretty inefficient...
1415
1416 threads = (*activeThreads).begin();
1417 while (threads != (*activeThreads).end()) {
1418 unsigned tid = (*threads++);
1419
1420 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1421
1422 // Update structures based on instructions committed.
1423 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1424 !fromCommit->commitInfo[tid].squash &&
1425 !fromCommit->commitInfo[tid].robSquashing) {
1426
1427 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1428
1429 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1430
1431 updateLSQNextCycle = true;
1432 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1433 }
1434
1435 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1436
1437 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1438 if (fromCommit->commitInfo[tid].uncached) {
1439 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1440 } else {
1441 instQueue.scheduleNonSpec(
1442 fromCommit->commitInfo[tid].nonSpecSeqNum);
1443 }
1444 }
1445
1446 if (broadcast_free_entries) {
1447 toFetch->iewInfo[tid].iqCount =
1448 instQueue.getCount(tid);
1449 toFetch->iewInfo[tid].ldstqCount =
1450 ldstQueue.getCount(tid);
1451
1452 toRename->iewInfo[tid].usedIQ = true;
1453 toRename->iewInfo[tid].freeIQEntries =
1454 instQueue.numFreeEntries();
1455 toRename->iewInfo[tid].usedLSQ = true;
1456 toRename->iewInfo[tid].freeLSQEntries =
1457 ldstQueue.numFreeEntries(tid);
1458
1459 wroteToTimeBuffer = true;
1460 }
1461
1462 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1463 tid, toRename->iewInfo[tid].dispatched);
1464 }
1465
1466 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1467 "LSQ has %i free entries.\n",
1468 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1469 ldstQueue.numFreeEntries());
1470
1471 updateStatus();
1472
1473 if (wroteToTimeBuffer) {
1474 DPRINTF(Activity, "Activity this cycle.\n");
1475 cpu->activityThisCycle();
1476 }
1477}
1478
1479template <class Impl>
1480void
1481DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1482{
1483 int thread_number = inst->threadNumber;
1484
1485 //
1486 // Pick off the software prefetches
1487 //
1488#ifdef TARGET_ALPHA
1489 if (inst->isDataPrefetch())
1512 exeSwp[thread_number]++;
1490 iewExecutedSwp[thread_number]++;
1491 else
1514 iewExecutedInsts++;
1492 iewIewExecutedcutedInsts++;
1493#else
1494 iewExecutedInsts++;
1495#endif
1496
1497 //
1498 // Control operations
1499 //
1500 if (inst->isControl())
1523 exeBranches[thread_number]++;
1501 iewExecutedBranches[thread_number]++;
1502
1503 //
1504 // Memory operations
1505 //
1506 if (inst->isMemRef()) {
1529 exeRefs[thread_number]++;
1507 iewExecutedRefs[thread_number]++;
1508
1509 if (inst->isLoad()) {
1510 iewExecLoadInsts[thread_number]++;
1511 }
1512 }
1513}