1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1208 unchanged lines hidden (view full) --- 1217 continue; 1218 } 1219 1220 Fault fault = NoFault; 1221 1222 // Execute instruction. 1223 // Note that if the instruction faults, it will be handled 1224 // at the commit stage. |
1225 if (inst->isMemRef()) { |
1226 DPRINTF(IEW, "Execute: Calculating address for memory " 1227 "reference.\n"); 1228 1229 // Tell the LDSTQ to execute this instruction (if it is a load). 1230 if (inst->isLoad()) { 1231 // Loads will mark themselves as executed, and their writeback 1232 // event adds the instruction to the queue to commit 1233 fault = ldstQueue.executeLoad(inst); |
1234 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1235 fault = NoFault; 1236 } |
1237 } else if (inst->isStore()) { 1238 fault = ldstQueue.executeStore(inst); 1239 1240 // If the store had a fault then it may not have a mem req 1241 if (fault != NoFault || inst->readPredicate() == false || 1242 !inst->isStoreConditional()) { 1243 // If the instruction faulted, then we need to send it along 1244 // to commit without the instruction completing. --- 375 unchanged lines hidden --- |