1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1119 add_to_iq = false;
1120
1121 ++iewDispNonSpecInsts;
1122 } else {
1123 add_to_iq = true;
1124 }
1125
1126 toRename->iewInfo[tid].dispatchedToLSQ++;
1127#if FULL_SYSTEM
1127 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1128 // Same as non-speculative stores.
1129 inst->setCanCommit();
1130 instQueue.insertBarrier(inst);
1131 add_to_iq = false;
1133#endif
1132 } else if (inst->isNonSpeculative()) {
1133 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1134 "encountered, skipping.\n", tid);
1135
1136 // Same as non-speculative stores.
1137 inst->setCanCommit();
1138
1139 // Specifically insert it as nonspeculative.

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