1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 467 unchanged lines hidden (view full) --- 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483#if ISA_HAS_DELAY_SLOT |
484 bool branch_taken = inst->readNextNPC() != 485 (inst->readNextPC() + sizeof(TheISA::MachInst)); |
486 487 toCommit->branchTaken[tid] = branch_taken; 488 |
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot(); 490 491 if (inst->isCondDelaySlot() && branch_taken) { |
492 toCommit->nextPC[tid] = inst->readNextPC(); |
493 } else { |
494 toCommit->nextPC[tid] = inst->readNextNPC(); |
495 } |
496#else 497 toCommit->branchTaken[tid] = inst->readNextPC() != 498 (inst->readPC() + sizeof(TheISA::MachInst)); 499 toCommit->nextPC[tid] = inst->readNextPC(); 500#endif 501 502 toCommit->includeSquashInst[tid] = false; 503 --- 5 unchanged lines hidden (view full) --- 509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 510{ 511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 513 514 toCommit->squash[tid] = true; 515 toCommit->squashedSeqNum[tid] = inst->seqNum; 516 toCommit->nextPC[tid] = inst->readNextPC(); |
517 toCommit->branchMispredict[tid] = false; |
518 519 toCommit->includeSquashInst[tid] = false; 520 521 wroteToTimeBuffer = true; 522} 523 524template<class Impl> 525void 526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 527{ 528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 530 531 toCommit->squash[tid] = true; 532 toCommit->squashedSeqNum[tid] = inst->seqNum; 533 toCommit->nextPC[tid] = inst->readPC(); |
534 toCommit->branchMispredict[tid] = false; |
535 536 // Must include the broadcasted SN in the squash. 537 toCommit->includeSquashInst[tid] = true; 538 539 ldstQueue.setLoadBlockedHandled(tid); 540 541 wroteToTimeBuffer = true; 542} --- 123 unchanged lines hidden (view full) --- 666} 667 668template<class Impl> 669int 670DefaultIEW<Impl>::skidCount() 671{ 672 int max=0; 673 |
674 std::list<unsigned>::iterator threads = activeThreads->begin(); 675 std::list<unsigned>::iterator end = activeThreads->end(); |
676 |
677 while (threads != end) { 678 unsigned tid = *threads++; 679 unsigned thread_count = skidBuffer[tid].size(); |
680 if (max < thread_count) 681 max = thread_count; 682 } 683 684 return max; 685} 686 687template<class Impl> 688bool 689DefaultIEW<Impl>::skidsEmpty() 690{ |
691 std::list<unsigned>::iterator threads = activeThreads->begin(); 692 std::list<unsigned>::iterator end = activeThreads->end(); |
693 |
694 while (threads != end) { 695 unsigned tid = *threads++; 696 697 if (!skidBuffer[tid].empty()) |
698 return false; 699 } 700 701 return true; 702} 703 704template <class Impl> 705void 706DefaultIEW<Impl>::updateStatus() 707{ 708 bool any_unblocking = false; 709 |
710 std::list<unsigned>::iterator threads = activeThreads->begin(); 711 std::list<unsigned>::iterator end = activeThreads->end(); |
712 |
713 while (threads != end) { |
714 unsigned tid = *threads++; 715 716 if (dispatchStatus[tid] == Unblocking) { 717 any_unblocking = true; 718 break; 719 } 720 } 721 --- 503 unchanged lines hidden (view full) --- 1225 1226template <class Impl> 1227void 1228DefaultIEW<Impl>::executeInsts() 1229{ 1230 wbNumInst = 0; 1231 wbCycle = 0; 1232 |
1233 std::list<unsigned>::iterator threads = activeThreads->begin(); 1234 std::list<unsigned>::iterator end = activeThreads->end(); |
1235 |
1236 while (threads != end) { |
1237 unsigned tid = *threads++; 1238 fetchRedirect[tid] = false; 1239 } 1240 1241 // Uncomment this if you want to see all available instructions. 1242// printAvailableInsts(); 1243 1244 // Execute/writeback any instructions that are available. --- 48 unchanged lines hidden (view full) --- 1293 // If the store had a fault then it may not have a mem req 1294 if (!inst->isStoreConditional() && fault == NoFault) { 1295 inst->setExecuted(); 1296 1297 instToCommit(inst); 1298 } else if (fault != NoFault) { 1299 // If the instruction faulted, then we need to send it along to commit 1300 // without the instruction completing. |
1301 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 1302 fault->name(), inst->seqNum); |
1303 1304 // Send this instruction to commit, also make sure iew stage 1305 // realizes there is activity. 1306 inst->setExecuted(); 1307 1308 instToCommit(inst); 1309 activityThisCycle(); 1310 } --- 20 unchanged lines hidden (view full) --- 1331 // handle this if there hasn't already been something that 1332 // redirects fetch in this group of instructions. 1333 1334 // This probably needs to prioritize the redirects if a different 1335 // scheduler is used. Currently the scheduler schedules the oldest 1336 // instruction first, so the branch resolution order will be correct. 1337 unsigned tid = inst->threadNumber; 1338 |
1339 if (!fetchRedirect[tid] || 1340 toCommit->squashedSeqNum[tid] > inst->seqNum) { |
1341 1342 if (inst->mispredicted()) { 1343 fetchRedirect[tid] = true; 1344 1345 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); |
1346#if ISA_HAS_DELAY_SLOT 1347 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1348 inst->nextNPC); 1349#else 1350 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1351 inst->nextPC); 1352#endif 1353 // If incorrect, then signal the ROB that it must be squashed. 1354 squashDueToBranch(inst, tid); 1355 |
1356 if (inst->predTaken()) { |
1357 predictedTakenIncorrect++; 1358 } else { 1359 predictedNotTakenIncorrect++; 1360 } 1361 } else if (ldstQueue.violation(tid)) { |
1362 // If there was an ordering violation, then get the 1363 // DynInst that caused the violation. Note that this 1364 // clears the violation signal. 1365 DynInstPtr violator; 1366 violator = ldstQueue.getMemDepViolator(tid); 1367 1368 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1369 "%#x, inst PC: %#x. Addr is: %#x.\n", 1370 violator->readPC(), inst->readPC(), inst->physEffAddr); 1371 |
1372 // Ensure the violating instruction is older than 1373 // current squash 1374 if (fetchRedirect[tid] && 1375 violator->seqNum >= toCommit->squashedSeqNum[tid]) 1376 continue; 1377 1378 fetchRedirect[tid] = true; 1379 |
1380 // Tell the instruction queue that a violation has occured. 1381 instQueue.violation(inst, violator); 1382 1383 // Squash. 1384 squashDueToMemOrder(inst,tid); 1385 1386 ++memOrderViolationEvents; 1387 } else if (ldstQueue.loadBlocked(tid) && --- 81 unchanged lines hidden (view full) --- 1469 wroteToTimeBuffer = false; 1470 updatedQueues = false; 1471 1472 sortInsts(); 1473 1474 // Free function units marked as being freed this cycle. 1475 fuPool->processFreeUnits(); 1476 |
1477 std::list<unsigned>::iterator threads = activeThreads->begin(); 1478 std::list<unsigned>::iterator end = activeThreads->end(); |
1479 1480 // Check stall and squash signals, dispatch any instructions. |
1481 while (threads != end) { 1482 unsigned tid = *threads++; |
1483 1484 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1485 1486 checkSignalsAndUpdate(tid); 1487 dispatch(tid); 1488 } 1489 1490 if (exeStatus != Squashing) { --- 23 unchanged lines hidden (view full) --- 1514 // Writeback any stores using any leftover bandwidth. 1515 ldstQueue.writebackStores(); 1516 1517 // Check the committed load/store signals to see if there's a load 1518 // or store to commit. Also check if it's being told to execute a 1519 // nonspeculative instruction. 1520 // This is pretty inefficient... 1521 |
1522 threads = activeThreads->begin(); 1523 while (threads != end) { |
1524 unsigned tid = (*threads++); 1525 1526 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1527 1528 // Update structures based on instructions committed. 1529 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1530 !fromCommit->commitInfo[tid].squash && 1531 !fromCommit->commitInfo[tid].robSquashing) { --- 88 unchanged lines hidden --- |