1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 467 unchanged lines hidden (view full) --- 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483#if ISA_HAS_DELAY_SLOT |
484 bool branch_taken = 485 (inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) && 486 inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst))); 487 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 488 branch_taken ? "true": "false", inst->seqNum); |
489 490 toCommit->branchTaken[tid] = branch_taken; 491 |
492 bool squashDelaySlot = 493 (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 494 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 495 squashDelaySlot ? "true": "false", inst->seqNum); 496 toCommit->squashDelaySlot[tid] = squashDelaySlot; 497 //If we're squashing the delay slot, we need to pick back up at NextPC. 498 //Otherwise, NextPC isn't being squashed, so we should pick back up at 499 //NextNPC. 500 if (squashDelaySlot) |
501 toCommit->nextPC[tid] = inst->readNextPC(); |
502 else |
503 toCommit->nextPC[tid] = inst->readNextNPC(); |
504#else 505 toCommit->branchTaken[tid] = inst->readNextPC() != 506 (inst->readPC() + sizeof(TheISA::MachInst)); 507 toCommit->nextPC[tid] = inst->readNextPC(); 508#endif 509 510 toCommit->includeSquashInst[tid] = false; 511 --- 5 unchanged lines hidden (view full) --- 517DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 518{ 519 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 520 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 521 522 toCommit->squash[tid] = true; 523 toCommit->squashedSeqNum[tid] = inst->seqNum; 524 toCommit->nextPC[tid] = inst->readNextPC(); |
525 526 toCommit->includeSquashInst[tid] = false; 527 528 wroteToTimeBuffer = true; 529} 530 531template<class Impl> 532void 533DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 534{ 535 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 536 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 537 538 toCommit->squash[tid] = true; 539 toCommit->squashedSeqNum[tid] = inst->seqNum; 540 toCommit->nextPC[tid] = inst->readPC(); |
541 542 // Must include the broadcasted SN in the squash. 543 toCommit->includeSquashInst[tid] = true; 544 545 ldstQueue.setLoadBlockedHandled(tid); 546 547 wroteToTimeBuffer = true; 548} --- 745 unchanged lines hidden (view full) --- 1294 // If the store had a fault then it may not have a mem req 1295 if (!inst->isStoreConditional() && fault == NoFault) { 1296 inst->setExecuted(); 1297 1298 instToCommit(inst); 1299 } else if (fault != NoFault) { 1300 // If the instruction faulted, then we need to send it along to commit 1301 // without the instruction completing. |
1302 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum); |
1303 1304 // Send this instruction to commit, also make sure iew stage 1305 // realizes there is activity. 1306 inst->setExecuted(); 1307 1308 instToCommit(inst); 1309 activityThisCycle(); 1310 } --- 20 unchanged lines hidden (view full) --- 1331 // handle this if there hasn't already been something that 1332 // redirects fetch in this group of instructions. 1333 1334 // This probably needs to prioritize the redirects if a different 1335 // scheduler is used. Currently the scheduler schedules the oldest 1336 // instruction first, so the branch resolution order will be correct. 1337 unsigned tid = inst->threadNumber; 1338 |
1339 if (!fetchRedirect[tid]) { |
1340 1341 if (inst->mispredicted()) { 1342 fetchRedirect[tid] = true; 1343 1344 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1345#if ISA_HAS_DELAY_SLOT 1346 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1347 inst->nextNPC); --- 5 unchanged lines hidden (view full) --- 1353 squashDueToBranch(inst, tid); 1354 1355 if (inst->predTaken()) { 1356 predictedTakenIncorrect++; 1357 } else { 1358 predictedNotTakenIncorrect++; 1359 } 1360 } else if (ldstQueue.violation(tid)) { |
1361 fetchRedirect[tid] = true; 1362 |
1363 // If there was an ordering violation, then get the 1364 // DynInst that caused the violation. Note that this 1365 // clears the violation signal. 1366 DynInstPtr violator; 1367 violator = ldstQueue.getMemDepViolator(tid); 1368 1369 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1370 "%#x, inst PC: %#x. Addr is: %#x.\n", 1371 violator->readPC(), inst->readPC(), inst->physEffAddr); 1372 |
1373 // Tell the instruction queue that a violation has occured. 1374 instQueue.violation(inst, violator); 1375 1376 // Squash. 1377 squashDueToMemOrder(inst,tid); 1378 1379 ++memOrderViolationEvents; 1380 } else if (ldstQueue.loadBlocked(tid) && --- 231 unchanged lines hidden --- |