1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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88
89template <class Impl>
90void
91DefaultIEW<Impl>::regStats()
92{
93 using namespace Stats;
94
95 instQueue.regStats();
96 ldstQueue.regStats();
97
98 iewIdleCycles
99 .name(name() + ".iewIdleCycles")
100 .desc("Number of cycles IEW is idle");
101
102 iewSquashCycles
103 .name(name() + ".iewSquashCycles")
104 .desc("Number of cycles IEW is squashing");

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134 iewIQFullEvents
135 .name(name() + ".iewIQFullEvents")
136 .desc("Number of times the IQ has become full, causing a stall");
137
138 iewLSQFullEvents
139 .name(name() + ".iewLSQFullEvents")
140 .desc("Number of times the LSQ has become full, causing a stall");
141
141 iewExecutedInsts
142 .name(name() + ".iewExecutedInsts")
143 .desc("Number of executed instructions");
144
145 iewExecLoadInsts
146 .init(cpu->number_of_threads)
147 .name(name() + ".iewExecLoadInsts")
148 .desc("Number of load instructions executed")
149 .flags(total);
150
151 iewExecSquashedInsts
152 .name(name() + ".iewExecSquashedInsts")
153 .desc("Number of squashed instructions skipped in execute");
154
142 memOrderViolationEvents
143 .name(name() + ".memOrderViolationEvents")
144 .desc("Number of memory order violations");
145
146 predictedTakenIncorrect
147 .name(name() + ".predictedTakenIncorrect")
148 .desc("Number of branches that were predicted taken incorrectly");
149
150 predictedNotTakenIncorrect
151 .name(name() + ".predictedNotTakenIncorrect")
152 .desc("Number of branches that were predicted not taken incorrectly");
153
154 branchMispredicts
155 .name(name() + ".branchMispredicts")
156 .desc("Number of branch mispredicts detected at execute");
157
158 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
159
173 exeSwp
160 iewExecutedInsts
161 .name(name() + ".EXEC:insts")
162 .desc("Number of executed instructions");
163
164 iewExecLoadInsts
165 .init(cpu->number_of_threads)
166 .name(name() + ".EXEC:loads")
167 .desc("Number of load instructions executed")
168 .flags(total);
169
170 iewExecSquashedInsts
171 .name(name() + ".EXEC:squashedInsts")
172 .desc("Number of squashed instructions skipped in execute");
173
174 iewExecutedSwp
175 .init(cpu->number_of_threads)
176 .name(name() + ".EXEC:swp")
177 .desc("number of swp insts executed")
177 .flags(total)
178 ;
178 .flags(total);
179
180 exeNop
180 iewExecutedNop
181 .init(cpu->number_of_threads)
182 .name(name() + ".EXEC:nop")
183 .desc("number of nop insts executed")
184 .flags(total)
185 ;
184 .flags(total);
185
187 exeRefs
186 iewExecutedRefs
187 .init(cpu->number_of_threads)
188 .name(name() + ".EXEC:refs")
189 .desc("number of memory reference insts executed")
191 .flags(total)
192 ;
190 .flags(total);
191
194 exeBranches
192 iewExecutedBranches
193 .init(cpu->number_of_threads)
194 .name(name() + ".EXEC:branches")
195 .desc("Number of branches executed")
198 .flags(total)
199 ;
196 .flags(total);
197
201 issueRate
202 .name(name() + ".EXEC:rate")
203 .desc("Inst execution rate")
204 .flags(total)
205 ;
206 issueRate = iewExecutedInsts / cpu->numCycles;
207
198 iewExecStoreInsts
199 .name(name() + ".EXEC:stores")
200 .desc("Number of stores executed")
211 .flags(total)
212 ;
213 iewExecStoreInsts = exeRefs - iewExecLoadInsts;
214/*
215 for (int i=0; i<Num_OpClasses; ++i) {
216 stringstream subname;
217 subname << opClassStrings[i] << "_delay";
218 issue_delay_dist.subname(i, subname.str());
219 }
220*/
221 //
222 // Other stats
223 //
201 .flags(total);
202 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
203
204 iewExecRate
205 .name(name() + ".EXEC:rate")
206 .desc("Inst execution rate")
207 .flags(total);
208
209 iewExecRate = iewExecutedInsts / cpu->numCycles;
210
211 iewInstsToCommit
212 .init(cpu->number_of_threads)
213 .name(name() + ".WB:sent")
214 .desc("cumulative count of insts sent to commit")
229 .flags(total)
230 ;
215 .flags(total);
216
217 writebackCount
218 .init(cpu->number_of_threads)
219 .name(name() + ".WB:count")
220 .desc("cumulative count of insts written-back")
236 .flags(total)
237 ;
221 .flags(total);
222
223 producerInst
224 .init(cpu->number_of_threads)
225 .name(name() + ".WB:producers")
226 .desc("num instructions producing a value")
243 .flags(total)
244 ;
227 .flags(total);
228
229 consumerInst
230 .init(cpu->number_of_threads)
231 .name(name() + ".WB:consumers")
232 .desc("num instructions consuming a value")
250 .flags(total)
251 ;
233 .flags(total);
234
235 wbPenalized
236 .init(cpu->number_of_threads)
237 .name(name() + ".WB:penalized")
238 .desc("number of instrctions required to write to 'other' IQ")
257 .flags(total)
258 ;
239 .flags(total);
240
241 wbPenalizedRate
242 .name(name() + ".WB:penalized_rate")
243 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
263 .flags(total)
264 ;
244 .flags(total);
245
246 wbPenalizedRate = wbPenalized / writebackCount;
247
248 wbFanout
249 .name(name() + ".WB:fanout")
250 .desc("average fanout of values written-back")
271 .flags(total)
272 ;
251 .flags(total);
252
253 wbFanout = producerInst / consumerInst;
254
255 wbRate
256 .name(name() + ".WB:rate")
257 .desc("insts written-back per cycle")
279 .flags(total)
280 ;
258 .flags(total);
259 wbRate = writebackCount / cpu->numCycles;
260}
261
262template<class Impl>
263void
264DefaultIEW<Impl>::initStage()
265{
266 for (int tid=0; tid < numThreads; tid++) {

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1071 "skipping.\n", tid);
1072
1073 inst->setIssued();
1074 inst->setExecuted();
1075 inst->setCanCommit();
1076
1077 instQueue.recordProducer(inst);
1078
1101 exeNop[tid]++;
1079 iewExecutedNop[tid]++;
1080
1081 add_to_iq = false;
1082 } else if (inst->isExecuted()) {
1083 assert(0 && "Instruction shouldn't be executed.\n");
1084 DPRINTF(IEW, "Issue: Executed branch encountered, "
1085 "skipping.\n");
1086
1087 inst->setIssued();

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1482{
1483 int thread_number = inst->threadNumber;
1484
1485 //
1486 // Pick off the software prefetches
1487 //
1488#ifdef TARGET_ALPHA
1489 if (inst->isDataPrefetch())
1512 exeSwp[thread_number]++;
1490 iewExecutedSwp[thread_number]++;
1491 else
1514 iewExecutedInsts++;
1492 iewIewExecutedcutedInsts++;
1493#else
1494 iewExecutedInsts++;
1495#endif
1496
1497 //
1498 // Control operations
1499 //
1500 if (inst->isControl())
1523 exeBranches[thread_number]++;
1501 iewExecutedBranches[thread_number]++;
1502
1503 //
1504 // Memory operations
1505 //
1506 if (inst->isMemRef()) {
1529 exeRefs[thread_number]++;
1507 iewExecutedRefs[thread_number]++;
1508
1509 if (inst->isLoad()) {
1510 iewExecLoadInsts[thread_number]++;
1511 }
1512 }
1513}