1/* 2 * Copyright (c) 2010-2013, 2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 465 unchanged lines hidden (view full) --- 474 // Clear the skid buffer in case it has any data in it. 475 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 476 tid, fromCommit->commitInfo[tid].doneSeqNum); 477 478 while (!skidBuffer[tid].empty()) { 479 if (skidBuffer[tid].front()->isLoad()) { 480 toRename->iewInfo[tid].dispatchedToLQ++; 481 } |
482 if (skidBuffer[tid].front()->isStore() || 483 skidBuffer[tid].front()->isAtomic()) { |
484 toRename->iewInfo[tid].dispatchedToSQ++; 485 } 486 487 toRename->iewInfo[tid].dispatched++; 488 489 skidBuffer[tid].pop(); 490 } 491 --- 366 unchanged lines hidden (view full) --- 858{ 859 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 860 861 while (!insts[tid].empty()) { 862 863 if (insts[tid].front()->isLoad()) { 864 toRename->iewInfo[tid].dispatchedToLQ++; 865 } |
866 if (insts[tid].front()->isStore() || 867 insts[tid].front()->isAtomic()) { |
868 toRename->iewInfo[tid].dispatchedToSQ++; 869 } 870 871 toRename->iewInfo[tid].dispatched++; 872 873 insts[tid].pop(); 874 } 875} --- 125 unchanged lines hidden (view full) --- 1001 ++iewDispSquashedInsts; 1002 1003 insts_to_dispatch.pop(); 1004 1005 //Tell Rename That An Instruction has been processed 1006 if (inst->isLoad()) { 1007 toRename->iewInfo[tid].dispatchedToLQ++; 1008 } |
1009 if (inst->isStore() || inst->isAtomic()) { |
1010 toRename->iewInfo[tid].dispatchedToSQ++; 1011 } 1012 1013 toRename->iewInfo[tid].dispatched++; 1014 1015 continue; 1016 } 1017 --- 9 unchanged lines hidden (view full) --- 1027 // get full in the IQ. 1028 toRename->iewUnblock[tid] = false; 1029 1030 ++iewIQFullEvents; 1031 break; 1032 } 1033 1034 // Check LSQ if inst is LD/ST |
1035 if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 1036 (inst->isLoad() && ldstQueue.lqFull(tid)) || |
1037 (inst->isStore() && ldstQueue.sqFull(tid))) { 1038 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1039 inst->isLoad() ? "LQ" : "SQ"); 1040 1041 // Call function to start blocking. 1042 block(tid); 1043 1044 // Set unblock to false. Special case where we are using 1045 // skidbuffer (unblocking) instructions but then we still 1046 // get full in the IQ. 1047 toRename->iewUnblock[tid] = false; 1048 1049 ++iewLSQFullEvents; 1050 break; 1051 } 1052 1053 // Otherwise issue the instruction just fine. |
1054 if (inst->isAtomic()) { |
1055 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1056 "encountered, adding to LSQ.\n", tid); 1057 |
1058 ldstQueue.insertStore(inst); 1059 1060 ++iewDispStoreInsts; 1061 1062 // AMOs need to be set as "canCommit()" 1063 // so that commit can process them when they reach the 1064 // head of commit. 1065 inst->setCanCommit(); 1066 instQueue.insertNonSpec(inst); 1067 add_to_iq = false; 1068 1069 ++iewDispNonSpecInsts; 1070 1071 toRename->iewInfo[tid].dispatchedToSQ++; 1072 } else if (inst->isLoad()) { 1073 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1074 "encountered, adding to LSQ.\n", tid); 1075 |
1076 // Reserve a spot in the load store queue for this 1077 // memory access. 1078 ldstQueue.insertLoad(inst); 1079 1080 ++iewDispLoadInsts; 1081 1082 add_to_iq = true; 1083 --- 175 unchanged lines hidden (view full) --- 1259 // Execute instruction. 1260 // Note that if the instruction faults, it will be handled 1261 // at the commit stage. 1262 if (inst->isMemRef()) { 1263 DPRINTF(IEW, "Execute: Calculating address for memory " 1264 "reference.\n"); 1265 1266 // Tell the LDSTQ to execute this instruction (if it is a load). |
1267 if (inst->isAtomic()) { 1268 // AMOs are treated like store requests 1269 fault = ldstQueue.executeStore(inst); 1270 1271 if (inst->isTranslationDelayed() && 1272 fault == NoFault) { 1273 // A hw page table walk is currently going on; the 1274 // instruction must be deferred. 1275 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1276 "store.\n"); 1277 instQueue.deferMemInst(inst); 1278 continue; 1279 } 1280 } else if (inst->isLoad()) { |
1281 // Loads will mark themselves as executed, and their writeback 1282 // event adds the instruction to the queue to commit 1283 fault = ldstQueue.executeLoad(inst); 1284 1285 if (inst->isTranslationDelayed() && 1286 fault == NoFault) { 1287 // A hw page table walk is currently going on; the 1288 // instruction must be deferred. --- 397 unchanged lines hidden --- |