482c482,483
< if (skidBuffer[tid].front()->isStore()) {
---
> if (skidBuffer[tid].front()->isStore() ||
> skidBuffer[tid].front()->isAtomic()) {
865c866,867
< if (insts[tid].front()->isStore()) {
---
> if (insts[tid].front()->isStore() ||
> insts[tid].front()->isAtomic()) {
1007c1009
< if (inst->isStore()) {
---
> if (inst->isStore() || inst->isAtomic()) {
1033c1035,1036
< if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
---
> if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
> (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1051c1054
< if (inst->isLoad()) {
---
> if (inst->isAtomic()) {
1054a1058,1075
> ldstQueue.insertStore(inst);
>
> ++iewDispStoreInsts;
>
> // AMOs need to be set as "canCommit()"
> // so that commit can process them when they reach the
> // head of commit.
> inst->setCanCommit();
> instQueue.insertNonSpec(inst);
> add_to_iq = false;
>
> ++iewDispNonSpecInsts;
>
> toRename->iewInfo[tid].dispatchedToSQ++;
> } else if (inst->isLoad()) {
> DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
> "encountered, adding to LSQ.\n", tid);
>
1246c1267,1280
< if (inst->isLoad()) {
---
> if (inst->isAtomic()) {
> // AMOs are treated like store requests
> fault = ldstQueue.executeStore(inst);
>
> if (inst->isTranslationDelayed() &&
> fault == NoFault) {
> // A hw page table walk is currently going on; the
> // instruction must be deferred.
> DPRINTF(IEW, "Execute: Delayed translation, deferring "
> "store.\n");
> instQueue.deferMemInst(inst);
> continue;
> }
> } else if (inst->isLoad()) {