455,459c455,461
< toCommit->squash[tid] = true;
< toCommit->squashedSeqNum[tid] = inst->seqNum;
< toCommit->mispredPC[tid] = inst->instAddr();
< toCommit->branchMispredict[tid] = true;
< toCommit->mispredictInst[tid] = inst;
---
> if (toCommit->squash[tid] == false ||
> inst->seqNum < toCommit->squashedSeqNum[tid]) {
> toCommit->squash[tid] = true;
> toCommit->squashedSeqNum[tid] = inst->seqNum;
> toCommit->mispredPC[tid] = inst->instAddr();
> toCommit->branchMispredict[tid] = true;
> toCommit->branchTaken[tid] = inst->pcState().branching();
461,464c463,464
< toCommit->branchTaken[tid] = inst->pcState().branching();
< TheISA::PCState pc = inst->pcState();
< TheISA::advancePC(pc, inst->staticInst);
< toCommit->pc[tid] = pc;
---
> TheISA::PCState pc = inst->pcState();
> TheISA::advancePC(pc, inst->staticInst);
466c466,468
< toCommit->includeSquashInst[tid] = false;
---
> toCommit->pc[tid] = pc;
> toCommit->mispredictInst[tid] = inst;
> toCommit->includeSquashInst[tid] = false;
468c470,472
< wroteToTimeBuffer = true;
---
> wroteToTimeBuffer = true;
> }
>
478,483c482,489
< toCommit->squash[tid] = true;
< toCommit->squashedSeqNum[tid] = inst->seqNum;
< TheISA::PCState pc = inst->pcState();
< TheISA::advancePC(pc, inst->staticInst);
< toCommit->pc[tid] = pc;
< toCommit->branchMispredict[tid] = false;
---
> if (toCommit->squash[tid] == false ||
> inst->seqNum < toCommit->squashedSeqNum[tid]) {
> toCommit->squash[tid] = true;
> toCommit->squashedSeqNum[tid] = inst->seqNum;
> TheISA::PCState pc = inst->pcState();
> TheISA::advancePC(pc, inst->staticInst);
> toCommit->pc[tid] = pc;
> toCommit->branchMispredict[tid] = false;
485c491
< toCommit->includeSquashInst[tid] = false;
---
> toCommit->includeSquashInst[tid] = false;
487c493,494
< wroteToTimeBuffer = true;
---
> wroteToTimeBuffer = true;
> }
495a503,505
> if (toCommit->squash[tid] == false ||
> inst->seqNum < toCommit->squashedSeqNum[tid]) {
> toCommit->squash[tid] = true;
497,500c507,509
< toCommit->squash[tid] = true;
< toCommit->squashedSeqNum[tid] = inst->seqNum;
< toCommit->pc[tid] = inst->pcState();
< toCommit->branchMispredict[tid] = false;
---
> toCommit->squashedSeqNum[tid] = inst->seqNum;
> toCommit->pc[tid] = inst->pcState();
> toCommit->branchMispredict[tid] = false;
502,503c511,512
< // Must include the broadcasted SN in the squash.
< toCommit->includeSquashInst[tid] = true;
---
> // Must include the broadcasted SN in the squash.
> toCommit->includeSquashInst[tid] = true;
505c514
< ldstQueue.setLoadBlockedHandled(tid);
---
> ldstQueue.setLoadBlockedHandled(tid);
507c516,517
< wroteToTimeBuffer = true;
---
> wroteToTimeBuffer = true;
> }
791d800
<
800d808
<
1288a1297
> !toCommit->squash[tid] ||
1384a1394
>
1598a1609
> !toCommit->squash[tid] ||