410
411 startupStage();
412 cpu->activityThisCycle();
413
414 for (ThreadID tid = 0; tid < numThreads; tid++) {
415 dispatchStatus[tid] = Running;
416 stalls[tid].commit = false;
417 fetchRedirect[tid] = false;
418 }
419
420 updateLSQNextCycle = false;
421
422 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
423 issueToExecQueue.advance();
424 }
425}
426
427template<class Impl>
428void
429DefaultIEW<Impl>::squash(ThreadID tid)
430{
431 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
432
433 // Tell the IQ to start squashing.
434 instQueue.squash(tid);
435
436 // Tell the LDSTQ to start squashing.
437 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
438 updatedQueues = true;
439
440 // Clear the skid buffer in case it has any data in it.
441 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
442 tid, fromCommit->commitInfo[tid].doneSeqNum);
443
444 while (!skidBuffer[tid].empty()) {
445 if (skidBuffer[tid].front()->isLoad() ||
446 skidBuffer[tid].front()->isStore() ) {
447 toRename->iewInfo[tid].dispatchedToLSQ++;
448 }
449
450 toRename->iewInfo[tid].dispatched++;
451
452 skidBuffer[tid].pop();
453 }
454
455 emptyRenameInsts(tid);
456}
457
458template<class Impl>
459void
460DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
461{
462 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
463 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
464
465 if (toCommit->squash[tid] == false ||
466 inst->seqNum < toCommit->squashedSeqNum[tid]) {
467 toCommit->squash[tid] = true;
468 toCommit->squashedSeqNum[tid] = inst->seqNum;
469 toCommit->branchTaken[tid] = inst->pcState().branching();
470
471 TheISA::PCState pc = inst->pcState();
472 TheISA::advancePC(pc, inst->staticInst);
473
474 toCommit->pc[tid] = pc;
475 toCommit->mispredictInst[tid] = inst;
476 toCommit->includeSquashInst[tid] = false;
477
478 wroteToTimeBuffer = true;
479 }
480
481}
482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
488 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489 // Need to include inst->seqNum in the following comparison to cover the
490 // corner case when a branch misprediction and a memory violation for the
491 // same instruction (e.g. load PC) are detected in the same cycle. In this
492 // case the memory violator should take precedence over the branch
493 // misprediction because it requires the violator itself to be included in
494 // the squash.
495 if (toCommit->squash[tid] == false ||
496 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
497 toCommit->squash[tid] = true;
498
499 toCommit->squashedSeqNum[tid] = inst->seqNum;
500 toCommit->pc[tid] = inst->pcState();
501 toCommit->mispredictInst[tid] = NULL;
502
503 // Must include the memory violator in the squash.
504 toCommit->includeSquashInst[tid] = true;
505
506 wroteToTimeBuffer = true;
507 }
508}
509
510template<class Impl>
511void
512DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
513{
514 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
515 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
516 if (toCommit->squash[tid] == false ||
517 inst->seqNum < toCommit->squashedSeqNum[tid]) {
518 toCommit->squash[tid] = true;
519
520 toCommit->squashedSeqNum[tid] = inst->seqNum;
521 toCommit->pc[tid] = inst->pcState();
522 toCommit->mispredictInst[tid] = NULL;
523
524 // Must include the broadcasted SN in the squash.
525 toCommit->includeSquashInst[tid] = true;
526
527 ldstQueue.setLoadBlockedHandled(tid);
528
529 wroteToTimeBuffer = true;
530 }
531}
532
533template<class Impl>
534void
535DefaultIEW<Impl>::block(ThreadID tid)
536{
537 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
538
539 if (dispatchStatus[tid] != Blocked &&
540 dispatchStatus[tid] != Unblocking) {
541 toRename->iewBlock[tid] = true;
542 wroteToTimeBuffer = true;
543 }
544
545 // Add the current inputs to the skid buffer so they can be
546 // reprocessed when this stage unblocks.
547 skidInsert(tid);
548
549 dispatchStatus[tid] = Blocked;
550}
551
552template<class Impl>
553void
554DefaultIEW<Impl>::unblock(ThreadID tid)
555{
556 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
557 "buffer %u.\n",tid, tid);
558
559 // If the skid bufffer is empty, signal back to previous stages to unblock.
560 // Also switch status to running.
561 if (skidBuffer[tid].empty()) {
562 toRename->iewUnblock[tid] = true;
563 wroteToTimeBuffer = true;
564 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
565 dispatchStatus[tid] = Running;
566 }
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
572{
573 instQueue.wakeDependents(inst);
574}
575
576template<class Impl>
577void
578DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
579{
580 instQueue.rescheduleMemInst(inst);
581}
582
583template<class Impl>
584void
585DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
586{
587 instQueue.replayMemInst(inst);
588}
589
590template<class Impl>
591void
592DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
593{
594 // This function should not be called after writebackInsts in a
595 // single cycle. That will cause problems with an instruction
596 // being added to the queue to commit without being processed by
597 // writebackInsts prior to being sent to commit.
598
599 // First check the time slot that this instruction will write
600 // to. If there are free write ports at the time, then go ahead
601 // and write the instruction to that time. If there are not,
602 // keep looking back to see where's the first time there's a
603 // free slot.
604 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
605 ++wbNumInst;
606 if (wbNumInst == wbWidth) {
607 ++wbCycle;
608 wbNumInst = 0;
609 }
610
611 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
612 }
613
614 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
615 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
616 // Add finished instruction to queue to commit.
617 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
618 (*iewQueue)[wbCycle].size++;
619}
620
621template <class Impl>
622unsigned
623DefaultIEW<Impl>::validInstsFromRename()
624{
625 unsigned inst_count = 0;
626
627 for (int i=0; i<fromRename->size; i++) {
628 if (!fromRename->insts[i]->isSquashed())
629 inst_count++;
630 }
631
632 return inst_count;
633}
634
635template<class Impl>
636void
637DefaultIEW<Impl>::skidInsert(ThreadID tid)
638{
639 DynInstPtr inst = NULL;
640
641 while (!insts[tid].empty()) {
642 inst = insts[tid].front();
643
644 insts[tid].pop();
645
646 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
647 "dispatch skidBuffer %i\n",tid, inst->seqNum,
648 inst->pcState(),tid);
649
650 skidBuffer[tid].push(inst);
651 }
652
653 assert(skidBuffer[tid].size() <= skidBufferMax &&
654 "Skidbuffer Exceeded Max Size");
655}
656
657template<class Impl>
658int
659DefaultIEW<Impl>::skidCount()
660{
661 int max=0;
662
663 list<ThreadID>::iterator threads = activeThreads->begin();
664 list<ThreadID>::iterator end = activeThreads->end();
665
666 while (threads != end) {
667 ThreadID tid = *threads++;
668 unsigned thread_count = skidBuffer[tid].size();
669 if (max < thread_count)
670 max = thread_count;
671 }
672
673 return max;
674}
675
676template<class Impl>
677bool
678DefaultIEW<Impl>::skidsEmpty()
679{
680 list<ThreadID>::iterator threads = activeThreads->begin();
681 list<ThreadID>::iterator end = activeThreads->end();
682
683 while (threads != end) {
684 ThreadID tid = *threads++;
685
686 if (!skidBuffer[tid].empty())
687 return false;
688 }
689
690 return true;
691}
692
693template <class Impl>
694void
695DefaultIEW<Impl>::updateStatus()
696{
697 bool any_unblocking = false;
698
699 list<ThreadID>::iterator threads = activeThreads->begin();
700 list<ThreadID>::iterator end = activeThreads->end();
701
702 while (threads != end) {
703 ThreadID tid = *threads++;
704
705 if (dispatchStatus[tid] == Unblocking) {
706 any_unblocking = true;
707 break;
708 }
709 }
710
711 // If there are no ready instructions waiting to be scheduled by the IQ,
712 // and there's no stores waiting to write back, and dispatch is not
713 // unblocking, then there is no internal activity for the IEW stage.
714 instQueue.intInstQueueReads++;
715 if (_status == Active && !instQueue.hasReadyInsts() &&
716 !ldstQueue.willWB() && !any_unblocking) {
717 DPRINTF(IEW, "IEW switching to idle\n");
718
719 deactivateStage();
720
721 _status = Inactive;
722 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
723 ldstQueue.willWB() ||
724 any_unblocking)) {
725 // Otherwise there is internal activity. Set to active.
726 DPRINTF(IEW, "IEW switching to active\n");
727
728 activateStage();
729
730 _status = Active;
731 }
732}
733
734template <class Impl>
735void
736DefaultIEW<Impl>::resetEntries()
737{
738 instQueue.resetEntries();
739 ldstQueue.resetEntries();
740}
741
742template <class Impl>
743void
744DefaultIEW<Impl>::readStallSignals(ThreadID tid)
745{
746 if (fromCommit->commitBlock[tid]) {
747 stalls[tid].commit = true;
748 }
749
750 if (fromCommit->commitUnblock[tid]) {
751 assert(stalls[tid].commit);
752 stalls[tid].commit = false;
753 }
754}
755
756template <class Impl>
757bool
758DefaultIEW<Impl>::checkStall(ThreadID tid)
759{
760 bool ret_val(false);
761
762 if (stalls[tid].commit) {
763 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
764 ret_val = true;
765 } else if (instQueue.isFull(tid)) {
766 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
767 ret_val = true;
768 } else if (ldstQueue.isFull(tid)) {
769 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
770
771 if (ldstQueue.numLoads(tid) > 0 ) {
772
773 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
774 tid,ldstQueue.getLoadHeadSeqNum(tid));
775 }
776
777 if (ldstQueue.numStores(tid) > 0) {
778
779 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
780 tid,ldstQueue.getStoreHeadSeqNum(tid));
781 }
782
783 ret_val = true;
784 } else if (ldstQueue.isStalled(tid)) {
785 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
786 ret_val = true;
787 }
788
789 return ret_val;
790}
791
792template <class Impl>
793void
794DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
795{
796 // Check if there's a squash signal, squash if there is
797 // Check stall signals, block if there is.
798 // If status was Blocked
799 // if so then go to unblocking
800 // If status was Squashing
801 // check if squashing is not high. Switch to running this cycle.
802
803 readStallSignals(tid);
804
805 if (fromCommit->commitInfo[tid].squash) {
806 squash(tid);
807
808 if (dispatchStatus[tid] == Blocked ||
809 dispatchStatus[tid] == Unblocking) {
810 toRename->iewUnblock[tid] = true;
811 wroteToTimeBuffer = true;
812 }
813
814 dispatchStatus[tid] = Squashing;
815 fetchRedirect[tid] = false;
816 return;
817 }
818
819 if (fromCommit->commitInfo[tid].robSquashing) {
820 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
821
822 dispatchStatus[tid] = Squashing;
823 emptyRenameInsts(tid);
824 wroteToTimeBuffer = true;
825 return;
826 }
827
828 if (checkStall(tid)) {
829 block(tid);
830 dispatchStatus[tid] = Blocked;
831 return;
832 }
833
834 if (dispatchStatus[tid] == Blocked) {
835 // Status from previous cycle was blocked, but there are no more stall
836 // conditions. Switch over to unblocking.
837 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
838 tid);
839
840 dispatchStatus[tid] = Unblocking;
841
842 unblock(tid);
843
844 return;
845 }
846
847 if (dispatchStatus[tid] == Squashing) {
848 // Switch status to running if rename isn't being told to block or
849 // squash this cycle.
850 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
851 tid);
852
853 dispatchStatus[tid] = Running;
854
855 return;
856 }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::sortInsts()
862{
863 int insts_from_rename = fromRename->size;
864#ifdef DEBUG
865 for (ThreadID tid = 0; tid < numThreads; tid++)
866 assert(insts[tid].empty());
867#endif
868 for (int i = 0; i < insts_from_rename; ++i) {
869 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
870 }
871}
872
873template <class Impl>
874void
875DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
876{
877 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
878
879 while (!insts[tid].empty()) {
880
881 if (insts[tid].front()->isLoad() ||
882 insts[tid].front()->isStore() ) {
883 toRename->iewInfo[tid].dispatchedToLSQ++;
884 }
885
886 toRename->iewInfo[tid].dispatched++;
887
888 insts[tid].pop();
889 }
890}
891
892template <class Impl>
893void
894DefaultIEW<Impl>::wakeCPU()
895{
896 cpu->wakeCPU();
897}
898
899template <class Impl>
900void
901DefaultIEW<Impl>::activityThisCycle()
902{
903 DPRINTF(Activity, "Activity this cycle.\n");
904 cpu->activityThisCycle();
905}
906
907template <class Impl>
908inline void
909DefaultIEW<Impl>::activateStage()
910{
911 DPRINTF(Activity, "Activating stage.\n");
912 cpu->activateStage(O3CPU::IEWIdx);
913}
914
915template <class Impl>
916inline void
917DefaultIEW<Impl>::deactivateStage()
918{
919 DPRINTF(Activity, "Deactivating stage.\n");
920 cpu->deactivateStage(O3CPU::IEWIdx);
921}
922
923template<class Impl>
924void
925DefaultIEW<Impl>::dispatch(ThreadID tid)
926{
927 // If status is Running or idle,
928 // call dispatchInsts()
929 // If status is Unblocking,
930 // buffer any instructions coming from rename
931 // continue trying to empty skid buffer
932 // check if stall conditions have passed
933
934 if (dispatchStatus[tid] == Blocked) {
935 ++iewBlockCycles;
936
937 } else if (dispatchStatus[tid] == Squashing) {
938 ++iewSquashCycles;
939 }
940
941 // Dispatch should try to dispatch as many instructions as its bandwidth
942 // will allow, as long as it is not currently blocked.
943 if (dispatchStatus[tid] == Running ||
944 dispatchStatus[tid] == Idle) {
945 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
946 "dispatch.\n", tid);
947
948 dispatchInsts(tid);
949 } else if (dispatchStatus[tid] == Unblocking) {
950 // Make sure that the skid buffer has something in it if the
951 // status is unblocking.
952 assert(!skidsEmpty());
953
954 // If the status was unblocking, then instructions from the skid
955 // buffer were used. Remove those instructions and handle
956 // the rest of unblocking.
957 dispatchInsts(tid);
958
959 ++iewUnblockCycles;
960
961 if (validInstsFromRename()) {
962 // Add the current inputs to the skid buffer so they can be
963 // reprocessed when this stage unblocks.
964 skidInsert(tid);
965 }
966
967 unblock(tid);
968 }
969}
970
971template <class Impl>
972void
973DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
974{
975 // Obtain instructions from skid buffer if unblocking, or queue from rename
976 // otherwise.
977 std::queue<DynInstPtr> &insts_to_dispatch =
978 dispatchStatus[tid] == Unblocking ?
979 skidBuffer[tid] : insts[tid];
980
981 int insts_to_add = insts_to_dispatch.size();
982
983 DynInstPtr inst;
984 bool add_to_iq = false;
985 int dis_num_inst = 0;
986
987 // Loop through the instructions, putting them in the instruction
988 // queue.
989 for ( ; dis_num_inst < insts_to_add &&
990 dis_num_inst < dispatchWidth;
991 ++dis_num_inst)
992 {
993 inst = insts_to_dispatch.front();
994
995 if (dispatchStatus[tid] == Unblocking) {
996 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
997 "buffer\n", tid);
998 }
999
1000 // Make sure there's a valid instruction there.
1001 assert(inst);
1002
1003 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1004 "IQ.\n",
1005 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1006
1007 // Be sure to mark these instructions as ready so that the
1008 // commit stage can go ahead and execute them, and mark
1009 // them as issued so the IQ doesn't reprocess them.
1010
1011 // Check for squashed instructions.
1012 if (inst->isSquashed()) {
1013 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1014 "not adding to IQ.\n", tid);
1015
1016 ++iewDispSquashedInsts;
1017
1018 insts_to_dispatch.pop();
1019
1020 //Tell Rename That An Instruction has been processed
1021 if (inst->isLoad() || inst->isStore()) {
1022 toRename->iewInfo[tid].dispatchedToLSQ++;
1023 }
1024 toRename->iewInfo[tid].dispatched++;
1025
1026 continue;
1027 }
1028
1029 // Check for full conditions.
1030 if (instQueue.isFull(tid)) {
1031 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1032
1033 // Call function to start blocking.
1034 block(tid);
1035
1036 // Set unblock to false. Special case where we are using
1037 // skidbuffer (unblocking) instructions but then we still
1038 // get full in the IQ.
1039 toRename->iewUnblock[tid] = false;
1040
1041 ++iewIQFullEvents;
1042 break;
1043 } else if (ldstQueue.isFull(tid)) {
1044 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1045
1046 // Call function to start blocking.
1047 block(tid);
1048
1049 // Set unblock to false. Special case where we are using
1050 // skidbuffer (unblocking) instructions but then we still
1051 // get full in the IQ.
1052 toRename->iewUnblock[tid] = false;
1053
1054 ++iewLSQFullEvents;
1055 break;
1056 }
1057
1058 // Otherwise issue the instruction just fine.
1059 if (inst->isLoad()) {
1060 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1061 "encountered, adding to LSQ.\n", tid);
1062
1063 // Reserve a spot in the load store queue for this
1064 // memory access.
1065 ldstQueue.insertLoad(inst);
1066
1067 ++iewDispLoadInsts;
1068
1069 add_to_iq = true;
1070
1071 toRename->iewInfo[tid].dispatchedToLSQ++;
1072 } else if (inst->isStore()) {
1073 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1074 "encountered, adding to LSQ.\n", tid);
1075
1076 ldstQueue.insertStore(inst);
1077
1078 ++iewDispStoreInsts;
1079
1080 if (inst->isStoreConditional()) {
1081 // Store conditionals need to be set as "canCommit()"
1082 // so that commit can process them when they reach the
1083 // head of commit.
1084 // @todo: This is somewhat specific to Alpha.
1085 inst->setCanCommit();
1086 instQueue.insertNonSpec(inst);
1087 add_to_iq = false;
1088
1089 ++iewDispNonSpecInsts;
1090 } else {
1091 add_to_iq = true;
1092 }
1093
1094 toRename->iewInfo[tid].dispatchedToLSQ++;
1095 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1096 // Same as non-speculative stores.
1097 inst->setCanCommit();
1098 instQueue.insertBarrier(inst);
1099 add_to_iq = false;
1100 } else if (inst->isNop()) {
1101 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1102 "skipping.\n", tid);
1103
1104 inst->setIssued();
1105 inst->setExecuted();
1106 inst->setCanCommit();
1107
1108 instQueue.recordProducer(inst);
1109
1110 iewExecutedNop[tid]++;
1111
1112 add_to_iq = false;
1113 } else if (inst->isExecuted()) {
1114 assert(0 && "Instruction shouldn't be executed.\n");
1115 DPRINTF(IEW, "Issue: Executed branch encountered, "
1116 "skipping.\n");
1117
1118 inst->setIssued();
1119 inst->setCanCommit();
1120
1121 instQueue.recordProducer(inst);
1122
1123 add_to_iq = false;
1124 } else {
1125 add_to_iq = true;
1126 }
1127 if (inst->isNonSpeculative()) {
1128 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1129 "encountered, skipping.\n", tid);
1130
1131 // Same as non-speculative stores.
1132 inst->setCanCommit();
1133
1134 // Specifically insert it as nonspeculative.
1135 instQueue.insertNonSpec(inst);
1136
1137 ++iewDispNonSpecInsts;
1138
1139 add_to_iq = false;
1140 }
1141
1142 // If the instruction queue is not full, then add the
1143 // instruction.
1144 if (add_to_iq) {
1145 instQueue.insert(inst);
1146 }
1147
1148 insts_to_dispatch.pop();
1149
1150 toRename->iewInfo[tid].dispatched++;
1151
1152 ++iewDispatchedInsts;
1153
1154#if TRACING_ON
1155 inst->dispatchTick = curTick() - inst->fetchTick;
1156#endif
1157 }
1158
1159 if (!insts_to_dispatch.empty()) {
1160 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1161 block(tid);
1162 toRename->iewUnblock[tid] = false;
1163 }
1164
1165 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1166 dispatchStatus[tid] = Running;
1167
1168 updatedQueues = true;
1169 }
1170
1171 dis_num_inst = 0;
1172}
1173
1174template <class Impl>
1175void
1176DefaultIEW<Impl>::printAvailableInsts()
1177{
1178 int inst = 0;
1179
1180 std::cout << "Available Instructions: ";
1181
1182 while (fromIssue->insts[inst]) {
1183
1184 if (inst%3==0) std::cout << "\n\t";
1185
1186 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1187 << " TN: " << fromIssue->insts[inst]->threadNumber
1188 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1189
1190 inst++;
1191
1192 }
1193
1194 std::cout << "\n";
1195}
1196
1197template <class Impl>
1198void
1199DefaultIEW<Impl>::executeInsts()
1200{
1201 wbNumInst = 0;
1202 wbCycle = 0;
1203
1204 list<ThreadID>::iterator threads = activeThreads->begin();
1205 list<ThreadID>::iterator end = activeThreads->end();
1206
1207 while (threads != end) {
1208 ThreadID tid = *threads++;
1209 fetchRedirect[tid] = false;
1210 }
1211
1212 // Uncomment this if you want to see all available instructions.
1213 // @todo This doesn't actually work anymore, we should fix it.
1214// printAvailableInsts();
1215
1216 // Execute/writeback any instructions that are available.
1217 int insts_to_execute = fromIssue->size;
1218 int inst_num = 0;
1219 for (; inst_num < insts_to_execute;
1220 ++inst_num) {
1221
1222 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1223
1224 DynInstPtr inst = instQueue.getInstToExecute();
1225
1226 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1227 inst->pcState(), inst->threadNumber,inst->seqNum);
1228
1229 // Check if the instruction is squashed; if so then skip it
1230 if (inst->isSquashed()) {
1231 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1232 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1233 inst->seqNum);
1234
1235 // Consider this instruction executed so that commit can go
1236 // ahead and retire the instruction.
1237 inst->setExecuted();
1238
1239 // Not sure if I should set this here or just let commit try to
1240 // commit any squashed instructions. I like the latter a bit more.
1241 inst->setCanCommit();
1242
1243 ++iewExecSquashedInsts;
1244
1245 decrWb(inst->seqNum);
1246 continue;
1247 }
1248
1249 Fault fault = NoFault;
1250
1251 // Execute instruction.
1252 // Note that if the instruction faults, it will be handled
1253 // at the commit stage.
1254 if (inst->isMemRef()) {
1255 DPRINTF(IEW, "Execute: Calculating address for memory "
1256 "reference.\n");
1257
1258 // Tell the LDSTQ to execute this instruction (if it is a load).
1259 if (inst->isLoad()) {
1260 // Loads will mark themselves as executed, and their writeback
1261 // event adds the instruction to the queue to commit
1262 fault = ldstQueue.executeLoad(inst);
1263
1264 if (inst->isTranslationDelayed() &&
1265 fault == NoFault) {
1266 // A hw page table walk is currently going on; the
1267 // instruction must be deferred.
1268 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1269 "load.\n");
1270 instQueue.deferMemInst(inst);
1271 continue;
1272 }
1273
1274 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1275 inst->fault = NoFault;
1276 }
1277 } else if (inst->isStore()) {
1278 fault = ldstQueue.executeStore(inst);
1279
1280 if (inst->isTranslationDelayed() &&
1281 fault == NoFault) {
1282 // A hw page table walk is currently going on; the
1283 // instruction must be deferred.
1284 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1285 "store.\n");
1286 instQueue.deferMemInst(inst);
1287 continue;
1288 }
1289
1290 // If the store had a fault then it may not have a mem req
1291 if (fault != NoFault || inst->readPredicate() == false ||
1292 !inst->isStoreConditional()) {
1293 // If the instruction faulted, then we need to send it along
1294 // to commit without the instruction completing.
1295 // Send this instruction to commit, also make sure iew stage
1296 // realizes there is activity.
1297 inst->setExecuted();
1298 instToCommit(inst);
1299 activityThisCycle();
1300 }
1301
1302 // Store conditionals will mark themselves as
1303 // executed, and their writeback event will add the
1304 // instruction to the queue to commit.
1305 } else {
1306 panic("Unexpected memory type!\n");
1307 }
1308
1309 } else {
1310 // If the instruction has already faulted, then skip executing it.
1311 // Such case can happen when it faulted during ITLB translation.
1312 // If we execute the instruction (even if it's a nop) the fault
1313 // will be replaced and we will lose it.
1314 if (inst->getFault() == NoFault) {
1315 inst->execute();
1316 if (inst->readPredicate() == false)
1317 inst->forwardOldRegs();
1318 }
1319
1320 inst->setExecuted();
1321
1322 instToCommit(inst);
1323 }
1324
1325 updateExeInstStats(inst);
1326
1327 // Check if branch prediction was correct, if not then we need
1328 // to tell commit to squash in flight instructions. Only
1329 // handle this if there hasn't already been something that
1330 // redirects fetch in this group of instructions.
1331
1332 // This probably needs to prioritize the redirects if a different
1333 // scheduler is used. Currently the scheduler schedules the oldest
1334 // instruction first, so the branch resolution order will be correct.
1335 ThreadID tid = inst->threadNumber;
1336
1337 if (!fetchRedirect[tid] ||
1338 !toCommit->squash[tid] ||
1339 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1340
1341 // Prevent testing for misprediction on load instructions,
1342 // that have not been executed.
1343 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1344
1345 if (inst->mispredicted() && !loadNotExecuted) {
1346 fetchRedirect[tid] = true;
1347
1348 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1349 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1350 inst->readPredTarg());
1351 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1352 inst->pcState());
1353 // If incorrect, then signal the ROB that it must be squashed.
1354 squashDueToBranch(inst, tid);
1355
1356 if (inst->readPredTaken()) {
1357 predictedTakenIncorrect++;
1358 } else {
1359 predictedNotTakenIncorrect++;
1360 }
1361 } else if (ldstQueue.violation(tid)) {
1362 assert(inst->isMemRef());
1363 // If there was an ordering violation, then get the
1364 // DynInst that caused the violation. Note that this
1365 // clears the violation signal.
1366 DynInstPtr violator;
1367 violator = ldstQueue.getMemDepViolator(tid);
1368
1369 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1370 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1371 violator->pcState(), violator->seqNum,
1372 inst->pcState(), inst->seqNum, inst->physEffAddr);
1373
1374 fetchRedirect[tid] = true;
1375
1376 // Tell the instruction queue that a violation has occured.
1377 instQueue.violation(inst, violator);
1378
1379 // Squash.
1380 squashDueToMemOrder(violator, tid);
1381
1382 ++memOrderViolationEvents;
1383 } else if (ldstQueue.loadBlocked(tid) &&
1384 !ldstQueue.isLoadBlockedHandled(tid)) {
1385 fetchRedirect[tid] = true;
1386
1387 DPRINTF(IEW, "Load operation couldn't execute because the "
1388 "memory system is blocked. PC: %s [sn:%lli]\n",
1389 inst->pcState(), inst->seqNum);
1390
1391 squashDueToMemBlocked(inst, tid);
1392 }
1393 } else {
1394 // Reset any state associated with redirects that will not
1395 // be used.
1396 if (ldstQueue.violation(tid)) {
1397 assert(inst->isMemRef());
1398
1399 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1400
1401 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1402 "%s, inst PC: %s. Addr is: %#x.\n",
1403 violator->pcState(), inst->pcState(),
1404 inst->physEffAddr);
1405 DPRINTF(IEW, "Violation will not be handled because "
1406 "already squashing\n");
1407
1408 ++memOrderViolationEvents;
1409 }
1410 if (ldstQueue.loadBlocked(tid) &&
1411 !ldstQueue.isLoadBlockedHandled(tid)) {
1412 DPRINTF(IEW, "Load operation couldn't execute because the "
1413 "memory system is blocked. PC: %s [sn:%lli]\n",
1414 inst->pcState(), inst->seqNum);
1415 DPRINTF(IEW, "Blocked load will not be handled because "
1416 "already squashing\n");
1417
1418 ldstQueue.setLoadBlockedHandled(tid);
1419 }
1420
1421 }
1422 }
1423
1424 // Update and record activity if we processed any instructions.
1425 if (inst_num) {
1426 if (exeStatus == Idle) {
1427 exeStatus = Running;
1428 }
1429
1430 updatedQueues = true;
1431
1432 cpu->activityThisCycle();
1433 }
1434
1435 // Need to reset this in case a writeback event needs to write into the
1436 // iew queue. That way the writeback event will write into the correct
1437 // spot in the queue.
1438 wbNumInst = 0;
1439
1440}
1441
1442template <class Impl>
1443void
1444DefaultIEW<Impl>::writebackInsts()
1445{
1446 // Loop through the head of the time buffer and wake any
1447 // dependents. These instructions are about to write back. Also
1448 // mark scoreboard that this instruction is finally complete.
1449 // Either have IEW have direct access to scoreboard, or have this
1450 // as part of backwards communication.
1451 for (int inst_num = 0; inst_num < wbWidth &&
1452 toCommit->insts[inst_num]; inst_num++) {
1453 DynInstPtr inst = toCommit->insts[inst_num];
1454 ThreadID tid = inst->threadNumber;
1455
1456 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1457 inst->seqNum, inst->pcState());
1458
1459 iewInstsToCommit[tid]++;
1460
1461 // Some instructions will be sent to commit without having
1462 // executed because they need commit to handle them.
1463 // E.g. Uncached loads have not actually executed when they
1464 // are first sent to commit. Instead commit must tell the LSQ
1465 // when it's ready to execute the uncached load.
1466 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1467 int dependents = instQueue.wakeDependents(inst);
1468
1469 for (int i = 0; i < inst->numDestRegs(); i++) {
1470 //mark as Ready
1471 DPRINTF(IEW,"Setting Destination Register %i\n",
1472 inst->renamedDestRegIdx(i));
1473 scoreboard->setReg(inst->renamedDestRegIdx(i));
1474 }
1475
1476 if (dependents) {
1477 producerInst[tid]++;
1478 consumerInst[tid]+= dependents;
1479 }
1480 writebackCount[tid]++;
1481 }
1482
1483 decrWb(inst->seqNum);
1484 }
1485}
1486
1487template<class Impl>
1488void
1489DefaultIEW<Impl>::tick()
1490{
1491 wbNumInst = 0;
1492 wbCycle = 0;
1493
1494 wroteToTimeBuffer = false;
1495 updatedQueues = false;
1496
1497 sortInsts();
1498
1499 // Free function units marked as being freed this cycle.
1500 fuPool->processFreeUnits();
1501
1502 list<ThreadID>::iterator threads = activeThreads->begin();
1503 list<ThreadID>::iterator end = activeThreads->end();
1504
1505 // Check stall and squash signals, dispatch any instructions.
1506 while (threads != end) {
1507 ThreadID tid = *threads++;
1508
1509 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1510
1511 checkSignalsAndUpdate(tid);
1512 dispatch(tid);
1513 }
1514
1515 if (exeStatus != Squashing) {
1516 executeInsts();
1517
1518 writebackInsts();
1519
1520 // Have the instruction queue try to schedule any ready instructions.
1521 // (In actuality, this scheduling is for instructions that will
1522 // be executed next cycle.)
1523 instQueue.scheduleReadyInsts();
1524
1525 // Also should advance its own time buffers if the stage ran.
1526 // Not the best place for it, but this works (hopefully).
1527 issueToExecQueue.advance();
1528 }
1529
1530 bool broadcast_free_entries = false;
1531
1532 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1533 exeStatus = Idle;
1534 updateLSQNextCycle = false;
1535
1536 broadcast_free_entries = true;
1537 }
1538
1539 // Writeback any stores using any leftover bandwidth.
1540 ldstQueue.writebackStores();
1541
1542 // Check the committed load/store signals to see if there's a load
1543 // or store to commit. Also check if it's being told to execute a
1544 // nonspeculative instruction.
1545 // This is pretty inefficient...
1546
1547 threads = activeThreads->begin();
1548 while (threads != end) {
1549 ThreadID tid = (*threads++);
1550
1551 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1552
1553 // Update structures based on instructions committed.
1554 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1555 !fromCommit->commitInfo[tid].squash &&
1556 !fromCommit->commitInfo[tid].robSquashing) {
1557
1558 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1559
1560 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1561
1562 updateLSQNextCycle = true;
1563 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1564 }
1565
1566 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1567
1568 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1569 if (fromCommit->commitInfo[tid].uncached) {
1570 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1571 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1572 } else {
1573 instQueue.scheduleNonSpec(
1574 fromCommit->commitInfo[tid].nonSpecSeqNum);
1575 }
1576 }
1577
1578 if (broadcast_free_entries) {
1579 toFetch->iewInfo[tid].iqCount =
1580 instQueue.getCount(tid);
1581 toFetch->iewInfo[tid].ldstqCount =
1582 ldstQueue.getCount(tid);
1583
1584 toRename->iewInfo[tid].usedIQ = true;
1585 toRename->iewInfo[tid].freeIQEntries =
1586 instQueue.numFreeEntries();
1587 toRename->iewInfo[tid].usedLSQ = true;
1588 toRename->iewInfo[tid].freeLSQEntries =
1589 ldstQueue.numFreeEntries(tid);
1590
1591 wroteToTimeBuffer = true;
1592 }
1593
1594 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1595 tid, toRename->iewInfo[tid].dispatched);
1596 }
1597
1598 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1599 "LSQ has %i free entries.\n",
1600 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1601 ldstQueue.numFreeEntries());
1602
1603 updateStatus();
1604
1605 if (wroteToTimeBuffer) {
1606 DPRINTF(Activity, "Activity this cycle.\n");
1607 cpu->activityThisCycle();
1608 }
1609}
1610
1611template <class Impl>
1612void
1613DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1614{
1615 ThreadID tid = inst->threadNumber;
1616
1617 iewExecutedInsts++;
1618
1619#if TRACING_ON
1620 inst->completeTick = curTick() - inst->fetchTick;
1621#endif
1622
1623 //
1624 // Control operations
1625 //
1626 if (inst->isControl())
1627 iewExecutedBranches[tid]++;
1628
1629 //
1630 // Memory operations
1631 //
1632 if (inst->isMemRef()) {
1633 iewExecutedRefs[tid]++;
1634
1635 if (inst->isLoad()) {
1636 iewExecLoadInsts[tid]++;
1637 }
1638 }
1639}
1640
1641template <class Impl>
1642void
1643DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1644{
1645 ThreadID tid = inst->threadNumber;
1646
1647 if (!fetchRedirect[tid] ||
1648 !toCommit->squash[tid] ||
1649 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1650
1651 if (inst->mispredicted()) {
1652 fetchRedirect[tid] = true;
1653
1654 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1655 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1656 inst->predInstAddr(), inst->predNextInstAddr());
1657 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1658 " NPC: %#x.\n", inst->nextInstAddr(),
1659 inst->nextInstAddr());
1660 // If incorrect, then signal the ROB that it must be squashed.
1661 squashDueToBranch(inst, tid);
1662
1663 if (inst->readPredTaken()) {
1664 predictedTakenIncorrect++;
1665 } else {
1666 predictedNotTakenIncorrect++;
1667 }
1668 }
1669 }
1670}
| 404
405 startupStage();
406 cpu->activityThisCycle();
407
408 for (ThreadID tid = 0; tid < numThreads; tid++) {
409 dispatchStatus[tid] = Running;
410 stalls[tid].commit = false;
411 fetchRedirect[tid] = false;
412 }
413
414 updateLSQNextCycle = false;
415
416 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
417 issueToExecQueue.advance();
418 }
419}
420
421template<class Impl>
422void
423DefaultIEW<Impl>::squash(ThreadID tid)
424{
425 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432 updatedQueues = true;
433
434 // Clear the skid buffer in case it has any data in it.
435 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
436 tid, fromCommit->commitInfo[tid].doneSeqNum);
437
438 while (!skidBuffer[tid].empty()) {
439 if (skidBuffer[tid].front()->isLoad() ||
440 skidBuffer[tid].front()->isStore() ) {
441 toRename->iewInfo[tid].dispatchedToLSQ++;
442 }
443
444 toRename->iewInfo[tid].dispatched++;
445
446 skidBuffer[tid].pop();
447 }
448
449 emptyRenameInsts(tid);
450}
451
452template<class Impl>
453void
454DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
455{
456 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
457 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
458
459 if (toCommit->squash[tid] == false ||
460 inst->seqNum < toCommit->squashedSeqNum[tid]) {
461 toCommit->squash[tid] = true;
462 toCommit->squashedSeqNum[tid] = inst->seqNum;
463 toCommit->branchTaken[tid] = inst->pcState().branching();
464
465 TheISA::PCState pc = inst->pcState();
466 TheISA::advancePC(pc, inst->staticInst);
467
468 toCommit->pc[tid] = pc;
469 toCommit->mispredictInst[tid] = inst;
470 toCommit->includeSquashInst[tid] = false;
471
472 wroteToTimeBuffer = true;
473 }
474
475}
476
477template<class Impl>
478void
479DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
480{
481 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
482 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
483 // Need to include inst->seqNum in the following comparison to cover the
484 // corner case when a branch misprediction and a memory violation for the
485 // same instruction (e.g. load PC) are detected in the same cycle. In this
486 // case the memory violator should take precedence over the branch
487 // misprediction because it requires the violator itself to be included in
488 // the squash.
489 if (toCommit->squash[tid] == false ||
490 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
491 toCommit->squash[tid] = true;
492
493 toCommit->squashedSeqNum[tid] = inst->seqNum;
494 toCommit->pc[tid] = inst->pcState();
495 toCommit->mispredictInst[tid] = NULL;
496
497 // Must include the memory violator in the squash.
498 toCommit->includeSquashInst[tid] = true;
499
500 wroteToTimeBuffer = true;
501 }
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
507{
508 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
509 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
510 if (toCommit->squash[tid] == false ||
511 inst->seqNum < toCommit->squashedSeqNum[tid]) {
512 toCommit->squash[tid] = true;
513
514 toCommit->squashedSeqNum[tid] = inst->seqNum;
515 toCommit->pc[tid] = inst->pcState();
516 toCommit->mispredictInst[tid] = NULL;
517
518 // Must include the broadcasted SN in the squash.
519 toCommit->includeSquashInst[tid] = true;
520
521 ldstQueue.setLoadBlockedHandled(tid);
522
523 wroteToTimeBuffer = true;
524 }
525}
526
527template<class Impl>
528void
529DefaultIEW<Impl>::block(ThreadID tid)
530{
531 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
532
533 if (dispatchStatus[tid] != Blocked &&
534 dispatchStatus[tid] != Unblocking) {
535 toRename->iewBlock[tid] = true;
536 wroteToTimeBuffer = true;
537 }
538
539 // Add the current inputs to the skid buffer so they can be
540 // reprocessed when this stage unblocks.
541 skidInsert(tid);
542
543 dispatchStatus[tid] = Blocked;
544}
545
546template<class Impl>
547void
548DefaultIEW<Impl>::unblock(ThreadID tid)
549{
550 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
551 "buffer %u.\n",tid, tid);
552
553 // If the skid bufffer is empty, signal back to previous stages to unblock.
554 // Also switch status to running.
555 if (skidBuffer[tid].empty()) {
556 toRename->iewUnblock[tid] = true;
557 wroteToTimeBuffer = true;
558 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
559 dispatchStatus[tid] = Running;
560 }
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
566{
567 instQueue.wakeDependents(inst);
568}
569
570template<class Impl>
571void
572DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
573{
574 instQueue.rescheduleMemInst(inst);
575}
576
577template<class Impl>
578void
579DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
580{
581 instQueue.replayMemInst(inst);
582}
583
584template<class Impl>
585void
586DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
587{
588 // This function should not be called after writebackInsts in a
589 // single cycle. That will cause problems with an instruction
590 // being added to the queue to commit without being processed by
591 // writebackInsts prior to being sent to commit.
592
593 // First check the time slot that this instruction will write
594 // to. If there are free write ports at the time, then go ahead
595 // and write the instruction to that time. If there are not,
596 // keep looking back to see where's the first time there's a
597 // free slot.
598 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
599 ++wbNumInst;
600 if (wbNumInst == wbWidth) {
601 ++wbCycle;
602 wbNumInst = 0;
603 }
604
605 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
606 }
607
608 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
609 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
610 // Add finished instruction to queue to commit.
611 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
612 (*iewQueue)[wbCycle].size++;
613}
614
615template <class Impl>
616unsigned
617DefaultIEW<Impl>::validInstsFromRename()
618{
619 unsigned inst_count = 0;
620
621 for (int i=0; i<fromRename->size; i++) {
622 if (!fromRename->insts[i]->isSquashed())
623 inst_count++;
624 }
625
626 return inst_count;
627}
628
629template<class Impl>
630void
631DefaultIEW<Impl>::skidInsert(ThreadID tid)
632{
633 DynInstPtr inst = NULL;
634
635 while (!insts[tid].empty()) {
636 inst = insts[tid].front();
637
638 insts[tid].pop();
639
640 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
641 "dispatch skidBuffer %i\n",tid, inst->seqNum,
642 inst->pcState(),tid);
643
644 skidBuffer[tid].push(inst);
645 }
646
647 assert(skidBuffer[tid].size() <= skidBufferMax &&
648 "Skidbuffer Exceeded Max Size");
649}
650
651template<class Impl>
652int
653DefaultIEW<Impl>::skidCount()
654{
655 int max=0;
656
657 list<ThreadID>::iterator threads = activeThreads->begin();
658 list<ThreadID>::iterator end = activeThreads->end();
659
660 while (threads != end) {
661 ThreadID tid = *threads++;
662 unsigned thread_count = skidBuffer[tid].size();
663 if (max < thread_count)
664 max = thread_count;
665 }
666
667 return max;
668}
669
670template<class Impl>
671bool
672DefaultIEW<Impl>::skidsEmpty()
673{
674 list<ThreadID>::iterator threads = activeThreads->begin();
675 list<ThreadID>::iterator end = activeThreads->end();
676
677 while (threads != end) {
678 ThreadID tid = *threads++;
679
680 if (!skidBuffer[tid].empty())
681 return false;
682 }
683
684 return true;
685}
686
687template <class Impl>
688void
689DefaultIEW<Impl>::updateStatus()
690{
691 bool any_unblocking = false;
692
693 list<ThreadID>::iterator threads = activeThreads->begin();
694 list<ThreadID>::iterator end = activeThreads->end();
695
696 while (threads != end) {
697 ThreadID tid = *threads++;
698
699 if (dispatchStatus[tid] == Unblocking) {
700 any_unblocking = true;
701 break;
702 }
703 }
704
705 // If there are no ready instructions waiting to be scheduled by the IQ,
706 // and there's no stores waiting to write back, and dispatch is not
707 // unblocking, then there is no internal activity for the IEW stage.
708 instQueue.intInstQueueReads++;
709 if (_status == Active && !instQueue.hasReadyInsts() &&
710 !ldstQueue.willWB() && !any_unblocking) {
711 DPRINTF(IEW, "IEW switching to idle\n");
712
713 deactivateStage();
714
715 _status = Inactive;
716 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
717 ldstQueue.willWB() ||
718 any_unblocking)) {
719 // Otherwise there is internal activity. Set to active.
720 DPRINTF(IEW, "IEW switching to active\n");
721
722 activateStage();
723
724 _status = Active;
725 }
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::resetEntries()
731{
732 instQueue.resetEntries();
733 ldstQueue.resetEntries();
734}
735
736template <class Impl>
737void
738DefaultIEW<Impl>::readStallSignals(ThreadID tid)
739{
740 if (fromCommit->commitBlock[tid]) {
741 stalls[tid].commit = true;
742 }
743
744 if (fromCommit->commitUnblock[tid]) {
745 assert(stalls[tid].commit);
746 stalls[tid].commit = false;
747 }
748}
749
750template <class Impl>
751bool
752DefaultIEW<Impl>::checkStall(ThreadID tid)
753{
754 bool ret_val(false);
755
756 if (stalls[tid].commit) {
757 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
758 ret_val = true;
759 } else if (instQueue.isFull(tid)) {
760 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
761 ret_val = true;
762 } else if (ldstQueue.isFull(tid)) {
763 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
764
765 if (ldstQueue.numLoads(tid) > 0 ) {
766
767 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
768 tid,ldstQueue.getLoadHeadSeqNum(tid));
769 }
770
771 if (ldstQueue.numStores(tid) > 0) {
772
773 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
774 tid,ldstQueue.getStoreHeadSeqNum(tid));
775 }
776
777 ret_val = true;
778 } else if (ldstQueue.isStalled(tid)) {
779 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
780 ret_val = true;
781 }
782
783 return ret_val;
784}
785
786template <class Impl>
787void
788DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
789{
790 // Check if there's a squash signal, squash if there is
791 // Check stall signals, block if there is.
792 // If status was Blocked
793 // if so then go to unblocking
794 // If status was Squashing
795 // check if squashing is not high. Switch to running this cycle.
796
797 readStallSignals(tid);
798
799 if (fromCommit->commitInfo[tid].squash) {
800 squash(tid);
801
802 if (dispatchStatus[tid] == Blocked ||
803 dispatchStatus[tid] == Unblocking) {
804 toRename->iewUnblock[tid] = true;
805 wroteToTimeBuffer = true;
806 }
807
808 dispatchStatus[tid] = Squashing;
809 fetchRedirect[tid] = false;
810 return;
811 }
812
813 if (fromCommit->commitInfo[tid].robSquashing) {
814 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
815
816 dispatchStatus[tid] = Squashing;
817 emptyRenameInsts(tid);
818 wroteToTimeBuffer = true;
819 return;
820 }
821
822 if (checkStall(tid)) {
823 block(tid);
824 dispatchStatus[tid] = Blocked;
825 return;
826 }
827
828 if (dispatchStatus[tid] == Blocked) {
829 // Status from previous cycle was blocked, but there are no more stall
830 // conditions. Switch over to unblocking.
831 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
832 tid);
833
834 dispatchStatus[tid] = Unblocking;
835
836 unblock(tid);
837
838 return;
839 }
840
841 if (dispatchStatus[tid] == Squashing) {
842 // Switch status to running if rename isn't being told to block or
843 // squash this cycle.
844 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
845 tid);
846
847 dispatchStatus[tid] = Running;
848
849 return;
850 }
851}
852
853template <class Impl>
854void
855DefaultIEW<Impl>::sortInsts()
856{
857 int insts_from_rename = fromRename->size;
858#ifdef DEBUG
859 for (ThreadID tid = 0; tid < numThreads; tid++)
860 assert(insts[tid].empty());
861#endif
862 for (int i = 0; i < insts_from_rename; ++i) {
863 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
864 }
865}
866
867template <class Impl>
868void
869DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
870{
871 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
872
873 while (!insts[tid].empty()) {
874
875 if (insts[tid].front()->isLoad() ||
876 insts[tid].front()->isStore() ) {
877 toRename->iewInfo[tid].dispatchedToLSQ++;
878 }
879
880 toRename->iewInfo[tid].dispatched++;
881
882 insts[tid].pop();
883 }
884}
885
886template <class Impl>
887void
888DefaultIEW<Impl>::wakeCPU()
889{
890 cpu->wakeCPU();
891}
892
893template <class Impl>
894void
895DefaultIEW<Impl>::activityThisCycle()
896{
897 DPRINTF(Activity, "Activity this cycle.\n");
898 cpu->activityThisCycle();
899}
900
901template <class Impl>
902inline void
903DefaultIEW<Impl>::activateStage()
904{
905 DPRINTF(Activity, "Activating stage.\n");
906 cpu->activateStage(O3CPU::IEWIdx);
907}
908
909template <class Impl>
910inline void
911DefaultIEW<Impl>::deactivateStage()
912{
913 DPRINTF(Activity, "Deactivating stage.\n");
914 cpu->deactivateStage(O3CPU::IEWIdx);
915}
916
917template<class Impl>
918void
919DefaultIEW<Impl>::dispatch(ThreadID tid)
920{
921 // If status is Running or idle,
922 // call dispatchInsts()
923 // If status is Unblocking,
924 // buffer any instructions coming from rename
925 // continue trying to empty skid buffer
926 // check if stall conditions have passed
927
928 if (dispatchStatus[tid] == Blocked) {
929 ++iewBlockCycles;
930
931 } else if (dispatchStatus[tid] == Squashing) {
932 ++iewSquashCycles;
933 }
934
935 // Dispatch should try to dispatch as many instructions as its bandwidth
936 // will allow, as long as it is not currently blocked.
937 if (dispatchStatus[tid] == Running ||
938 dispatchStatus[tid] == Idle) {
939 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
940 "dispatch.\n", tid);
941
942 dispatchInsts(tid);
943 } else if (dispatchStatus[tid] == Unblocking) {
944 // Make sure that the skid buffer has something in it if the
945 // status is unblocking.
946 assert(!skidsEmpty());
947
948 // If the status was unblocking, then instructions from the skid
949 // buffer were used. Remove those instructions and handle
950 // the rest of unblocking.
951 dispatchInsts(tid);
952
953 ++iewUnblockCycles;
954
955 if (validInstsFromRename()) {
956 // Add the current inputs to the skid buffer so they can be
957 // reprocessed when this stage unblocks.
958 skidInsert(tid);
959 }
960
961 unblock(tid);
962 }
963}
964
965template <class Impl>
966void
967DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
968{
969 // Obtain instructions from skid buffer if unblocking, or queue from rename
970 // otherwise.
971 std::queue<DynInstPtr> &insts_to_dispatch =
972 dispatchStatus[tid] == Unblocking ?
973 skidBuffer[tid] : insts[tid];
974
975 int insts_to_add = insts_to_dispatch.size();
976
977 DynInstPtr inst;
978 bool add_to_iq = false;
979 int dis_num_inst = 0;
980
981 // Loop through the instructions, putting them in the instruction
982 // queue.
983 for ( ; dis_num_inst < insts_to_add &&
984 dis_num_inst < dispatchWidth;
985 ++dis_num_inst)
986 {
987 inst = insts_to_dispatch.front();
988
989 if (dispatchStatus[tid] == Unblocking) {
990 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
991 "buffer\n", tid);
992 }
993
994 // Make sure there's a valid instruction there.
995 assert(inst);
996
997 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
998 "IQ.\n",
999 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1000
1001 // Be sure to mark these instructions as ready so that the
1002 // commit stage can go ahead and execute them, and mark
1003 // them as issued so the IQ doesn't reprocess them.
1004
1005 // Check for squashed instructions.
1006 if (inst->isSquashed()) {
1007 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1008 "not adding to IQ.\n", tid);
1009
1010 ++iewDispSquashedInsts;
1011
1012 insts_to_dispatch.pop();
1013
1014 //Tell Rename That An Instruction has been processed
1015 if (inst->isLoad() || inst->isStore()) {
1016 toRename->iewInfo[tid].dispatchedToLSQ++;
1017 }
1018 toRename->iewInfo[tid].dispatched++;
1019
1020 continue;
1021 }
1022
1023 // Check for full conditions.
1024 if (instQueue.isFull(tid)) {
1025 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1026
1027 // Call function to start blocking.
1028 block(tid);
1029
1030 // Set unblock to false. Special case where we are using
1031 // skidbuffer (unblocking) instructions but then we still
1032 // get full in the IQ.
1033 toRename->iewUnblock[tid] = false;
1034
1035 ++iewIQFullEvents;
1036 break;
1037 } else if (ldstQueue.isFull(tid)) {
1038 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1039
1040 // Call function to start blocking.
1041 block(tid);
1042
1043 // Set unblock to false. Special case where we are using
1044 // skidbuffer (unblocking) instructions but then we still
1045 // get full in the IQ.
1046 toRename->iewUnblock[tid] = false;
1047
1048 ++iewLSQFullEvents;
1049 break;
1050 }
1051
1052 // Otherwise issue the instruction just fine.
1053 if (inst->isLoad()) {
1054 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1055 "encountered, adding to LSQ.\n", tid);
1056
1057 // Reserve a spot in the load store queue for this
1058 // memory access.
1059 ldstQueue.insertLoad(inst);
1060
1061 ++iewDispLoadInsts;
1062
1063 add_to_iq = true;
1064
1065 toRename->iewInfo[tid].dispatchedToLSQ++;
1066 } else if (inst->isStore()) {
1067 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1068 "encountered, adding to LSQ.\n", tid);
1069
1070 ldstQueue.insertStore(inst);
1071
1072 ++iewDispStoreInsts;
1073
1074 if (inst->isStoreConditional()) {
1075 // Store conditionals need to be set as "canCommit()"
1076 // so that commit can process them when they reach the
1077 // head of commit.
1078 // @todo: This is somewhat specific to Alpha.
1079 inst->setCanCommit();
1080 instQueue.insertNonSpec(inst);
1081 add_to_iq = false;
1082
1083 ++iewDispNonSpecInsts;
1084 } else {
1085 add_to_iq = true;
1086 }
1087
1088 toRename->iewInfo[tid].dispatchedToLSQ++;
1089 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1090 // Same as non-speculative stores.
1091 inst->setCanCommit();
1092 instQueue.insertBarrier(inst);
1093 add_to_iq = false;
1094 } else if (inst->isNop()) {
1095 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1096 "skipping.\n", tid);
1097
1098 inst->setIssued();
1099 inst->setExecuted();
1100 inst->setCanCommit();
1101
1102 instQueue.recordProducer(inst);
1103
1104 iewExecutedNop[tid]++;
1105
1106 add_to_iq = false;
1107 } else if (inst->isExecuted()) {
1108 assert(0 && "Instruction shouldn't be executed.\n");
1109 DPRINTF(IEW, "Issue: Executed branch encountered, "
1110 "skipping.\n");
1111
1112 inst->setIssued();
1113 inst->setCanCommit();
1114
1115 instQueue.recordProducer(inst);
1116
1117 add_to_iq = false;
1118 } else {
1119 add_to_iq = true;
1120 }
1121 if (inst->isNonSpeculative()) {
1122 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1123 "encountered, skipping.\n", tid);
1124
1125 // Same as non-speculative stores.
1126 inst->setCanCommit();
1127
1128 // Specifically insert it as nonspeculative.
1129 instQueue.insertNonSpec(inst);
1130
1131 ++iewDispNonSpecInsts;
1132
1133 add_to_iq = false;
1134 }
1135
1136 // If the instruction queue is not full, then add the
1137 // instruction.
1138 if (add_to_iq) {
1139 instQueue.insert(inst);
1140 }
1141
1142 insts_to_dispatch.pop();
1143
1144 toRename->iewInfo[tid].dispatched++;
1145
1146 ++iewDispatchedInsts;
1147
1148#if TRACING_ON
1149 inst->dispatchTick = curTick() - inst->fetchTick;
1150#endif
1151 }
1152
1153 if (!insts_to_dispatch.empty()) {
1154 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1155 block(tid);
1156 toRename->iewUnblock[tid] = false;
1157 }
1158
1159 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1160 dispatchStatus[tid] = Running;
1161
1162 updatedQueues = true;
1163 }
1164
1165 dis_num_inst = 0;
1166}
1167
1168template <class Impl>
1169void
1170DefaultIEW<Impl>::printAvailableInsts()
1171{
1172 int inst = 0;
1173
1174 std::cout << "Available Instructions: ";
1175
1176 while (fromIssue->insts[inst]) {
1177
1178 if (inst%3==0) std::cout << "\n\t";
1179
1180 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1181 << " TN: " << fromIssue->insts[inst]->threadNumber
1182 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1183
1184 inst++;
1185
1186 }
1187
1188 std::cout << "\n";
1189}
1190
1191template <class Impl>
1192void
1193DefaultIEW<Impl>::executeInsts()
1194{
1195 wbNumInst = 0;
1196 wbCycle = 0;
1197
1198 list<ThreadID>::iterator threads = activeThreads->begin();
1199 list<ThreadID>::iterator end = activeThreads->end();
1200
1201 while (threads != end) {
1202 ThreadID tid = *threads++;
1203 fetchRedirect[tid] = false;
1204 }
1205
1206 // Uncomment this if you want to see all available instructions.
1207 // @todo This doesn't actually work anymore, we should fix it.
1208// printAvailableInsts();
1209
1210 // Execute/writeback any instructions that are available.
1211 int insts_to_execute = fromIssue->size;
1212 int inst_num = 0;
1213 for (; inst_num < insts_to_execute;
1214 ++inst_num) {
1215
1216 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1217
1218 DynInstPtr inst = instQueue.getInstToExecute();
1219
1220 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1221 inst->pcState(), inst->threadNumber,inst->seqNum);
1222
1223 // Check if the instruction is squashed; if so then skip it
1224 if (inst->isSquashed()) {
1225 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1226 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1227 inst->seqNum);
1228
1229 // Consider this instruction executed so that commit can go
1230 // ahead and retire the instruction.
1231 inst->setExecuted();
1232
1233 // Not sure if I should set this here or just let commit try to
1234 // commit any squashed instructions. I like the latter a bit more.
1235 inst->setCanCommit();
1236
1237 ++iewExecSquashedInsts;
1238
1239 decrWb(inst->seqNum);
1240 continue;
1241 }
1242
1243 Fault fault = NoFault;
1244
1245 // Execute instruction.
1246 // Note that if the instruction faults, it will be handled
1247 // at the commit stage.
1248 if (inst->isMemRef()) {
1249 DPRINTF(IEW, "Execute: Calculating address for memory "
1250 "reference.\n");
1251
1252 // Tell the LDSTQ to execute this instruction (if it is a load).
1253 if (inst->isLoad()) {
1254 // Loads will mark themselves as executed, and their writeback
1255 // event adds the instruction to the queue to commit
1256 fault = ldstQueue.executeLoad(inst);
1257
1258 if (inst->isTranslationDelayed() &&
1259 fault == NoFault) {
1260 // A hw page table walk is currently going on; the
1261 // instruction must be deferred.
1262 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1263 "load.\n");
1264 instQueue.deferMemInst(inst);
1265 continue;
1266 }
1267
1268 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1269 inst->fault = NoFault;
1270 }
1271 } else if (inst->isStore()) {
1272 fault = ldstQueue.executeStore(inst);
1273
1274 if (inst->isTranslationDelayed() &&
1275 fault == NoFault) {
1276 // A hw page table walk is currently going on; the
1277 // instruction must be deferred.
1278 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1279 "store.\n");
1280 instQueue.deferMemInst(inst);
1281 continue;
1282 }
1283
1284 // If the store had a fault then it may not have a mem req
1285 if (fault != NoFault || inst->readPredicate() == false ||
1286 !inst->isStoreConditional()) {
1287 // If the instruction faulted, then we need to send it along
1288 // to commit without the instruction completing.
1289 // Send this instruction to commit, also make sure iew stage
1290 // realizes there is activity.
1291 inst->setExecuted();
1292 instToCommit(inst);
1293 activityThisCycle();
1294 }
1295
1296 // Store conditionals will mark themselves as
1297 // executed, and their writeback event will add the
1298 // instruction to the queue to commit.
1299 } else {
1300 panic("Unexpected memory type!\n");
1301 }
1302
1303 } else {
1304 // If the instruction has already faulted, then skip executing it.
1305 // Such case can happen when it faulted during ITLB translation.
1306 // If we execute the instruction (even if it's a nop) the fault
1307 // will be replaced and we will lose it.
1308 if (inst->getFault() == NoFault) {
1309 inst->execute();
1310 if (inst->readPredicate() == false)
1311 inst->forwardOldRegs();
1312 }
1313
1314 inst->setExecuted();
1315
1316 instToCommit(inst);
1317 }
1318
1319 updateExeInstStats(inst);
1320
1321 // Check if branch prediction was correct, if not then we need
1322 // to tell commit to squash in flight instructions. Only
1323 // handle this if there hasn't already been something that
1324 // redirects fetch in this group of instructions.
1325
1326 // This probably needs to prioritize the redirects if a different
1327 // scheduler is used. Currently the scheduler schedules the oldest
1328 // instruction first, so the branch resolution order will be correct.
1329 ThreadID tid = inst->threadNumber;
1330
1331 if (!fetchRedirect[tid] ||
1332 !toCommit->squash[tid] ||
1333 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1334
1335 // Prevent testing for misprediction on load instructions,
1336 // that have not been executed.
1337 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1338
1339 if (inst->mispredicted() && !loadNotExecuted) {
1340 fetchRedirect[tid] = true;
1341
1342 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1343 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1344 inst->readPredTarg());
1345 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1346 inst->pcState());
1347 // If incorrect, then signal the ROB that it must be squashed.
1348 squashDueToBranch(inst, tid);
1349
1350 if (inst->readPredTaken()) {
1351 predictedTakenIncorrect++;
1352 } else {
1353 predictedNotTakenIncorrect++;
1354 }
1355 } else if (ldstQueue.violation(tid)) {
1356 assert(inst->isMemRef());
1357 // If there was an ordering violation, then get the
1358 // DynInst that caused the violation. Note that this
1359 // clears the violation signal.
1360 DynInstPtr violator;
1361 violator = ldstQueue.getMemDepViolator(tid);
1362
1363 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1364 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1365 violator->pcState(), violator->seqNum,
1366 inst->pcState(), inst->seqNum, inst->physEffAddr);
1367
1368 fetchRedirect[tid] = true;
1369
1370 // Tell the instruction queue that a violation has occured.
1371 instQueue.violation(inst, violator);
1372
1373 // Squash.
1374 squashDueToMemOrder(violator, tid);
1375
1376 ++memOrderViolationEvents;
1377 } else if (ldstQueue.loadBlocked(tid) &&
1378 !ldstQueue.isLoadBlockedHandled(tid)) {
1379 fetchRedirect[tid] = true;
1380
1381 DPRINTF(IEW, "Load operation couldn't execute because the "
1382 "memory system is blocked. PC: %s [sn:%lli]\n",
1383 inst->pcState(), inst->seqNum);
1384
1385 squashDueToMemBlocked(inst, tid);
1386 }
1387 } else {
1388 // Reset any state associated with redirects that will not
1389 // be used.
1390 if (ldstQueue.violation(tid)) {
1391 assert(inst->isMemRef());
1392
1393 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1394
1395 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1396 "%s, inst PC: %s. Addr is: %#x.\n",
1397 violator->pcState(), inst->pcState(),
1398 inst->physEffAddr);
1399 DPRINTF(IEW, "Violation will not be handled because "
1400 "already squashing\n");
1401
1402 ++memOrderViolationEvents;
1403 }
1404 if (ldstQueue.loadBlocked(tid) &&
1405 !ldstQueue.isLoadBlockedHandled(tid)) {
1406 DPRINTF(IEW, "Load operation couldn't execute because the "
1407 "memory system is blocked. PC: %s [sn:%lli]\n",
1408 inst->pcState(), inst->seqNum);
1409 DPRINTF(IEW, "Blocked load will not be handled because "
1410 "already squashing\n");
1411
1412 ldstQueue.setLoadBlockedHandled(tid);
1413 }
1414
1415 }
1416 }
1417
1418 // Update and record activity if we processed any instructions.
1419 if (inst_num) {
1420 if (exeStatus == Idle) {
1421 exeStatus = Running;
1422 }
1423
1424 updatedQueues = true;
1425
1426 cpu->activityThisCycle();
1427 }
1428
1429 // Need to reset this in case a writeback event needs to write into the
1430 // iew queue. That way the writeback event will write into the correct
1431 // spot in the queue.
1432 wbNumInst = 0;
1433
1434}
1435
1436template <class Impl>
1437void
1438DefaultIEW<Impl>::writebackInsts()
1439{
1440 // Loop through the head of the time buffer and wake any
1441 // dependents. These instructions are about to write back. Also
1442 // mark scoreboard that this instruction is finally complete.
1443 // Either have IEW have direct access to scoreboard, or have this
1444 // as part of backwards communication.
1445 for (int inst_num = 0; inst_num < wbWidth &&
1446 toCommit->insts[inst_num]; inst_num++) {
1447 DynInstPtr inst = toCommit->insts[inst_num];
1448 ThreadID tid = inst->threadNumber;
1449
1450 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1451 inst->seqNum, inst->pcState());
1452
1453 iewInstsToCommit[tid]++;
1454
1455 // Some instructions will be sent to commit without having
1456 // executed because they need commit to handle them.
1457 // E.g. Uncached loads have not actually executed when they
1458 // are first sent to commit. Instead commit must tell the LSQ
1459 // when it's ready to execute the uncached load.
1460 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1461 int dependents = instQueue.wakeDependents(inst);
1462
1463 for (int i = 0; i < inst->numDestRegs(); i++) {
1464 //mark as Ready
1465 DPRINTF(IEW,"Setting Destination Register %i\n",
1466 inst->renamedDestRegIdx(i));
1467 scoreboard->setReg(inst->renamedDestRegIdx(i));
1468 }
1469
1470 if (dependents) {
1471 producerInst[tid]++;
1472 consumerInst[tid]+= dependents;
1473 }
1474 writebackCount[tid]++;
1475 }
1476
1477 decrWb(inst->seqNum);
1478 }
1479}
1480
1481template<class Impl>
1482void
1483DefaultIEW<Impl>::tick()
1484{
1485 wbNumInst = 0;
1486 wbCycle = 0;
1487
1488 wroteToTimeBuffer = false;
1489 updatedQueues = false;
1490
1491 sortInsts();
1492
1493 // Free function units marked as being freed this cycle.
1494 fuPool->processFreeUnits();
1495
1496 list<ThreadID>::iterator threads = activeThreads->begin();
1497 list<ThreadID>::iterator end = activeThreads->end();
1498
1499 // Check stall and squash signals, dispatch any instructions.
1500 while (threads != end) {
1501 ThreadID tid = *threads++;
1502
1503 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1504
1505 checkSignalsAndUpdate(tid);
1506 dispatch(tid);
1507 }
1508
1509 if (exeStatus != Squashing) {
1510 executeInsts();
1511
1512 writebackInsts();
1513
1514 // Have the instruction queue try to schedule any ready instructions.
1515 // (In actuality, this scheduling is for instructions that will
1516 // be executed next cycle.)
1517 instQueue.scheduleReadyInsts();
1518
1519 // Also should advance its own time buffers if the stage ran.
1520 // Not the best place for it, but this works (hopefully).
1521 issueToExecQueue.advance();
1522 }
1523
1524 bool broadcast_free_entries = false;
1525
1526 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1527 exeStatus = Idle;
1528 updateLSQNextCycle = false;
1529
1530 broadcast_free_entries = true;
1531 }
1532
1533 // Writeback any stores using any leftover bandwidth.
1534 ldstQueue.writebackStores();
1535
1536 // Check the committed load/store signals to see if there's a load
1537 // or store to commit. Also check if it's being told to execute a
1538 // nonspeculative instruction.
1539 // This is pretty inefficient...
1540
1541 threads = activeThreads->begin();
1542 while (threads != end) {
1543 ThreadID tid = (*threads++);
1544
1545 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1546
1547 // Update structures based on instructions committed.
1548 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1549 !fromCommit->commitInfo[tid].squash &&
1550 !fromCommit->commitInfo[tid].robSquashing) {
1551
1552 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1553
1554 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1555
1556 updateLSQNextCycle = true;
1557 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1558 }
1559
1560 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1561
1562 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1563 if (fromCommit->commitInfo[tid].uncached) {
1564 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1565 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1566 } else {
1567 instQueue.scheduleNonSpec(
1568 fromCommit->commitInfo[tid].nonSpecSeqNum);
1569 }
1570 }
1571
1572 if (broadcast_free_entries) {
1573 toFetch->iewInfo[tid].iqCount =
1574 instQueue.getCount(tid);
1575 toFetch->iewInfo[tid].ldstqCount =
1576 ldstQueue.getCount(tid);
1577
1578 toRename->iewInfo[tid].usedIQ = true;
1579 toRename->iewInfo[tid].freeIQEntries =
1580 instQueue.numFreeEntries();
1581 toRename->iewInfo[tid].usedLSQ = true;
1582 toRename->iewInfo[tid].freeLSQEntries =
1583 ldstQueue.numFreeEntries(tid);
1584
1585 wroteToTimeBuffer = true;
1586 }
1587
1588 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1589 tid, toRename->iewInfo[tid].dispatched);
1590 }
1591
1592 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1593 "LSQ has %i free entries.\n",
1594 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1595 ldstQueue.numFreeEntries());
1596
1597 updateStatus();
1598
1599 if (wroteToTimeBuffer) {
1600 DPRINTF(Activity, "Activity this cycle.\n");
1601 cpu->activityThisCycle();
1602 }
1603}
1604
1605template <class Impl>
1606void
1607DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1608{
1609 ThreadID tid = inst->threadNumber;
1610
1611 iewExecutedInsts++;
1612
1613#if TRACING_ON
1614 inst->completeTick = curTick() - inst->fetchTick;
1615#endif
1616
1617 //
1618 // Control operations
1619 //
1620 if (inst->isControl())
1621 iewExecutedBranches[tid]++;
1622
1623 //
1624 // Memory operations
1625 //
1626 if (inst->isMemRef()) {
1627 iewExecutedRefs[tid]++;
1628
1629 if (inst->isLoad()) {
1630 iewExecLoadInsts[tid]++;
1631 }
1632 }
1633}
1634
1635template <class Impl>
1636void
1637DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1638{
1639 ThreadID tid = inst->threadNumber;
1640
1641 if (!fetchRedirect[tid] ||
1642 !toCommit->squash[tid] ||
1643 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1644
1645 if (inst->mispredicted()) {
1646 fetchRedirect[tid] = true;
1647
1648 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1649 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1650 inst->predInstAddr(), inst->predNextInstAddr());
1651 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1652 " NPC: %#x.\n", inst->nextInstAddr(),
1653 inst->nextInstAddr());
1654 // If incorrect, then signal the ROB that it must be squashed.
1655 squashDueToBranch(inst, tid);
1656
1657 if (inst->readPredTaken()) {
1658 predictedTakenIncorrect++;
1659 } else {
1660 predictedNotTakenIncorrect++;
1661 }
1662 }
1663 }
1664}
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