1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew. There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "cpu/timebuf.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template<class Impl>
58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59 : issueToExecQueue(params->backComSize, params->forwardComSize),
60 cpu(_cpu),
61 instQueue(_cpu, this, params),
62 ldstQueue(_cpu, this, params),
63 fuPool(params->fuPool),
64 commitToIEWDelay(params->commitToIEWDelay),
65 renameToIEWDelay(params->renameToIEWDelay),
66 issueToExecuteDelay(params->issueToExecuteDelay),
67 dispatchWidth(params->dispatchWidth),
68 issueWidth(params->issueWidth),
69 wbOutstanding(0),
70 wbWidth(params->wbWidth),
71 numThreads(params->numThreads),
72 switchedOut(false)
73{
74 _status = Active;
75 exeStatus = Running;
76 wbStatus = Idle;
77
78 // Setup wire to read instructions coming from issue.
79 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
80
81 // Instruction queue needs the queue between issue and execute.
82 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
83
84 for (ThreadID tid = 0; tid < numThreads; tid++) {
85 dispatchStatus[tid] = Running;
86 stalls[tid].commit = false;
87 fetchRedirect[tid] = false;
88 }
89
90 wbMax = wbWidth * params->wbDepth;
91
92 updateLSQNextCycle = false;
93
94 ableToIssue = true;
95
96 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
97}
98
99template <class Impl>
100std::string
101DefaultIEW<Impl>::name() const
102{
103 return cpu->name() + ".iew";
104}
105
106template <class Impl>
107void
108DefaultIEW<Impl>::regStats()
109{
110 using namespace Stats;
111
112 instQueue.regStats();
113 ldstQueue.regStats();
114
115 iewIdleCycles
116 .name(name() + ".iewIdleCycles")
117 .desc("Number of cycles IEW is idle");
118
119 iewSquashCycles
120 .name(name() + ".iewSquashCycles")
121 .desc("Number of cycles IEW is squashing");
122
123 iewBlockCycles
124 .name(name() + ".iewBlockCycles")
125 .desc("Number of cycles IEW is blocking");
126
127 iewUnblockCycles
128 .name(name() + ".iewUnblockCycles")
129 .desc("Number of cycles IEW is unblocking");
130
131 iewDispatchedInsts
132 .name(name() + ".iewDispatchedInsts")
133 .desc("Number of instructions dispatched to IQ");
134
135 iewDispSquashedInsts
136 .name(name() + ".iewDispSquashedInsts")
137 .desc("Number of squashed instructions skipped by dispatch");
138
139 iewDispLoadInsts
140 .name(name() + ".iewDispLoadInsts")
141 .desc("Number of dispatched load instructions");
142
143 iewDispStoreInsts
144 .name(name() + ".iewDispStoreInsts")
145 .desc("Number of dispatched store instructions");
146
147 iewDispNonSpecInsts
148 .name(name() + ".iewDispNonSpecInsts")
149 .desc("Number of dispatched non-speculative instructions");
150
151 iewIQFullEvents
152 .name(name() + ".iewIQFullEvents")
153 .desc("Number of times the IQ has become full, causing a stall");
154
155 iewLSQFullEvents
156 .name(name() + ".iewLSQFullEvents")
157 .desc("Number of times the LSQ has become full, causing a stall");
158
159 memOrderViolationEvents
160 .name(name() + ".memOrderViolationEvents")
161 .desc("Number of memory order violations");
162
163 predictedTakenIncorrect
164 .name(name() + ".predictedTakenIncorrect")
165 .desc("Number of branches that were predicted taken incorrectly");
166
167 predictedNotTakenIncorrect
168 .name(name() + ".predictedNotTakenIncorrect")
169 .desc("Number of branches that were predicted not taken incorrectly");
170
171 branchMispredicts
172 .name(name() + ".branchMispredicts")
173 .desc("Number of branch mispredicts detected at execute");
174
175 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
176
177 iewExecutedInsts
178 .name(name() + ".iewExecutedInsts")
179 .desc("Number of executed instructions");
180
181 iewExecLoadInsts
182 .init(cpu->numThreads)
183 .name(name() + ".iewExecLoadInsts")
184 .desc("Number of load instructions executed")
185 .flags(total);
186
187 iewExecSquashedInsts
188 .name(name() + ".iewExecSquashedInsts")
189 .desc("Number of squashed instructions skipped in execute");
190
191 iewExecutedSwp
192 .init(cpu->numThreads)
193 .name(name() + ".EXEC:swp")
194 .desc("number of swp insts executed")
195 .flags(total);
196
197 iewExecutedNop
198 .init(cpu->numThreads)
199 .name(name() + ".EXEC:nop")
200 .desc("number of nop insts executed")
201 .flags(total);
202
203 iewExecutedRefs
204 .init(cpu->numThreads)
205 .name(name() + ".EXEC:refs")
206 .desc("number of memory reference insts executed")
207 .flags(total);
208
209 iewExecutedBranches
210 .init(cpu->numThreads)
211 .name(name() + ".EXEC:branches")
212 .desc("Number of branches executed")
213 .flags(total);
214
215 iewExecStoreInsts
216 .name(name() + ".EXEC:stores")
217 .desc("Number of stores executed")
218 .flags(total);
219 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
220
221 iewExecRate
222 .name(name() + ".EXEC:rate")
223 .desc("Inst execution rate")
224 .flags(total);
225
226 iewExecRate = iewExecutedInsts / cpu->numCycles;
227
228 iewInstsToCommit
229 .init(cpu->numThreads)
230 .name(name() + ".WB:sent")
231 .desc("cumulative count of insts sent to commit")
232 .flags(total);
233
234 writebackCount
235 .init(cpu->numThreads)
236 .name(name() + ".WB:count")
237 .desc("cumulative count of insts written-back")
238 .flags(total);
239
240 producerInst
241 .init(cpu->numThreads)
242 .name(name() + ".WB:producers")
243 .desc("num instructions producing a value")
244 .flags(total);
245
246 consumerInst
247 .init(cpu->numThreads)
248 .name(name() + ".WB:consumers")
249 .desc("num instructions consuming a value")
250 .flags(total);
251
252 wbPenalized
253 .init(cpu->numThreads)
254 .name(name() + ".WB:penalized")
255 .desc("number of instrctions required to write to 'other' IQ")
256 .flags(total);
257
258 wbPenalizedRate
259 .name(name() + ".WB:penalized_rate")
260 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
261 .flags(total);
262
263 wbPenalizedRate = wbPenalized / writebackCount;
264
265 wbFanout
266 .name(name() + ".WB:fanout")
267 .desc("average fanout of values written-back")
268 .flags(total);
269
270 wbFanout = producerInst / consumerInst;
271
272 wbRate
273 .name(name() + ".WB:rate")
274 .desc("insts written-back per cycle")
275 .flags(total);
276 wbRate = writebackCount / cpu->numCycles;
277}
278
279template<class Impl>
280void
281DefaultIEW<Impl>::initStage()
282{
283 for (ThreadID tid = 0; tid < numThreads; tid++) {
284 toRename->iewInfo[tid].usedIQ = true;
285 toRename->iewInfo[tid].freeIQEntries =
286 instQueue.numFreeEntries(tid);
287
288 toRename->iewInfo[tid].usedLSQ = true;
289 toRename->iewInfo[tid].freeLSQEntries =
290 ldstQueue.numFreeEntries(tid);
291 }
292
293 cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300 timeBuffer = tb_ptr;
301
302 // Setup wire to read information from time buffer, from commit.
303 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304
305 // Setup wire to write information back to previous stages.
306 toRename = timeBuffer->getWire(0);
307
308 toFetch = timeBuffer->getWire(0);
309
310 // Instruction queue also needs main time buffer.
311 instQueue.setTimeBuffer(tb_ptr);
312}
313
314template<class Impl>
315void
316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 iewQueue = iq_ptr;
329
330 // Setup wire to write instructions to commit.
331 toCommit = iewQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337{
338 activeThreads = at_ptr;
339
340 ldstQueue.setActiveThreads(at_ptr);
341 instQueue.setActiveThreads(at_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
347{
348 scoreboard = sb_ptr;
349}
350
351template <class Impl>
352bool
353DefaultIEW<Impl>::drain()
354{
355 // IEW is ready to drain at any time.
356 cpu->signalDrained();
357 return true;
358}
359
360template <class Impl>
361void
362DefaultIEW<Impl>::resume()
363{
364}
365
366template <class Impl>
367void
368DefaultIEW<Impl>::switchOut()
369{
370 // Clear any state.
371 switchedOut = true;
372 assert(insts[0].empty());
373 assert(skidBuffer[0].empty());
374
375 instQueue.switchOut();
376 ldstQueue.switchOut();
377 fuPool->switchOut();
378
379 for (ThreadID tid = 0; tid < numThreads; tid++) {
380 while (!insts[tid].empty())
381 insts[tid].pop();
382 while (!skidBuffer[tid].empty())
383 skidBuffer[tid].pop();
384 }
385}
386
387template <class Impl>
388void
389DefaultIEW<Impl>::takeOverFrom()
390{
391 // Reset all state.
392 _status = Active;
393 exeStatus = Running;
394 wbStatus = Idle;
395 switchedOut = false;
396
397 instQueue.takeOverFrom();
398 ldstQueue.takeOverFrom();
399 fuPool->takeOverFrom();
400
401 initStage();
402 cpu->activityThisCycle();
403
404 for (ThreadID tid = 0; tid < numThreads; tid++) {
405 dispatchStatus[tid] = Running;
406 stalls[tid].commit = false;
407 fetchRedirect[tid] = false;
408 }
409
410 updateLSQNextCycle = false;
411
412 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413 issueToExecQueue.advance();
414 }
415}
416
417template<class Impl>
418void
419DefaultIEW<Impl>::squash(ThreadID tid)
420{
421 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
422
423 // Tell the IQ to start squashing.
424 instQueue.squash(tid);
425
426 // Tell the LDSTQ to start squashing.
427 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428 updatedQueues = true;
429
430 // Clear the skid buffer in case it has any data in it.
431 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432 tid, fromCommit->commitInfo[tid].doneSeqNum);
433
434 while (!skidBuffer[tid].empty()) {
435 if (skidBuffer[tid].front()->isLoad() ||
436 skidBuffer[tid].front()->isStore() ) {
437 toRename->iewInfo[tid].dispatchedToLSQ++;
438 }
439
440 toRename->iewInfo[tid].dispatched++;
441
442 skidBuffer[tid].pop();
443 }
444
445 emptyRenameInsts(tid);
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 toCommit->squash[tid] = true;
456 toCommit->squashedSeqNum[tid] = inst->seqNum;
457 toCommit->mispredPC[tid] = inst->instAddr();
458 toCommit->branchMispredict[tid] = true;
459
460 toCommit->branchTaken[tid] = inst->pcState().branching();
461 TheISA::PCState pc = inst->pcState();
462 TheISA::advancePC(pc, inst->staticInst);
463 toCommit->pc[tid] = pc;
464
465 toCommit->includeSquashInst[tid] = false;
466
467 wroteToTimeBuffer = true;
468}
469
470template<class Impl>
471void
472DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
473{
474 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
475 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
476
477 toCommit->squash[tid] = true;
478 toCommit->squashedSeqNum[tid] = inst->seqNum;
479 TheISA::PCState pc = inst->pcState();
480 TheISA::advancePC(pc, inst->staticInst);
481 toCommit->pc[tid] = pc;
482 toCommit->branchMispredict[tid] = false;
483
484 toCommit->includeSquashInst[tid] = false;
485
486 wroteToTimeBuffer = true;
487}
488
489template<class Impl>
490void
491DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
492{
493 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
494 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
495
496 toCommit->squash[tid] = true;
497 toCommit->squashedSeqNum[tid] = inst->seqNum;
498 toCommit->pc[tid] = inst->pcState();
499 toCommit->branchMispredict[tid] = false;
500
501 // Must include the broadcasted SN in the squash.
502 toCommit->includeSquashInst[tid] = true;
503
504 ldstQueue.setLoadBlockedHandled(tid);
505
506 wroteToTimeBuffer = true;
507}
508
509template<class Impl>
510void
511DefaultIEW<Impl>::block(ThreadID tid)
512{
513 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
514
515 if (dispatchStatus[tid] != Blocked &&
516 dispatchStatus[tid] != Unblocking) {
517 toRename->iewBlock[tid] = true;
518 wroteToTimeBuffer = true;
519 }
520
521 // Add the current inputs to the skid buffer so they can be
522 // reprocessed when this stage unblocks.
523 skidInsert(tid);
524
525 dispatchStatus[tid] = Blocked;
526}
527
528template<class Impl>
529void
530DefaultIEW<Impl>::unblock(ThreadID tid)
531{
532 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
533 "buffer %u.\n",tid, tid);
534
535 // If the skid bufffer is empty, signal back to previous stages to unblock.
536 // Also switch status to running.
537 if (skidBuffer[tid].empty()) {
538 toRename->iewUnblock[tid] = true;
539 wroteToTimeBuffer = true;
540 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
541 dispatchStatus[tid] = Running;
542 }
543}
544
545template<class Impl>
546void
547DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
548{
549 instQueue.wakeDependents(inst);
550}
551
552template<class Impl>
553void
554DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
555{
556 instQueue.rescheduleMemInst(inst);
557}
558
559template<class Impl>
560void
561DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
562{
563 instQueue.replayMemInst(inst);
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
569{
570 // This function should not be called after writebackInsts in a
571 // single cycle. That will cause problems with an instruction
572 // being added to the queue to commit without being processed by
573 // writebackInsts prior to being sent to commit.
574
575 // First check the time slot that this instruction will write
576 // to. If there are free write ports at the time, then go ahead
577 // and write the instruction to that time. If there are not,
578 // keep looking back to see where's the first time there's a
579 // free slot.
580 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
581 ++wbNumInst;
582 if (wbNumInst == wbWidth) {
583 ++wbCycle;
584 wbNumInst = 0;
585 }
586
587 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
588 }
589
590 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
591 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
592 // Add finished instruction to queue to commit.
593 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
594 (*iewQueue)[wbCycle].size++;
595}
596
597template <class Impl>
598unsigned
599DefaultIEW<Impl>::validInstsFromRename()
600{
601 unsigned inst_count = 0;
602
603 for (int i=0; i<fromRename->size; i++) {
604 if (!fromRename->insts[i]->isSquashed())
605 inst_count++;
606 }
607
608 return inst_count;
609}
610
611template<class Impl>
612void
613DefaultIEW<Impl>::skidInsert(ThreadID tid)
614{
615 DynInstPtr inst = NULL;
616
617 while (!insts[tid].empty()) {
618 inst = insts[tid].front();
619
620 insts[tid].pop();
621
622 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
623 "dispatch skidBuffer %i\n",tid, inst->seqNum,
624 inst->pcState(),tid);
625
626 skidBuffer[tid].push(inst);
627 }
628
629 assert(skidBuffer[tid].size() <= skidBufferMax &&
630 "Skidbuffer Exceeded Max Size");
631}
632
633template<class Impl>
634int
635DefaultIEW<Impl>::skidCount()
636{
637 int max=0;
638
639 list<ThreadID>::iterator threads = activeThreads->begin();
640 list<ThreadID>::iterator end = activeThreads->end();
641
642 while (threads != end) {
643 ThreadID tid = *threads++;
644 unsigned thread_count = skidBuffer[tid].size();
645 if (max < thread_count)
646 max = thread_count;
647 }
648
649 return max;
650}
651
652template<class Impl>
653bool
654DefaultIEW<Impl>::skidsEmpty()
655{
656 list<ThreadID>::iterator threads = activeThreads->begin();
657 list<ThreadID>::iterator end = activeThreads->end();
658
659 while (threads != end) {
660 ThreadID tid = *threads++;
661
662 if (!skidBuffer[tid].empty())
663 return false;
664 }
665
666 return true;
667}
668
669template <class Impl>
670void
671DefaultIEW<Impl>::updateStatus()
672{
673 bool any_unblocking = false;
674
675 list<ThreadID>::iterator threads = activeThreads->begin();
676 list<ThreadID>::iterator end = activeThreads->end();
677
678 while (threads != end) {
679 ThreadID tid = *threads++;
680
681 if (dispatchStatus[tid] == Unblocking) {
682 any_unblocking = true;
683 break;
684 }
685 }
686
687 // If there are no ready instructions waiting to be scheduled by the IQ,
688 // and there's no stores waiting to write back, and dispatch is not
689 // unblocking, then there is no internal activity for the IEW stage.
690 if (_status == Active && !instQueue.hasReadyInsts() &&
691 !ldstQueue.willWB() && !any_unblocking) {
692 DPRINTF(IEW, "IEW switching to idle\n");
693
694 deactivateStage();
695
696 _status = Inactive;
697 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
698 ldstQueue.willWB() ||
699 any_unblocking)) {
700 // Otherwise there is internal activity. Set to active.
701 DPRINTF(IEW, "IEW switching to active\n");
702
703 activateStage();
704
705 _status = Active;
706 }
707}
708
709template <class Impl>
710void
711DefaultIEW<Impl>::resetEntries()
712{
713 instQueue.resetEntries();
714 ldstQueue.resetEntries();
715}
716
717template <class Impl>
718void
719DefaultIEW<Impl>::readStallSignals(ThreadID tid)
720{
721 if (fromCommit->commitBlock[tid]) {
722 stalls[tid].commit = true;
723 }
724
725 if (fromCommit->commitUnblock[tid]) {
726 assert(stalls[tid].commit);
727 stalls[tid].commit = false;
728 }
729}
730
731template <class Impl>
732bool
733DefaultIEW<Impl>::checkStall(ThreadID tid)
734{
735 bool ret_val(false);
736
737 if (stalls[tid].commit) {
738 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
739 ret_val = true;
740 } else if (instQueue.isFull(tid)) {
741 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
742 ret_val = true;
743 } else if (ldstQueue.isFull(tid)) {
744 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
745
746 if (ldstQueue.numLoads(tid) > 0 ) {
747
748 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
749 tid,ldstQueue.getLoadHeadSeqNum(tid));
750 }
751
752 if (ldstQueue.numStores(tid) > 0) {
753
754 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
755 tid,ldstQueue.getStoreHeadSeqNum(tid));
756 }
757
758 ret_val = true;
759 } else if (ldstQueue.isStalled(tid)) {
760 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
761 ret_val = true;
762 }
763
764 return ret_val;
765}
766
767template <class Impl>
768void
769DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
770{
771 // Check if there's a squash signal, squash if there is
772 // Check stall signals, block if there is.
773 // If status was Blocked
774 // if so then go to unblocking
775 // If status was Squashing
776 // check if squashing is not high. Switch to running this cycle.
777
778 readStallSignals(tid);
779
780 if (fromCommit->commitInfo[tid].squash) {
781 squash(tid);
782
783 if (dispatchStatus[tid] == Blocked ||
784 dispatchStatus[tid] == Unblocking) {
785 toRename->iewUnblock[tid] = true;
786 wroteToTimeBuffer = true;
787 }
788
789 dispatchStatus[tid] = Squashing;
790
791 fetchRedirect[tid] = false;
792 return;
793 }
794
795 if (fromCommit->commitInfo[tid].robSquashing) {
796 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
797
798 dispatchStatus[tid] = Squashing;
799
800 emptyRenameInsts(tid);
801 wroteToTimeBuffer = true;
802 return;
803 }
804
805 if (checkStall(tid)) {
806 block(tid);
807 dispatchStatus[tid] = Blocked;
808 return;
809 }
810
811 if (dispatchStatus[tid] == Blocked) {
812 // Status from previous cycle was blocked, but there are no more stall
813 // conditions. Switch over to unblocking.
814 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
815 tid);
816
817 dispatchStatus[tid] = Unblocking;
818
819 unblock(tid);
820
821 return;
822 }
823
824 if (dispatchStatus[tid] == Squashing) {
825 // Switch status to running if rename isn't being told to block or
826 // squash this cycle.
827 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
828 tid);
829
830 dispatchStatus[tid] = Running;
831
832 return;
833 }
834}
835
836template <class Impl>
837void
838DefaultIEW<Impl>::sortInsts()
839{
840 int insts_from_rename = fromRename->size;
841#ifdef DEBUG
842 for (ThreadID tid = 0; tid < numThreads; tid++)
843 assert(insts[tid].empty());
844#endif
845 for (int i = 0; i < insts_from_rename; ++i) {
846 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
847 }
848}
849
850template <class Impl>
851void
852DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
853{
854 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
855
856 while (!insts[tid].empty()) {
857
858 if (insts[tid].front()->isLoad() ||
859 insts[tid].front()->isStore() ) {
860 toRename->iewInfo[tid].dispatchedToLSQ++;
861 }
862
863 toRename->iewInfo[tid].dispatched++;
864
865 insts[tid].pop();
866 }
867}
868
869template <class Impl>
870void
871DefaultIEW<Impl>::wakeCPU()
872{
873 cpu->wakeCPU();
874}
875
876template <class Impl>
877void
878DefaultIEW<Impl>::activityThisCycle()
879{
880 DPRINTF(Activity, "Activity this cycle.\n");
881 cpu->activityThisCycle();
882}
883
884template <class Impl>
885inline void
886DefaultIEW<Impl>::activateStage()
887{
888 DPRINTF(Activity, "Activating stage.\n");
889 cpu->activateStage(O3CPU::IEWIdx);
890}
891
892template <class Impl>
893inline void
894DefaultIEW<Impl>::deactivateStage()
895{
896 DPRINTF(Activity, "Deactivating stage.\n");
897 cpu->deactivateStage(O3CPU::IEWIdx);
898}
899
900template<class Impl>
901void
902DefaultIEW<Impl>::dispatch(ThreadID tid)
903{
904 // If status is Running or idle,
905 // call dispatchInsts()
906 // If status is Unblocking,
907 // buffer any instructions coming from rename
908 // continue trying to empty skid buffer
909 // check if stall conditions have passed
910
911 if (dispatchStatus[tid] == Blocked) {
912 ++iewBlockCycles;
913
914 } else if (dispatchStatus[tid] == Squashing) {
915 ++iewSquashCycles;
916 }
917
918 // Dispatch should try to dispatch as many instructions as its bandwidth
919 // will allow, as long as it is not currently blocked.
920 if (dispatchStatus[tid] == Running ||
921 dispatchStatus[tid] == Idle) {
922 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
923 "dispatch.\n", tid);
924
925 dispatchInsts(tid);
926 } else if (dispatchStatus[tid] == Unblocking) {
927 // Make sure that the skid buffer has something in it if the
928 // status is unblocking.
929 assert(!skidsEmpty());
930
931 // If the status was unblocking, then instructions from the skid
932 // buffer were used. Remove those instructions and handle
933 // the rest of unblocking.
934 dispatchInsts(tid);
935
936 ++iewUnblockCycles;
937
938 if (validInstsFromRename()) {
939 // Add the current inputs to the skid buffer so they can be
940 // reprocessed when this stage unblocks.
941 skidInsert(tid);
942 }
943
944 unblock(tid);
945 }
946}
947
948template <class Impl>
949void
950DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
951{
952 // Obtain instructions from skid buffer if unblocking, or queue from rename
953 // otherwise.
954 std::queue<DynInstPtr> &insts_to_dispatch =
955 dispatchStatus[tid] == Unblocking ?
956 skidBuffer[tid] : insts[tid];
957
958 int insts_to_add = insts_to_dispatch.size();
959
960 DynInstPtr inst;
961 bool add_to_iq = false;
962 int dis_num_inst = 0;
963
964 // Loop through the instructions, putting them in the instruction
965 // queue.
966 for ( ; dis_num_inst < insts_to_add &&
967 dis_num_inst < dispatchWidth;
968 ++dis_num_inst)
969 {
970 inst = insts_to_dispatch.front();
971
972 if (dispatchStatus[tid] == Unblocking) {
973 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
974 "buffer\n", tid);
975 }
976
977 // Make sure there's a valid instruction there.
978 assert(inst);
979
980 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
981 "IQ.\n",
982 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
983
984 // Be sure to mark these instructions as ready so that the
985 // commit stage can go ahead and execute them, and mark
986 // them as issued so the IQ doesn't reprocess them.
987
988 // Check for squashed instructions.
989 if (inst->isSquashed()) {
990 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
991 "not adding to IQ.\n", tid);
992
993 ++iewDispSquashedInsts;
994
995 insts_to_dispatch.pop();
996
997 //Tell Rename That An Instruction has been processed
998 if (inst->isLoad() || inst->isStore()) {
999 toRename->iewInfo[tid].dispatchedToLSQ++;
1000 }
1001 toRename->iewInfo[tid].dispatched++;
1002
1003 continue;
1004 }
1005
1006 // Check for full conditions.
1007 if (instQueue.isFull(tid)) {
1008 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1009
1010 // Call function to start blocking.
1011 block(tid);
1012
1013 // Set unblock to false. Special case where we are using
1014 // skidbuffer (unblocking) instructions but then we still
1015 // get full in the IQ.
1016 toRename->iewUnblock[tid] = false;
1017
1018 ++iewIQFullEvents;
1019 break;
1020 } else if (ldstQueue.isFull(tid)) {
1021 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1022
1023 // Call function to start blocking.
1024 block(tid);
1025
1026 // Set unblock to false. Special case where we are using
1027 // skidbuffer (unblocking) instructions but then we still
1028 // get full in the IQ.
1029 toRename->iewUnblock[tid] = false;
1030
1031 ++iewLSQFullEvents;
1032 break;
1033 }
1034
1035 // Otherwise issue the instruction just fine.
1036 if (inst->isLoad()) {
1037 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1038 "encountered, adding to LSQ.\n", tid);
1039
1040 // Reserve a spot in the load store queue for this
1041 // memory access.
1042 ldstQueue.insertLoad(inst);
1043
1044 ++iewDispLoadInsts;
1045
1046 add_to_iq = true;
1047
1048 toRename->iewInfo[tid].dispatchedToLSQ++;
1049 } else if (inst->isStore()) {
1050 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1051 "encountered, adding to LSQ.\n", tid);
1052
1053 ldstQueue.insertStore(inst);
1054
1055 ++iewDispStoreInsts;
1056
1057 if (inst->isStoreConditional()) {
1058 // Store conditionals need to be set as "canCommit()"
1059 // so that commit can process them when they reach the
1060 // head of commit.
1061 // @todo: This is somewhat specific to Alpha.
1062 inst->setCanCommit();
1063 instQueue.insertNonSpec(inst);
1064 add_to_iq = false;
1065
1066 ++iewDispNonSpecInsts;
1067 } else {
1068 add_to_iq = true;
1069 }
1070
1071 toRename->iewInfo[tid].dispatchedToLSQ++;
1072 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1073 // Same as non-speculative stores.
1074 inst->setCanCommit();
1075 instQueue.insertBarrier(inst);
1076 add_to_iq = false;
1077 } else if (inst->isNop()) {
1078 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1079 "skipping.\n", tid);
1080
1081 inst->setIssued();
1082 inst->setExecuted();
1083 inst->setCanCommit();
1084
1085 instQueue.recordProducer(inst);
1086
1087 iewExecutedNop[tid]++;
1088
1089 add_to_iq = false;
1090 } else if (inst->isExecuted()) {
1091 assert(0 && "Instruction shouldn't be executed.\n");
1092 DPRINTF(IEW, "Issue: Executed branch encountered, "
1093 "skipping.\n");
1094
1095 inst->setIssued();
1096 inst->setCanCommit();
1097
1098 instQueue.recordProducer(inst);
1099
1100 add_to_iq = false;
1101 } else {
1102 add_to_iq = true;
1103 }
1104 if (inst->isNonSpeculative()) {
1105 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1106 "encountered, skipping.\n", tid);
1107
1108 // Same as non-speculative stores.
1109 inst->setCanCommit();
1110
1111 // Specifically insert it as nonspeculative.
1112 instQueue.insertNonSpec(inst);
1113
1114 ++iewDispNonSpecInsts;
1115
1116 add_to_iq = false;
1117 }
1118
1119 // If the instruction queue is not full, then add the
1120 // instruction.
1121 if (add_to_iq) {
1122 instQueue.insert(inst);
1123 }
1124
1125 insts_to_dispatch.pop();
1126
1127 toRename->iewInfo[tid].dispatched++;
1128
1129 ++iewDispatchedInsts;
1130 }
1131
1132 if (!insts_to_dispatch.empty()) {
1133 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1134 block(tid);
1135 toRename->iewUnblock[tid] = false;
1136 }
1137
1138 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1139 dispatchStatus[tid] = Running;
1140
1141 updatedQueues = true;
1142 }
1143
1144 dis_num_inst = 0;
1145}
1146
1147template <class Impl>
1148void
1149DefaultIEW<Impl>::printAvailableInsts()
1150{
1151 int inst = 0;
1152
1153 std::cout << "Available Instructions: ";
1154
1155 while (fromIssue->insts[inst]) {
1156
1157 if (inst%3==0) std::cout << "\n\t";
1158
1159 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1160 << " TN: " << fromIssue->insts[inst]->threadNumber
1161 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1162
1163 inst++;
1164
1165 }
1166
1167 std::cout << "\n";
1168}
1169
1170template <class Impl>
1171void
1172DefaultIEW<Impl>::executeInsts()
1173{
1174 wbNumInst = 0;
1175 wbCycle = 0;
1176
1177 list<ThreadID>::iterator threads = activeThreads->begin();
1178 list<ThreadID>::iterator end = activeThreads->end();
1179
1180 while (threads != end) {
1181 ThreadID tid = *threads++;
1182 fetchRedirect[tid] = false;
1183 }
1184
1185 // Uncomment this if you want to see all available instructions.
1186 // @todo This doesn't actually work anymore, we should fix it.
1187// printAvailableInsts();
1188
1189 // Execute/writeback any instructions that are available.
1190 int insts_to_execute = fromIssue->size;
1191 int inst_num = 0;
1192 for (; inst_num < insts_to_execute;
1193 ++inst_num) {
1194
1195 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1196
1197 DynInstPtr inst = instQueue.getInstToExecute();
1198
1199 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1200 inst->pcState(), inst->threadNumber,inst->seqNum);
1201
1202 // Check if the instruction is squashed; if so then skip it
1203 if (inst->isSquashed()) {
1204 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1205
1206 // Consider this instruction executed so that commit can go
1207 // ahead and retire the instruction.
1208 inst->setExecuted();
1209
1210 // Not sure if I should set this here or just let commit try to
1211 // commit any squashed instructions. I like the latter a bit more.
1212 inst->setCanCommit();
1213
1214 ++iewExecSquashedInsts;
1215
1216 decrWb(inst->seqNum);
1217 continue;
1218 }
1219
1220 Fault fault = NoFault;
1221
1222 // Execute instruction.
1223 // Note that if the instruction faults, it will be handled
1224 // at the commit stage.
1225 if (inst->isMemRef() &&
1226 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1227 DPRINTF(IEW, "Execute: Calculating address for memory "
1228 "reference.\n");
1229
1230 // Tell the LDSTQ to execute this instruction (if it is a load).
1231 if (inst->isLoad()) {
1232 // Loads will mark themselves as executed, and their writeback
1233 // event adds the instruction to the queue to commit
1234 fault = ldstQueue.executeLoad(inst);
1235 } else if (inst->isStore()) {
1236 fault = ldstQueue.executeStore(inst);
1237
1238 // If the store had a fault then it may not have a mem req
1239 if (fault != NoFault || inst->readPredicate() == false ||
1240 !inst->isStoreConditional()) {
1241 // If the instruction faulted, then we need to send it along
1242 // to commit without the instruction completing.
1243 // Send this instruction to commit, also make sure iew stage
1244 // realizes there is activity.
1245 inst->setExecuted();
1246 instToCommit(inst);
1247 activityThisCycle();
1248 }
1249
1250 // Store conditionals will mark themselves as
1251 // executed, and their writeback event will add the
1252 // instruction to the queue to commit.
1253 } else {
1254 panic("Unexpected memory type!\n");
1255 }
1256
1257 } else {
1258 // If the instruction has already faulted, then skip executing it.
1259 // Such case can happen when it faulted during ITLB translation.
1260 // If we execute the instruction (even if it's a nop) the fault
1261 // will be replaced and we will lose it.
1262 if (inst->getFault() == NoFault) {
1263 inst->execute();
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew. There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "cpu/timebuf.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template<class Impl>
58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59 : issueToExecQueue(params->backComSize, params->forwardComSize),
60 cpu(_cpu),
61 instQueue(_cpu, this, params),
62 ldstQueue(_cpu, this, params),
63 fuPool(params->fuPool),
64 commitToIEWDelay(params->commitToIEWDelay),
65 renameToIEWDelay(params->renameToIEWDelay),
66 issueToExecuteDelay(params->issueToExecuteDelay),
67 dispatchWidth(params->dispatchWidth),
68 issueWidth(params->issueWidth),
69 wbOutstanding(0),
70 wbWidth(params->wbWidth),
71 numThreads(params->numThreads),
72 switchedOut(false)
73{
74 _status = Active;
75 exeStatus = Running;
76 wbStatus = Idle;
77
78 // Setup wire to read instructions coming from issue.
79 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
80
81 // Instruction queue needs the queue between issue and execute.
82 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
83
84 for (ThreadID tid = 0; tid < numThreads; tid++) {
85 dispatchStatus[tid] = Running;
86 stalls[tid].commit = false;
87 fetchRedirect[tid] = false;
88 }
89
90 wbMax = wbWidth * params->wbDepth;
91
92 updateLSQNextCycle = false;
93
94 ableToIssue = true;
95
96 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
97}
98
99template <class Impl>
100std::string
101DefaultIEW<Impl>::name() const
102{
103 return cpu->name() + ".iew";
104}
105
106template <class Impl>
107void
108DefaultIEW<Impl>::regStats()
109{
110 using namespace Stats;
111
112 instQueue.regStats();
113 ldstQueue.regStats();
114
115 iewIdleCycles
116 .name(name() + ".iewIdleCycles")
117 .desc("Number of cycles IEW is idle");
118
119 iewSquashCycles
120 .name(name() + ".iewSquashCycles")
121 .desc("Number of cycles IEW is squashing");
122
123 iewBlockCycles
124 .name(name() + ".iewBlockCycles")
125 .desc("Number of cycles IEW is blocking");
126
127 iewUnblockCycles
128 .name(name() + ".iewUnblockCycles")
129 .desc("Number of cycles IEW is unblocking");
130
131 iewDispatchedInsts
132 .name(name() + ".iewDispatchedInsts")
133 .desc("Number of instructions dispatched to IQ");
134
135 iewDispSquashedInsts
136 .name(name() + ".iewDispSquashedInsts")
137 .desc("Number of squashed instructions skipped by dispatch");
138
139 iewDispLoadInsts
140 .name(name() + ".iewDispLoadInsts")
141 .desc("Number of dispatched load instructions");
142
143 iewDispStoreInsts
144 .name(name() + ".iewDispStoreInsts")
145 .desc("Number of dispatched store instructions");
146
147 iewDispNonSpecInsts
148 .name(name() + ".iewDispNonSpecInsts")
149 .desc("Number of dispatched non-speculative instructions");
150
151 iewIQFullEvents
152 .name(name() + ".iewIQFullEvents")
153 .desc("Number of times the IQ has become full, causing a stall");
154
155 iewLSQFullEvents
156 .name(name() + ".iewLSQFullEvents")
157 .desc("Number of times the LSQ has become full, causing a stall");
158
159 memOrderViolationEvents
160 .name(name() + ".memOrderViolationEvents")
161 .desc("Number of memory order violations");
162
163 predictedTakenIncorrect
164 .name(name() + ".predictedTakenIncorrect")
165 .desc("Number of branches that were predicted taken incorrectly");
166
167 predictedNotTakenIncorrect
168 .name(name() + ".predictedNotTakenIncorrect")
169 .desc("Number of branches that were predicted not taken incorrectly");
170
171 branchMispredicts
172 .name(name() + ".branchMispredicts")
173 .desc("Number of branch mispredicts detected at execute");
174
175 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
176
177 iewExecutedInsts
178 .name(name() + ".iewExecutedInsts")
179 .desc("Number of executed instructions");
180
181 iewExecLoadInsts
182 .init(cpu->numThreads)
183 .name(name() + ".iewExecLoadInsts")
184 .desc("Number of load instructions executed")
185 .flags(total);
186
187 iewExecSquashedInsts
188 .name(name() + ".iewExecSquashedInsts")
189 .desc("Number of squashed instructions skipped in execute");
190
191 iewExecutedSwp
192 .init(cpu->numThreads)
193 .name(name() + ".EXEC:swp")
194 .desc("number of swp insts executed")
195 .flags(total);
196
197 iewExecutedNop
198 .init(cpu->numThreads)
199 .name(name() + ".EXEC:nop")
200 .desc("number of nop insts executed")
201 .flags(total);
202
203 iewExecutedRefs
204 .init(cpu->numThreads)
205 .name(name() + ".EXEC:refs")
206 .desc("number of memory reference insts executed")
207 .flags(total);
208
209 iewExecutedBranches
210 .init(cpu->numThreads)
211 .name(name() + ".EXEC:branches")
212 .desc("Number of branches executed")
213 .flags(total);
214
215 iewExecStoreInsts
216 .name(name() + ".EXEC:stores")
217 .desc("Number of stores executed")
218 .flags(total);
219 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
220
221 iewExecRate
222 .name(name() + ".EXEC:rate")
223 .desc("Inst execution rate")
224 .flags(total);
225
226 iewExecRate = iewExecutedInsts / cpu->numCycles;
227
228 iewInstsToCommit
229 .init(cpu->numThreads)
230 .name(name() + ".WB:sent")
231 .desc("cumulative count of insts sent to commit")
232 .flags(total);
233
234 writebackCount
235 .init(cpu->numThreads)
236 .name(name() + ".WB:count")
237 .desc("cumulative count of insts written-back")
238 .flags(total);
239
240 producerInst
241 .init(cpu->numThreads)
242 .name(name() + ".WB:producers")
243 .desc("num instructions producing a value")
244 .flags(total);
245
246 consumerInst
247 .init(cpu->numThreads)
248 .name(name() + ".WB:consumers")
249 .desc("num instructions consuming a value")
250 .flags(total);
251
252 wbPenalized
253 .init(cpu->numThreads)
254 .name(name() + ".WB:penalized")
255 .desc("number of instrctions required to write to 'other' IQ")
256 .flags(total);
257
258 wbPenalizedRate
259 .name(name() + ".WB:penalized_rate")
260 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
261 .flags(total);
262
263 wbPenalizedRate = wbPenalized / writebackCount;
264
265 wbFanout
266 .name(name() + ".WB:fanout")
267 .desc("average fanout of values written-back")
268 .flags(total);
269
270 wbFanout = producerInst / consumerInst;
271
272 wbRate
273 .name(name() + ".WB:rate")
274 .desc("insts written-back per cycle")
275 .flags(total);
276 wbRate = writebackCount / cpu->numCycles;
277}
278
279template<class Impl>
280void
281DefaultIEW<Impl>::initStage()
282{
283 for (ThreadID tid = 0; tid < numThreads; tid++) {
284 toRename->iewInfo[tid].usedIQ = true;
285 toRename->iewInfo[tid].freeIQEntries =
286 instQueue.numFreeEntries(tid);
287
288 toRename->iewInfo[tid].usedLSQ = true;
289 toRename->iewInfo[tid].freeLSQEntries =
290 ldstQueue.numFreeEntries(tid);
291 }
292
293 cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300 timeBuffer = tb_ptr;
301
302 // Setup wire to read information from time buffer, from commit.
303 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304
305 // Setup wire to write information back to previous stages.
306 toRename = timeBuffer->getWire(0);
307
308 toFetch = timeBuffer->getWire(0);
309
310 // Instruction queue also needs main time buffer.
311 instQueue.setTimeBuffer(tb_ptr);
312}
313
314template<class Impl>
315void
316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 iewQueue = iq_ptr;
329
330 // Setup wire to write instructions to commit.
331 toCommit = iewQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337{
338 activeThreads = at_ptr;
339
340 ldstQueue.setActiveThreads(at_ptr);
341 instQueue.setActiveThreads(at_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
347{
348 scoreboard = sb_ptr;
349}
350
351template <class Impl>
352bool
353DefaultIEW<Impl>::drain()
354{
355 // IEW is ready to drain at any time.
356 cpu->signalDrained();
357 return true;
358}
359
360template <class Impl>
361void
362DefaultIEW<Impl>::resume()
363{
364}
365
366template <class Impl>
367void
368DefaultIEW<Impl>::switchOut()
369{
370 // Clear any state.
371 switchedOut = true;
372 assert(insts[0].empty());
373 assert(skidBuffer[0].empty());
374
375 instQueue.switchOut();
376 ldstQueue.switchOut();
377 fuPool->switchOut();
378
379 for (ThreadID tid = 0; tid < numThreads; tid++) {
380 while (!insts[tid].empty())
381 insts[tid].pop();
382 while (!skidBuffer[tid].empty())
383 skidBuffer[tid].pop();
384 }
385}
386
387template <class Impl>
388void
389DefaultIEW<Impl>::takeOverFrom()
390{
391 // Reset all state.
392 _status = Active;
393 exeStatus = Running;
394 wbStatus = Idle;
395 switchedOut = false;
396
397 instQueue.takeOverFrom();
398 ldstQueue.takeOverFrom();
399 fuPool->takeOverFrom();
400
401 initStage();
402 cpu->activityThisCycle();
403
404 for (ThreadID tid = 0; tid < numThreads; tid++) {
405 dispatchStatus[tid] = Running;
406 stalls[tid].commit = false;
407 fetchRedirect[tid] = false;
408 }
409
410 updateLSQNextCycle = false;
411
412 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413 issueToExecQueue.advance();
414 }
415}
416
417template<class Impl>
418void
419DefaultIEW<Impl>::squash(ThreadID tid)
420{
421 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
422
423 // Tell the IQ to start squashing.
424 instQueue.squash(tid);
425
426 // Tell the LDSTQ to start squashing.
427 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428 updatedQueues = true;
429
430 // Clear the skid buffer in case it has any data in it.
431 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432 tid, fromCommit->commitInfo[tid].doneSeqNum);
433
434 while (!skidBuffer[tid].empty()) {
435 if (skidBuffer[tid].front()->isLoad() ||
436 skidBuffer[tid].front()->isStore() ) {
437 toRename->iewInfo[tid].dispatchedToLSQ++;
438 }
439
440 toRename->iewInfo[tid].dispatched++;
441
442 skidBuffer[tid].pop();
443 }
444
445 emptyRenameInsts(tid);
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 toCommit->squash[tid] = true;
456 toCommit->squashedSeqNum[tid] = inst->seqNum;
457 toCommit->mispredPC[tid] = inst->instAddr();
458 toCommit->branchMispredict[tid] = true;
459
460 toCommit->branchTaken[tid] = inst->pcState().branching();
461 TheISA::PCState pc = inst->pcState();
462 TheISA::advancePC(pc, inst->staticInst);
463 toCommit->pc[tid] = pc;
464
465 toCommit->includeSquashInst[tid] = false;
466
467 wroteToTimeBuffer = true;
468}
469
470template<class Impl>
471void
472DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
473{
474 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
475 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
476
477 toCommit->squash[tid] = true;
478 toCommit->squashedSeqNum[tid] = inst->seqNum;
479 TheISA::PCState pc = inst->pcState();
480 TheISA::advancePC(pc, inst->staticInst);
481 toCommit->pc[tid] = pc;
482 toCommit->branchMispredict[tid] = false;
483
484 toCommit->includeSquashInst[tid] = false;
485
486 wroteToTimeBuffer = true;
487}
488
489template<class Impl>
490void
491DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
492{
493 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
494 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
495
496 toCommit->squash[tid] = true;
497 toCommit->squashedSeqNum[tid] = inst->seqNum;
498 toCommit->pc[tid] = inst->pcState();
499 toCommit->branchMispredict[tid] = false;
500
501 // Must include the broadcasted SN in the squash.
502 toCommit->includeSquashInst[tid] = true;
503
504 ldstQueue.setLoadBlockedHandled(tid);
505
506 wroteToTimeBuffer = true;
507}
508
509template<class Impl>
510void
511DefaultIEW<Impl>::block(ThreadID tid)
512{
513 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
514
515 if (dispatchStatus[tid] != Blocked &&
516 dispatchStatus[tid] != Unblocking) {
517 toRename->iewBlock[tid] = true;
518 wroteToTimeBuffer = true;
519 }
520
521 // Add the current inputs to the skid buffer so they can be
522 // reprocessed when this stage unblocks.
523 skidInsert(tid);
524
525 dispatchStatus[tid] = Blocked;
526}
527
528template<class Impl>
529void
530DefaultIEW<Impl>::unblock(ThreadID tid)
531{
532 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
533 "buffer %u.\n",tid, tid);
534
535 // If the skid bufffer is empty, signal back to previous stages to unblock.
536 // Also switch status to running.
537 if (skidBuffer[tid].empty()) {
538 toRename->iewUnblock[tid] = true;
539 wroteToTimeBuffer = true;
540 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
541 dispatchStatus[tid] = Running;
542 }
543}
544
545template<class Impl>
546void
547DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
548{
549 instQueue.wakeDependents(inst);
550}
551
552template<class Impl>
553void
554DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
555{
556 instQueue.rescheduleMemInst(inst);
557}
558
559template<class Impl>
560void
561DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
562{
563 instQueue.replayMemInst(inst);
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
569{
570 // This function should not be called after writebackInsts in a
571 // single cycle. That will cause problems with an instruction
572 // being added to the queue to commit without being processed by
573 // writebackInsts prior to being sent to commit.
574
575 // First check the time slot that this instruction will write
576 // to. If there are free write ports at the time, then go ahead
577 // and write the instruction to that time. If there are not,
578 // keep looking back to see where's the first time there's a
579 // free slot.
580 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
581 ++wbNumInst;
582 if (wbNumInst == wbWidth) {
583 ++wbCycle;
584 wbNumInst = 0;
585 }
586
587 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
588 }
589
590 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
591 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
592 // Add finished instruction to queue to commit.
593 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
594 (*iewQueue)[wbCycle].size++;
595}
596
597template <class Impl>
598unsigned
599DefaultIEW<Impl>::validInstsFromRename()
600{
601 unsigned inst_count = 0;
602
603 for (int i=0; i<fromRename->size; i++) {
604 if (!fromRename->insts[i]->isSquashed())
605 inst_count++;
606 }
607
608 return inst_count;
609}
610
611template<class Impl>
612void
613DefaultIEW<Impl>::skidInsert(ThreadID tid)
614{
615 DynInstPtr inst = NULL;
616
617 while (!insts[tid].empty()) {
618 inst = insts[tid].front();
619
620 insts[tid].pop();
621
622 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
623 "dispatch skidBuffer %i\n",tid, inst->seqNum,
624 inst->pcState(),tid);
625
626 skidBuffer[tid].push(inst);
627 }
628
629 assert(skidBuffer[tid].size() <= skidBufferMax &&
630 "Skidbuffer Exceeded Max Size");
631}
632
633template<class Impl>
634int
635DefaultIEW<Impl>::skidCount()
636{
637 int max=0;
638
639 list<ThreadID>::iterator threads = activeThreads->begin();
640 list<ThreadID>::iterator end = activeThreads->end();
641
642 while (threads != end) {
643 ThreadID tid = *threads++;
644 unsigned thread_count = skidBuffer[tid].size();
645 if (max < thread_count)
646 max = thread_count;
647 }
648
649 return max;
650}
651
652template<class Impl>
653bool
654DefaultIEW<Impl>::skidsEmpty()
655{
656 list<ThreadID>::iterator threads = activeThreads->begin();
657 list<ThreadID>::iterator end = activeThreads->end();
658
659 while (threads != end) {
660 ThreadID tid = *threads++;
661
662 if (!skidBuffer[tid].empty())
663 return false;
664 }
665
666 return true;
667}
668
669template <class Impl>
670void
671DefaultIEW<Impl>::updateStatus()
672{
673 bool any_unblocking = false;
674
675 list<ThreadID>::iterator threads = activeThreads->begin();
676 list<ThreadID>::iterator end = activeThreads->end();
677
678 while (threads != end) {
679 ThreadID tid = *threads++;
680
681 if (dispatchStatus[tid] == Unblocking) {
682 any_unblocking = true;
683 break;
684 }
685 }
686
687 // If there are no ready instructions waiting to be scheduled by the IQ,
688 // and there's no stores waiting to write back, and dispatch is not
689 // unblocking, then there is no internal activity for the IEW stage.
690 if (_status == Active && !instQueue.hasReadyInsts() &&
691 !ldstQueue.willWB() && !any_unblocking) {
692 DPRINTF(IEW, "IEW switching to idle\n");
693
694 deactivateStage();
695
696 _status = Inactive;
697 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
698 ldstQueue.willWB() ||
699 any_unblocking)) {
700 // Otherwise there is internal activity. Set to active.
701 DPRINTF(IEW, "IEW switching to active\n");
702
703 activateStage();
704
705 _status = Active;
706 }
707}
708
709template <class Impl>
710void
711DefaultIEW<Impl>::resetEntries()
712{
713 instQueue.resetEntries();
714 ldstQueue.resetEntries();
715}
716
717template <class Impl>
718void
719DefaultIEW<Impl>::readStallSignals(ThreadID tid)
720{
721 if (fromCommit->commitBlock[tid]) {
722 stalls[tid].commit = true;
723 }
724
725 if (fromCommit->commitUnblock[tid]) {
726 assert(stalls[tid].commit);
727 stalls[tid].commit = false;
728 }
729}
730
731template <class Impl>
732bool
733DefaultIEW<Impl>::checkStall(ThreadID tid)
734{
735 bool ret_val(false);
736
737 if (stalls[tid].commit) {
738 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
739 ret_val = true;
740 } else if (instQueue.isFull(tid)) {
741 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
742 ret_val = true;
743 } else if (ldstQueue.isFull(tid)) {
744 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
745
746 if (ldstQueue.numLoads(tid) > 0 ) {
747
748 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
749 tid,ldstQueue.getLoadHeadSeqNum(tid));
750 }
751
752 if (ldstQueue.numStores(tid) > 0) {
753
754 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
755 tid,ldstQueue.getStoreHeadSeqNum(tid));
756 }
757
758 ret_val = true;
759 } else if (ldstQueue.isStalled(tid)) {
760 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
761 ret_val = true;
762 }
763
764 return ret_val;
765}
766
767template <class Impl>
768void
769DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
770{
771 // Check if there's a squash signal, squash if there is
772 // Check stall signals, block if there is.
773 // If status was Blocked
774 // if so then go to unblocking
775 // If status was Squashing
776 // check if squashing is not high. Switch to running this cycle.
777
778 readStallSignals(tid);
779
780 if (fromCommit->commitInfo[tid].squash) {
781 squash(tid);
782
783 if (dispatchStatus[tid] == Blocked ||
784 dispatchStatus[tid] == Unblocking) {
785 toRename->iewUnblock[tid] = true;
786 wroteToTimeBuffer = true;
787 }
788
789 dispatchStatus[tid] = Squashing;
790
791 fetchRedirect[tid] = false;
792 return;
793 }
794
795 if (fromCommit->commitInfo[tid].robSquashing) {
796 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
797
798 dispatchStatus[tid] = Squashing;
799
800 emptyRenameInsts(tid);
801 wroteToTimeBuffer = true;
802 return;
803 }
804
805 if (checkStall(tid)) {
806 block(tid);
807 dispatchStatus[tid] = Blocked;
808 return;
809 }
810
811 if (dispatchStatus[tid] == Blocked) {
812 // Status from previous cycle was blocked, but there are no more stall
813 // conditions. Switch over to unblocking.
814 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
815 tid);
816
817 dispatchStatus[tid] = Unblocking;
818
819 unblock(tid);
820
821 return;
822 }
823
824 if (dispatchStatus[tid] == Squashing) {
825 // Switch status to running if rename isn't being told to block or
826 // squash this cycle.
827 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
828 tid);
829
830 dispatchStatus[tid] = Running;
831
832 return;
833 }
834}
835
836template <class Impl>
837void
838DefaultIEW<Impl>::sortInsts()
839{
840 int insts_from_rename = fromRename->size;
841#ifdef DEBUG
842 for (ThreadID tid = 0; tid < numThreads; tid++)
843 assert(insts[tid].empty());
844#endif
845 for (int i = 0; i < insts_from_rename; ++i) {
846 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
847 }
848}
849
850template <class Impl>
851void
852DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
853{
854 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
855
856 while (!insts[tid].empty()) {
857
858 if (insts[tid].front()->isLoad() ||
859 insts[tid].front()->isStore() ) {
860 toRename->iewInfo[tid].dispatchedToLSQ++;
861 }
862
863 toRename->iewInfo[tid].dispatched++;
864
865 insts[tid].pop();
866 }
867}
868
869template <class Impl>
870void
871DefaultIEW<Impl>::wakeCPU()
872{
873 cpu->wakeCPU();
874}
875
876template <class Impl>
877void
878DefaultIEW<Impl>::activityThisCycle()
879{
880 DPRINTF(Activity, "Activity this cycle.\n");
881 cpu->activityThisCycle();
882}
883
884template <class Impl>
885inline void
886DefaultIEW<Impl>::activateStage()
887{
888 DPRINTF(Activity, "Activating stage.\n");
889 cpu->activateStage(O3CPU::IEWIdx);
890}
891
892template <class Impl>
893inline void
894DefaultIEW<Impl>::deactivateStage()
895{
896 DPRINTF(Activity, "Deactivating stage.\n");
897 cpu->deactivateStage(O3CPU::IEWIdx);
898}
899
900template<class Impl>
901void
902DefaultIEW<Impl>::dispatch(ThreadID tid)
903{
904 // If status is Running or idle,
905 // call dispatchInsts()
906 // If status is Unblocking,
907 // buffer any instructions coming from rename
908 // continue trying to empty skid buffer
909 // check if stall conditions have passed
910
911 if (dispatchStatus[tid] == Blocked) {
912 ++iewBlockCycles;
913
914 } else if (dispatchStatus[tid] == Squashing) {
915 ++iewSquashCycles;
916 }
917
918 // Dispatch should try to dispatch as many instructions as its bandwidth
919 // will allow, as long as it is not currently blocked.
920 if (dispatchStatus[tid] == Running ||
921 dispatchStatus[tid] == Idle) {
922 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
923 "dispatch.\n", tid);
924
925 dispatchInsts(tid);
926 } else if (dispatchStatus[tid] == Unblocking) {
927 // Make sure that the skid buffer has something in it if the
928 // status is unblocking.
929 assert(!skidsEmpty());
930
931 // If the status was unblocking, then instructions from the skid
932 // buffer were used. Remove those instructions and handle
933 // the rest of unblocking.
934 dispatchInsts(tid);
935
936 ++iewUnblockCycles;
937
938 if (validInstsFromRename()) {
939 // Add the current inputs to the skid buffer so they can be
940 // reprocessed when this stage unblocks.
941 skidInsert(tid);
942 }
943
944 unblock(tid);
945 }
946}
947
948template <class Impl>
949void
950DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
951{
952 // Obtain instructions from skid buffer if unblocking, or queue from rename
953 // otherwise.
954 std::queue<DynInstPtr> &insts_to_dispatch =
955 dispatchStatus[tid] == Unblocking ?
956 skidBuffer[tid] : insts[tid];
957
958 int insts_to_add = insts_to_dispatch.size();
959
960 DynInstPtr inst;
961 bool add_to_iq = false;
962 int dis_num_inst = 0;
963
964 // Loop through the instructions, putting them in the instruction
965 // queue.
966 for ( ; dis_num_inst < insts_to_add &&
967 dis_num_inst < dispatchWidth;
968 ++dis_num_inst)
969 {
970 inst = insts_to_dispatch.front();
971
972 if (dispatchStatus[tid] == Unblocking) {
973 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
974 "buffer\n", tid);
975 }
976
977 // Make sure there's a valid instruction there.
978 assert(inst);
979
980 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
981 "IQ.\n",
982 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
983
984 // Be sure to mark these instructions as ready so that the
985 // commit stage can go ahead and execute them, and mark
986 // them as issued so the IQ doesn't reprocess them.
987
988 // Check for squashed instructions.
989 if (inst->isSquashed()) {
990 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
991 "not adding to IQ.\n", tid);
992
993 ++iewDispSquashedInsts;
994
995 insts_to_dispatch.pop();
996
997 //Tell Rename That An Instruction has been processed
998 if (inst->isLoad() || inst->isStore()) {
999 toRename->iewInfo[tid].dispatchedToLSQ++;
1000 }
1001 toRename->iewInfo[tid].dispatched++;
1002
1003 continue;
1004 }
1005
1006 // Check for full conditions.
1007 if (instQueue.isFull(tid)) {
1008 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1009
1010 // Call function to start blocking.
1011 block(tid);
1012
1013 // Set unblock to false. Special case where we are using
1014 // skidbuffer (unblocking) instructions but then we still
1015 // get full in the IQ.
1016 toRename->iewUnblock[tid] = false;
1017
1018 ++iewIQFullEvents;
1019 break;
1020 } else if (ldstQueue.isFull(tid)) {
1021 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1022
1023 // Call function to start blocking.
1024 block(tid);
1025
1026 // Set unblock to false. Special case where we are using
1027 // skidbuffer (unblocking) instructions but then we still
1028 // get full in the IQ.
1029 toRename->iewUnblock[tid] = false;
1030
1031 ++iewLSQFullEvents;
1032 break;
1033 }
1034
1035 // Otherwise issue the instruction just fine.
1036 if (inst->isLoad()) {
1037 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1038 "encountered, adding to LSQ.\n", tid);
1039
1040 // Reserve a spot in the load store queue for this
1041 // memory access.
1042 ldstQueue.insertLoad(inst);
1043
1044 ++iewDispLoadInsts;
1045
1046 add_to_iq = true;
1047
1048 toRename->iewInfo[tid].dispatchedToLSQ++;
1049 } else if (inst->isStore()) {
1050 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1051 "encountered, adding to LSQ.\n", tid);
1052
1053 ldstQueue.insertStore(inst);
1054
1055 ++iewDispStoreInsts;
1056
1057 if (inst->isStoreConditional()) {
1058 // Store conditionals need to be set as "canCommit()"
1059 // so that commit can process them when they reach the
1060 // head of commit.
1061 // @todo: This is somewhat specific to Alpha.
1062 inst->setCanCommit();
1063 instQueue.insertNonSpec(inst);
1064 add_to_iq = false;
1065
1066 ++iewDispNonSpecInsts;
1067 } else {
1068 add_to_iq = true;
1069 }
1070
1071 toRename->iewInfo[tid].dispatchedToLSQ++;
1072 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1073 // Same as non-speculative stores.
1074 inst->setCanCommit();
1075 instQueue.insertBarrier(inst);
1076 add_to_iq = false;
1077 } else if (inst->isNop()) {
1078 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1079 "skipping.\n", tid);
1080
1081 inst->setIssued();
1082 inst->setExecuted();
1083 inst->setCanCommit();
1084
1085 instQueue.recordProducer(inst);
1086
1087 iewExecutedNop[tid]++;
1088
1089 add_to_iq = false;
1090 } else if (inst->isExecuted()) {
1091 assert(0 && "Instruction shouldn't be executed.\n");
1092 DPRINTF(IEW, "Issue: Executed branch encountered, "
1093 "skipping.\n");
1094
1095 inst->setIssued();
1096 inst->setCanCommit();
1097
1098 instQueue.recordProducer(inst);
1099
1100 add_to_iq = false;
1101 } else {
1102 add_to_iq = true;
1103 }
1104 if (inst->isNonSpeculative()) {
1105 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1106 "encountered, skipping.\n", tid);
1107
1108 // Same as non-speculative stores.
1109 inst->setCanCommit();
1110
1111 // Specifically insert it as nonspeculative.
1112 instQueue.insertNonSpec(inst);
1113
1114 ++iewDispNonSpecInsts;
1115
1116 add_to_iq = false;
1117 }
1118
1119 // If the instruction queue is not full, then add the
1120 // instruction.
1121 if (add_to_iq) {
1122 instQueue.insert(inst);
1123 }
1124
1125 insts_to_dispatch.pop();
1126
1127 toRename->iewInfo[tid].dispatched++;
1128
1129 ++iewDispatchedInsts;
1130 }
1131
1132 if (!insts_to_dispatch.empty()) {
1133 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1134 block(tid);
1135 toRename->iewUnblock[tid] = false;
1136 }
1137
1138 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1139 dispatchStatus[tid] = Running;
1140
1141 updatedQueues = true;
1142 }
1143
1144 dis_num_inst = 0;
1145}
1146
1147template <class Impl>
1148void
1149DefaultIEW<Impl>::printAvailableInsts()
1150{
1151 int inst = 0;
1152
1153 std::cout << "Available Instructions: ";
1154
1155 while (fromIssue->insts[inst]) {
1156
1157 if (inst%3==0) std::cout << "\n\t";
1158
1159 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1160 << " TN: " << fromIssue->insts[inst]->threadNumber
1161 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1162
1163 inst++;
1164
1165 }
1166
1167 std::cout << "\n";
1168}
1169
1170template <class Impl>
1171void
1172DefaultIEW<Impl>::executeInsts()
1173{
1174 wbNumInst = 0;
1175 wbCycle = 0;
1176
1177 list<ThreadID>::iterator threads = activeThreads->begin();
1178 list<ThreadID>::iterator end = activeThreads->end();
1179
1180 while (threads != end) {
1181 ThreadID tid = *threads++;
1182 fetchRedirect[tid] = false;
1183 }
1184
1185 // Uncomment this if you want to see all available instructions.
1186 // @todo This doesn't actually work anymore, we should fix it.
1187// printAvailableInsts();
1188
1189 // Execute/writeback any instructions that are available.
1190 int insts_to_execute = fromIssue->size;
1191 int inst_num = 0;
1192 for (; inst_num < insts_to_execute;
1193 ++inst_num) {
1194
1195 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1196
1197 DynInstPtr inst = instQueue.getInstToExecute();
1198
1199 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1200 inst->pcState(), inst->threadNumber,inst->seqNum);
1201
1202 // Check if the instruction is squashed; if so then skip it
1203 if (inst->isSquashed()) {
1204 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1205
1206 // Consider this instruction executed so that commit can go
1207 // ahead and retire the instruction.
1208 inst->setExecuted();
1209
1210 // Not sure if I should set this here or just let commit try to
1211 // commit any squashed instructions. I like the latter a bit more.
1212 inst->setCanCommit();
1213
1214 ++iewExecSquashedInsts;
1215
1216 decrWb(inst->seqNum);
1217 continue;
1218 }
1219
1220 Fault fault = NoFault;
1221
1222 // Execute instruction.
1223 // Note that if the instruction faults, it will be handled
1224 // at the commit stage.
1225 if (inst->isMemRef() &&
1226 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1227 DPRINTF(IEW, "Execute: Calculating address for memory "
1228 "reference.\n");
1229
1230 // Tell the LDSTQ to execute this instruction (if it is a load).
1231 if (inst->isLoad()) {
1232 // Loads will mark themselves as executed, and their writeback
1233 // event adds the instruction to the queue to commit
1234 fault = ldstQueue.executeLoad(inst);
1235 } else if (inst->isStore()) {
1236 fault = ldstQueue.executeStore(inst);
1237
1238 // If the store had a fault then it may not have a mem req
1239 if (fault != NoFault || inst->readPredicate() == false ||
1240 !inst->isStoreConditional()) {
1241 // If the instruction faulted, then we need to send it along
1242 // to commit without the instruction completing.
1243 // Send this instruction to commit, also make sure iew stage
1244 // realizes there is activity.
1245 inst->setExecuted();
1246 instToCommit(inst);
1247 activityThisCycle();
1248 }
1249
1250 // Store conditionals will mark themselves as
1251 // executed, and their writeback event will add the
1252 // instruction to the queue to commit.
1253 } else {
1254 panic("Unexpected memory type!\n");
1255 }
1256
1257 } else {
1258 // If the instruction has already faulted, then skip executing it.
1259 // Such case can happen when it faulted during ITLB translation.
1260 // If we execute the instruction (even if it's a nop) the fault
1261 // will be replaced and we will lose it.
1262 if (inst->getFault() == NoFault) {
1263 inst->execute();
|
1264 }
1265
1266 inst->setExecuted();
1267
1268 instToCommit(inst);
1269 }
1270
1271 updateExeInstStats(inst);
1272
1273 // Check if branch prediction was correct, if not then we need
1274 // to tell commit to squash in flight instructions. Only
1275 // handle this if there hasn't already been something that
1276 // redirects fetch in this group of instructions.
1277
1278 // This probably needs to prioritize the redirects if a different
1279 // scheduler is used. Currently the scheduler schedules the oldest
1280 // instruction first, so the branch resolution order will be correct.
1281 ThreadID tid = inst->threadNumber;
1282
1283 if (!fetchRedirect[tid] ||
1284 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1285
1286 if (inst->mispredicted()) {
1287 fetchRedirect[tid] = true;
1288
1289 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1290 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1291 inst->predInstAddr(), inst->predNextInstAddr());
1292 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1293 inst->pcState(), inst->nextInstAddr());
1294 // If incorrect, then signal the ROB that it must be squashed.
1295 squashDueToBranch(inst, tid);
1296
1297 if (inst->readPredTaken()) {
1298 predictedTakenIncorrect++;
1299 } else {
1300 predictedNotTakenIncorrect++;
1301 }
1302 } else if (ldstQueue.violation(tid)) {
1303 assert(inst->isMemRef());
1304 // If there was an ordering violation, then get the
1305 // DynInst that caused the violation. Note that this
1306 // clears the violation signal.
1307 DynInstPtr violator;
1308 violator = ldstQueue.getMemDepViolator(tid);
1309
1310 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1311 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1312 violator->pcState(), violator->seqNum,
1313 inst->pcState(), inst->seqNum, inst->physEffAddr);
1314
1315 fetchRedirect[tid] = true;
1316
1317 // Tell the instruction queue that a violation has occured.
1318 instQueue.violation(inst, violator);
1319
1320 // Squash.
1321 squashDueToMemOrder(inst,tid);
1322
1323 ++memOrderViolationEvents;
1324 } else if (ldstQueue.loadBlocked(tid) &&
1325 !ldstQueue.isLoadBlockedHandled(tid)) {
1326 fetchRedirect[tid] = true;
1327
1328 DPRINTF(IEW, "Load operation couldn't execute because the "
1329 "memory system is blocked. PC: %s [sn:%lli]\n",
1330 inst->pcState(), inst->seqNum);
1331
1332 squashDueToMemBlocked(inst, tid);
1333 }
1334 } else {
1335 // Reset any state associated with redirects that will not
1336 // be used.
1337 if (ldstQueue.violation(tid)) {
1338 assert(inst->isMemRef());
1339
1340 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1341
1342 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1343 "%s, inst PC: %s. Addr is: %#x.\n",
1344 violator->pcState(), inst->pcState(),
1345 inst->physEffAddr);
1346 DPRINTF(IEW, "Violation will not be handled because "
1347 "already squashing\n");
1348
1349 ++memOrderViolationEvents;
1350 }
1351 if (ldstQueue.loadBlocked(tid) &&
1352 !ldstQueue.isLoadBlockedHandled(tid)) {
1353 DPRINTF(IEW, "Load operation couldn't execute because the "
1354 "memory system is blocked. PC: %s [sn:%lli]\n",
1355 inst->pcState(), inst->seqNum);
1356 DPRINTF(IEW, "Blocked load will not be handled because "
1357 "already squashing\n");
1358
1359 ldstQueue.setLoadBlockedHandled(tid);
1360 }
1361
1362 }
1363 }
1364
1365 // Update and record activity if we processed any instructions.
1366 if (inst_num) {
1367 if (exeStatus == Idle) {
1368 exeStatus = Running;
1369 }
1370
1371 updatedQueues = true;
1372
1373 cpu->activityThisCycle();
1374 }
1375
1376 // Need to reset this in case a writeback event needs to write into the
1377 // iew queue. That way the writeback event will write into the correct
1378 // spot in the queue.
1379 wbNumInst = 0;
1380}
1381
1382template <class Impl>
1383void
1384DefaultIEW<Impl>::writebackInsts()
1385{
1386 // Loop through the head of the time buffer and wake any
1387 // dependents. These instructions are about to write back. Also
1388 // mark scoreboard that this instruction is finally complete.
1389 // Either have IEW have direct access to scoreboard, or have this
1390 // as part of backwards communication.
1391 for (int inst_num = 0; inst_num < wbWidth &&
1392 toCommit->insts[inst_num]; inst_num++) {
1393 DynInstPtr inst = toCommit->insts[inst_num];
1394 ThreadID tid = inst->threadNumber;
1395
1396 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1397 inst->seqNum, inst->pcState());
1398
1399 iewInstsToCommit[tid]++;
1400
1401 // Some instructions will be sent to commit without having
1402 // executed because they need commit to handle them.
1403 // E.g. Uncached loads have not actually executed when they
1404 // are first sent to commit. Instead commit must tell the LSQ
1405 // when it's ready to execute the uncached load.
1406 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1407 int dependents = instQueue.wakeDependents(inst);
1408
1409 for (int i = 0; i < inst->numDestRegs(); i++) {
1410 //mark as Ready
1411 DPRINTF(IEW,"Setting Destination Register %i\n",
1412 inst->renamedDestRegIdx(i));
1413 scoreboard->setReg(inst->renamedDestRegIdx(i));
1414 }
1415
1416 if (dependents) {
1417 producerInst[tid]++;
1418 consumerInst[tid]+= dependents;
1419 }
1420 writebackCount[tid]++;
1421 }
1422
1423 decrWb(inst->seqNum);
1424 }
1425}
1426
1427template<class Impl>
1428void
1429DefaultIEW<Impl>::tick()
1430{
1431 wbNumInst = 0;
1432 wbCycle = 0;
1433
1434 wroteToTimeBuffer = false;
1435 updatedQueues = false;
1436
1437 sortInsts();
1438
1439 // Free function units marked as being freed this cycle.
1440 fuPool->processFreeUnits();
1441
1442 list<ThreadID>::iterator threads = activeThreads->begin();
1443 list<ThreadID>::iterator end = activeThreads->end();
1444
1445 // Check stall and squash signals, dispatch any instructions.
1446 while (threads != end) {
1447 ThreadID tid = *threads++;
1448
1449 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1450
1451 checkSignalsAndUpdate(tid);
1452 dispatch(tid);
1453 }
1454
1455 if (exeStatus != Squashing) {
1456 executeInsts();
1457
1458 writebackInsts();
1459
1460 // Have the instruction queue try to schedule any ready instructions.
1461 // (In actuality, this scheduling is for instructions that will
1462 // be executed next cycle.)
1463 instQueue.scheduleReadyInsts();
1464
1465 // Also should advance its own time buffers if the stage ran.
1466 // Not the best place for it, but this works (hopefully).
1467 issueToExecQueue.advance();
1468 }
1469
1470 bool broadcast_free_entries = false;
1471
1472 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1473 exeStatus = Idle;
1474 updateLSQNextCycle = false;
1475
1476 broadcast_free_entries = true;
1477 }
1478
1479 // Writeback any stores using any leftover bandwidth.
1480 ldstQueue.writebackStores();
1481
1482 // Check the committed load/store signals to see if there's a load
1483 // or store to commit. Also check if it's being told to execute a
1484 // nonspeculative instruction.
1485 // This is pretty inefficient...
1486
1487 threads = activeThreads->begin();
1488 while (threads != end) {
1489 ThreadID tid = (*threads++);
1490
1491 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1492
1493 // Update structures based on instructions committed.
1494 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1495 !fromCommit->commitInfo[tid].squash &&
1496 !fromCommit->commitInfo[tid].robSquashing) {
1497
1498 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1499
1500 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1501
1502 updateLSQNextCycle = true;
1503 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504 }
1505
1506 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1507
1508 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1509 if (fromCommit->commitInfo[tid].uncached) {
1510 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1511 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1512 } else {
1513 instQueue.scheduleNonSpec(
1514 fromCommit->commitInfo[tid].nonSpecSeqNum);
1515 }
1516 }
1517
1518 if (broadcast_free_entries) {
1519 toFetch->iewInfo[tid].iqCount =
1520 instQueue.getCount(tid);
1521 toFetch->iewInfo[tid].ldstqCount =
1522 ldstQueue.getCount(tid);
1523
1524 toRename->iewInfo[tid].usedIQ = true;
1525 toRename->iewInfo[tid].freeIQEntries =
1526 instQueue.numFreeEntries();
1527 toRename->iewInfo[tid].usedLSQ = true;
1528 toRename->iewInfo[tid].freeLSQEntries =
1529 ldstQueue.numFreeEntries(tid);
1530
1531 wroteToTimeBuffer = true;
1532 }
1533
1534 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1535 tid, toRename->iewInfo[tid].dispatched);
1536 }
1537
1538 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1539 "LSQ has %i free entries.\n",
1540 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1541 ldstQueue.numFreeEntries());
1542
1543 updateStatus();
1544
1545 if (wroteToTimeBuffer) {
1546 DPRINTF(Activity, "Activity this cycle.\n");
1547 cpu->activityThisCycle();
1548 }
1549}
1550
1551template <class Impl>
1552void
1553DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1554{
1555 ThreadID tid = inst->threadNumber;
1556
1557 //
1558 // Pick off the software prefetches
1559 //
1560#ifdef TARGET_ALPHA
1561 if (inst->isDataPrefetch())
1562 iewExecutedSwp[tid]++;
1563 else
1564 iewIewExecutedcutedInsts++;
1565#else
1566 iewExecutedInsts++;
1567#endif
1568
1569 //
1570 // Control operations
1571 //
1572 if (inst->isControl())
1573 iewExecutedBranches[tid]++;
1574
1575 //
1576 // Memory operations
1577 //
1578 if (inst->isMemRef()) {
1579 iewExecutedRefs[tid]++;
1580
1581 if (inst->isLoad()) {
1582 iewExecLoadInsts[tid]++;
1583 }
1584 }
1585}
1586
1587template <class Impl>
1588void
1589DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1590{
1591 ThreadID tid = inst->threadNumber;
1592
1593 if (!fetchRedirect[tid] ||
1594 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1595
1596 if (inst->mispredicted()) {
1597 fetchRedirect[tid] = true;
1598
1599 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1600 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1601 inst->predInstAddr(), inst->predNextInstAddr());
1602 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1603 " NPC: %#x.\n", inst->nextInstAddr(),
1604 inst->nextInstAddr());
1605 // If incorrect, then signal the ROB that it must be squashed.
1606 squashDueToBranch(inst, tid);
1607
1608 if (inst->readPredTaken()) {
1609 predictedTakenIncorrect++;
1610 } else {
1611 predictedNotTakenIncorrect++;
1612 }
1613 }
1614 }
1615}
| 1266 }
1267
1268 inst->setExecuted();
1269
1270 instToCommit(inst);
1271 }
1272
1273 updateExeInstStats(inst);
1274
1275 // Check if branch prediction was correct, if not then we need
1276 // to tell commit to squash in flight instructions. Only
1277 // handle this if there hasn't already been something that
1278 // redirects fetch in this group of instructions.
1279
1280 // This probably needs to prioritize the redirects if a different
1281 // scheduler is used. Currently the scheduler schedules the oldest
1282 // instruction first, so the branch resolution order will be correct.
1283 ThreadID tid = inst->threadNumber;
1284
1285 if (!fetchRedirect[tid] ||
1286 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1287
1288 if (inst->mispredicted()) {
1289 fetchRedirect[tid] = true;
1290
1291 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1292 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1293 inst->predInstAddr(), inst->predNextInstAddr());
1294 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1295 inst->pcState(), inst->nextInstAddr());
1296 // If incorrect, then signal the ROB that it must be squashed.
1297 squashDueToBranch(inst, tid);
1298
1299 if (inst->readPredTaken()) {
1300 predictedTakenIncorrect++;
1301 } else {
1302 predictedNotTakenIncorrect++;
1303 }
1304 } else if (ldstQueue.violation(tid)) {
1305 assert(inst->isMemRef());
1306 // If there was an ordering violation, then get the
1307 // DynInst that caused the violation. Note that this
1308 // clears the violation signal.
1309 DynInstPtr violator;
1310 violator = ldstQueue.getMemDepViolator(tid);
1311
1312 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1313 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1314 violator->pcState(), violator->seqNum,
1315 inst->pcState(), inst->seqNum, inst->physEffAddr);
1316
1317 fetchRedirect[tid] = true;
1318
1319 // Tell the instruction queue that a violation has occured.
1320 instQueue.violation(inst, violator);
1321
1322 // Squash.
1323 squashDueToMemOrder(inst,tid);
1324
1325 ++memOrderViolationEvents;
1326 } else if (ldstQueue.loadBlocked(tid) &&
1327 !ldstQueue.isLoadBlockedHandled(tid)) {
1328 fetchRedirect[tid] = true;
1329
1330 DPRINTF(IEW, "Load operation couldn't execute because the "
1331 "memory system is blocked. PC: %s [sn:%lli]\n",
1332 inst->pcState(), inst->seqNum);
1333
1334 squashDueToMemBlocked(inst, tid);
1335 }
1336 } else {
1337 // Reset any state associated with redirects that will not
1338 // be used.
1339 if (ldstQueue.violation(tid)) {
1340 assert(inst->isMemRef());
1341
1342 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1343
1344 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1345 "%s, inst PC: %s. Addr is: %#x.\n",
1346 violator->pcState(), inst->pcState(),
1347 inst->physEffAddr);
1348 DPRINTF(IEW, "Violation will not be handled because "
1349 "already squashing\n");
1350
1351 ++memOrderViolationEvents;
1352 }
1353 if (ldstQueue.loadBlocked(tid) &&
1354 !ldstQueue.isLoadBlockedHandled(tid)) {
1355 DPRINTF(IEW, "Load operation couldn't execute because the "
1356 "memory system is blocked. PC: %s [sn:%lli]\n",
1357 inst->pcState(), inst->seqNum);
1358 DPRINTF(IEW, "Blocked load will not be handled because "
1359 "already squashing\n");
1360
1361 ldstQueue.setLoadBlockedHandled(tid);
1362 }
1363
1364 }
1365 }
1366
1367 // Update and record activity if we processed any instructions.
1368 if (inst_num) {
1369 if (exeStatus == Idle) {
1370 exeStatus = Running;
1371 }
1372
1373 updatedQueues = true;
1374
1375 cpu->activityThisCycle();
1376 }
1377
1378 // Need to reset this in case a writeback event needs to write into the
1379 // iew queue. That way the writeback event will write into the correct
1380 // spot in the queue.
1381 wbNumInst = 0;
1382}
1383
1384template <class Impl>
1385void
1386DefaultIEW<Impl>::writebackInsts()
1387{
1388 // Loop through the head of the time buffer and wake any
1389 // dependents. These instructions are about to write back. Also
1390 // mark scoreboard that this instruction is finally complete.
1391 // Either have IEW have direct access to scoreboard, or have this
1392 // as part of backwards communication.
1393 for (int inst_num = 0; inst_num < wbWidth &&
1394 toCommit->insts[inst_num]; inst_num++) {
1395 DynInstPtr inst = toCommit->insts[inst_num];
1396 ThreadID tid = inst->threadNumber;
1397
1398 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1399 inst->seqNum, inst->pcState());
1400
1401 iewInstsToCommit[tid]++;
1402
1403 // Some instructions will be sent to commit without having
1404 // executed because they need commit to handle them.
1405 // E.g. Uncached loads have not actually executed when they
1406 // are first sent to commit. Instead commit must tell the LSQ
1407 // when it's ready to execute the uncached load.
1408 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1409 int dependents = instQueue.wakeDependents(inst);
1410
1411 for (int i = 0; i < inst->numDestRegs(); i++) {
1412 //mark as Ready
1413 DPRINTF(IEW,"Setting Destination Register %i\n",
1414 inst->renamedDestRegIdx(i));
1415 scoreboard->setReg(inst->renamedDestRegIdx(i));
1416 }
1417
1418 if (dependents) {
1419 producerInst[tid]++;
1420 consumerInst[tid]+= dependents;
1421 }
1422 writebackCount[tid]++;
1423 }
1424
1425 decrWb(inst->seqNum);
1426 }
1427}
1428
1429template<class Impl>
1430void
1431DefaultIEW<Impl>::tick()
1432{
1433 wbNumInst = 0;
1434 wbCycle = 0;
1435
1436 wroteToTimeBuffer = false;
1437 updatedQueues = false;
1438
1439 sortInsts();
1440
1441 // Free function units marked as being freed this cycle.
1442 fuPool->processFreeUnits();
1443
1444 list<ThreadID>::iterator threads = activeThreads->begin();
1445 list<ThreadID>::iterator end = activeThreads->end();
1446
1447 // Check stall and squash signals, dispatch any instructions.
1448 while (threads != end) {
1449 ThreadID tid = *threads++;
1450
1451 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1452
1453 checkSignalsAndUpdate(tid);
1454 dispatch(tid);
1455 }
1456
1457 if (exeStatus != Squashing) {
1458 executeInsts();
1459
1460 writebackInsts();
1461
1462 // Have the instruction queue try to schedule any ready instructions.
1463 // (In actuality, this scheduling is for instructions that will
1464 // be executed next cycle.)
1465 instQueue.scheduleReadyInsts();
1466
1467 // Also should advance its own time buffers if the stage ran.
1468 // Not the best place for it, but this works (hopefully).
1469 issueToExecQueue.advance();
1470 }
1471
1472 bool broadcast_free_entries = false;
1473
1474 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1475 exeStatus = Idle;
1476 updateLSQNextCycle = false;
1477
1478 broadcast_free_entries = true;
1479 }
1480
1481 // Writeback any stores using any leftover bandwidth.
1482 ldstQueue.writebackStores();
1483
1484 // Check the committed load/store signals to see if there's a load
1485 // or store to commit. Also check if it's being told to execute a
1486 // nonspeculative instruction.
1487 // This is pretty inefficient...
1488
1489 threads = activeThreads->begin();
1490 while (threads != end) {
1491 ThreadID tid = (*threads++);
1492
1493 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1494
1495 // Update structures based on instructions committed.
1496 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1497 !fromCommit->commitInfo[tid].squash &&
1498 !fromCommit->commitInfo[tid].robSquashing) {
1499
1500 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1501
1502 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1503
1504 updateLSQNextCycle = true;
1505 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1506 }
1507
1508 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1509
1510 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1511 if (fromCommit->commitInfo[tid].uncached) {
1512 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1513 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1514 } else {
1515 instQueue.scheduleNonSpec(
1516 fromCommit->commitInfo[tid].nonSpecSeqNum);
1517 }
1518 }
1519
1520 if (broadcast_free_entries) {
1521 toFetch->iewInfo[tid].iqCount =
1522 instQueue.getCount(tid);
1523 toFetch->iewInfo[tid].ldstqCount =
1524 ldstQueue.getCount(tid);
1525
1526 toRename->iewInfo[tid].usedIQ = true;
1527 toRename->iewInfo[tid].freeIQEntries =
1528 instQueue.numFreeEntries();
1529 toRename->iewInfo[tid].usedLSQ = true;
1530 toRename->iewInfo[tid].freeLSQEntries =
1531 ldstQueue.numFreeEntries(tid);
1532
1533 wroteToTimeBuffer = true;
1534 }
1535
1536 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1537 tid, toRename->iewInfo[tid].dispatched);
1538 }
1539
1540 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1541 "LSQ has %i free entries.\n",
1542 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1543 ldstQueue.numFreeEntries());
1544
1545 updateStatus();
1546
1547 if (wroteToTimeBuffer) {
1548 DPRINTF(Activity, "Activity this cycle.\n");
1549 cpu->activityThisCycle();
1550 }
1551}
1552
1553template <class Impl>
1554void
1555DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1556{
1557 ThreadID tid = inst->threadNumber;
1558
1559 //
1560 // Pick off the software prefetches
1561 //
1562#ifdef TARGET_ALPHA
1563 if (inst->isDataPrefetch())
1564 iewExecutedSwp[tid]++;
1565 else
1566 iewIewExecutedcutedInsts++;
1567#else
1568 iewExecutedInsts++;
1569#endif
1570
1571 //
1572 // Control operations
1573 //
1574 if (inst->isControl())
1575 iewExecutedBranches[tid]++;
1576
1577 //
1578 // Memory operations
1579 //
1580 if (inst->isMemRef()) {
1581 iewExecutedRefs[tid]++;
1582
1583 if (inst->isLoad()) {
1584 iewExecLoadInsts[tid]++;
1585 }
1586 }
1587}
1588
1589template <class Impl>
1590void
1591DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1592{
1593 ThreadID tid = inst->threadNumber;
1594
1595 if (!fetchRedirect[tid] ||
1596 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1597
1598 if (inst->mispredicted()) {
1599 fetchRedirect[tid] = true;
1600
1601 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1602 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1603 inst->predInstAddr(), inst->predNextInstAddr());
1604 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1605 " NPC: %#x.\n", inst->nextInstAddr(),
1606 inst->nextInstAddr());
1607 // If incorrect, then signal the ROB that it must be squashed.
1608 squashDueToBranch(inst, tid);
1609
1610 if (inst->readPredTaken()) {
1611 predictedTakenIncorrect++;
1612 } else {
1613 predictedNotTakenIncorrect++;
1614 }
1615 }
1616 }
1617}
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