1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40#include "params/DerivO3CPU.hh"
41
42template<class Impl>
43DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
44 : issueToExecQueue(params->backComSize, params->forwardComSize),
45 cpu(_cpu),
46 instQueue(_cpu, this, params),
47 ldstQueue(_cpu, this, params),
48 fuPool(params->fuPool),
49 commitToIEWDelay(params->commitToIEWDelay),
50 renameToIEWDelay(params->renameToIEWDelay),
51 issueToExecuteDelay(params->issueToExecuteDelay),
52 dispatchWidth(params->dispatchWidth),
53 issueWidth(params->issueWidth),
54 wbOutstanding(0),
55 wbWidth(params->wbWidth),
56 numThreads(params->numThreads),
57 switchedOut(false)
58{
59 _status = Active;
60 exeStatus = Running;
61 wbStatus = Idle;
62
63 // Setup wire to read instructions coming from issue.
64 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66 // Instruction queue needs the queue between issue and execute.
67 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69 for (int i=0; i < numThreads; i++) {
70 dispatchStatus[i] = Running;
71 stalls[i].commit = false;
72 fetchRedirect[i] = false;
73 }
74
75 wbMax = wbWidth * params->wbDepth;
76
77 updateLSQNextCycle = false;
78
79 ableToIssue = true;
80
81 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
82}
83
84template <class Impl>
85std::string
86DefaultIEW<Impl>::name() const
87{
88 return cpu->name() + ".iew";
89}
90
91template <class Impl>
92void
93DefaultIEW<Impl>::regStats()
94{
95 using namespace Stats;
96
97 instQueue.regStats();
98 ldstQueue.regStats();
99
100 iewIdleCycles
101 .name(name() + ".iewIdleCycles")
102 .desc("Number of cycles IEW is idle");
103
104 iewSquashCycles
105 .name(name() + ".iewSquashCycles")
106 .desc("Number of cycles IEW is squashing");
107
108 iewBlockCycles
109 .name(name() + ".iewBlockCycles")
110 .desc("Number of cycles IEW is blocking");
111
112 iewUnblockCycles
113 .name(name() + ".iewUnblockCycles")
114 .desc("Number of cycles IEW is unblocking");
115
116 iewDispatchedInsts
117 .name(name() + ".iewDispatchedInsts")
118 .desc("Number of instructions dispatched to IQ");
119
120 iewDispSquashedInsts
121 .name(name() + ".iewDispSquashedInsts")
122 .desc("Number of squashed instructions skipped by dispatch");
123
124 iewDispLoadInsts
125 .name(name() + ".iewDispLoadInsts")
126 .desc("Number of dispatched load instructions");
127
128 iewDispStoreInsts
129 .name(name() + ".iewDispStoreInsts")
130 .desc("Number of dispatched store instructions");
131
132 iewDispNonSpecInsts
133 .name(name() + ".iewDispNonSpecInsts")
134 .desc("Number of dispatched non-speculative instructions");
135
136 iewIQFullEvents
137 .name(name() + ".iewIQFullEvents")
138 .desc("Number of times the IQ has become full, causing a stall");
139
140 iewLSQFullEvents
141 .name(name() + ".iewLSQFullEvents")
142 .desc("Number of times the LSQ has become full, causing a stall");
143
144 memOrderViolationEvents
145 .name(name() + ".memOrderViolationEvents")
146 .desc("Number of memory order violations");
147
148 predictedTakenIncorrect
149 .name(name() + ".predictedTakenIncorrect")
150 .desc("Number of branches that were predicted taken incorrectly");
151
152 predictedNotTakenIncorrect
153 .name(name() + ".predictedNotTakenIncorrect")
154 .desc("Number of branches that were predicted not taken incorrectly");
155
156 branchMispredicts
157 .name(name() + ".branchMispredicts")
158 .desc("Number of branch mispredicts detected at execute");
159
160 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
161
162 iewExecutedInsts
163 .name(name() + ".iewExecutedInsts")
164 .desc("Number of executed instructions");
165
166 iewExecLoadInsts
167 .init(cpu->number_of_threads)
168 .name(name() + ".iewExecLoadInsts")
169 .desc("Number of load instructions executed")
170 .flags(total);
171
172 iewExecSquashedInsts
173 .name(name() + ".iewExecSquashedInsts")
174 .desc("Number of squashed instructions skipped in execute");
175
176 iewExecutedSwp
177 .init(cpu->number_of_threads)
178 .name(name() + ".EXEC:swp")
179 .desc("number of swp insts executed")
180 .flags(total);
181
182 iewExecutedNop
183 .init(cpu->number_of_threads)
184 .name(name() + ".EXEC:nop")
185 .desc("number of nop insts executed")
186 .flags(total);
187
188 iewExecutedRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".EXEC:refs")
191 .desc("number of memory reference insts executed")
192 .flags(total);
193
194 iewExecutedBranches
195 .init(cpu->number_of_threads)
196 .name(name() + ".EXEC:branches")
197 .desc("Number of branches executed")
198 .flags(total);
199
200 iewExecStoreInsts
201 .name(name() + ".EXEC:stores")
202 .desc("Number of stores executed")
203 .flags(total);
204 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
205
206 iewExecRate
207 .name(name() + ".EXEC:rate")
208 .desc("Inst execution rate")
209 .flags(total);
210
211 iewExecRate = iewExecutedInsts / cpu->numCycles;
212
213 iewInstsToCommit
214 .init(cpu->number_of_threads)
215 .name(name() + ".WB:sent")
216 .desc("cumulative count of insts sent to commit")
217 .flags(total);
218
219 writebackCount
220 .init(cpu->number_of_threads)
221 .name(name() + ".WB:count")
222 .desc("cumulative count of insts written-back")
223 .flags(total);
224
225 producerInst
226 .init(cpu->number_of_threads)
227 .name(name() + ".WB:producers")
228 .desc("num instructions producing a value")
229 .flags(total);
230
231 consumerInst
232 .init(cpu->number_of_threads)
233 .name(name() + ".WB:consumers")
234 .desc("num instructions consuming a value")
235 .flags(total);
236
237 wbPenalized
238 .init(cpu->number_of_threads)
239 .name(name() + ".WB:penalized")
240 .desc("number of instrctions required to write to 'other' IQ")
241 .flags(total);
242
243 wbPenalizedRate
244 .name(name() + ".WB:penalized_rate")
245 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
246 .flags(total);
247
248 wbPenalizedRate = wbPenalized / writebackCount;
249
250 wbFanout
251 .name(name() + ".WB:fanout")
252 .desc("average fanout of values written-back")
253 .flags(total);
254
255 wbFanout = producerInst / consumerInst;
256
257 wbRate
258 .name(name() + ".WB:rate")
259 .desc("insts written-back per cycle")
260 .flags(total);
261 wbRate = writebackCount / cpu->numCycles;
262}
263
264template<class Impl>
265void
266DefaultIEW<Impl>::initStage()
267{
268 for (int tid=0; tid < numThreads; tid++) {
269 toRename->iewInfo[tid].usedIQ = true;
270 toRename->iewInfo[tid].freeIQEntries =
271 instQueue.numFreeEntries(tid);
272
273 toRename->iewInfo[tid].usedLSQ = true;
274 toRename->iewInfo[tid].freeLSQEntries =
275 ldstQueue.numFreeEntries(tid);
276 }
277
278 cpu->activateStage(O3CPU::IEWIdx);
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
284{
285 timeBuffer = tb_ptr;
286
287 // Setup wire to read information from time buffer, from commit.
288 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
289
290 // Setup wire to write information back to previous stages.
291 toRename = timeBuffer->getWire(0);
292
293 toFetch = timeBuffer->getWire(0);
294
295 // Instruction queue also needs main time buffer.
296 instQueue.setTimeBuffer(tb_ptr);
297}
298
299template<class Impl>
300void
301DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
302{
303 renameQueue = rq_ptr;
304
305 // Setup wire to read information from rename queue.
306 fromRename = renameQueue->getWire(-renameToIEWDelay);
307}
308
309template<class Impl>
310void
311DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
312{
313 iewQueue = iq_ptr;
314
315 // Setup wire to write instructions to commit.
316 toCommit = iewQueue->getWire(0);
317}
318
319template<class Impl>
320void
321DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
322{
323 activeThreads = at_ptr;
324
325 ldstQueue.setActiveThreads(at_ptr);
326 instQueue.setActiveThreads(at_ptr);
327}
328
329template<class Impl>
330void
331DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
332{
333 scoreboard = sb_ptr;
334}
335
336template <class Impl>
337bool
338DefaultIEW<Impl>::drain()
339{
340 // IEW is ready to drain at any time.
341 cpu->signalDrained();
342 return true;
343}
344
345template <class Impl>
346void
347DefaultIEW<Impl>::resume()
348{
349}
350
351template <class Impl>
352void
353DefaultIEW<Impl>::switchOut()
354{
355 // Clear any state.
356 switchedOut = true;
357 assert(insts[0].empty());
358 assert(skidBuffer[0].empty());
359
360 instQueue.switchOut();
361 ldstQueue.switchOut();
362 fuPool->switchOut();
363
364 for (int i = 0; i < numThreads; i++) {
365 while (!insts[i].empty())
366 insts[i].pop();
367 while (!skidBuffer[i].empty())
368 skidBuffer[i].pop();
369 }
370}
371
372template <class Impl>
373void
374DefaultIEW<Impl>::takeOverFrom()
375{
376 // Reset all state.
377 _status = Active;
378 exeStatus = Running;
379 wbStatus = Idle;
380 switchedOut = false;
381
382 instQueue.takeOverFrom();
383 ldstQueue.takeOverFrom();
384 fuPool->takeOverFrom();
385
386 initStage();
387 cpu->activityThisCycle();
388
389 for (int i=0; i < numThreads; i++) {
390 dispatchStatus[i] = Running;
391 stalls[i].commit = false;
392 fetchRedirect[i] = false;
393 }
394
395 updateLSQNextCycle = false;
396
397 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
398 issueToExecQueue.advance();
399 }
400}
401
402template<class Impl>
403void
404DefaultIEW<Impl>::squash(unsigned tid)
405{
406 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
407 tid);
408
409 // Tell the IQ to start squashing.
410 instQueue.squash(tid);
411
412 // Tell the LDSTQ to start squashing.
413 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
414 updatedQueues = true;
415
416 // Clear the skid buffer in case it has any data in it.
417 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
418 tid, fromCommit->commitInfo[tid].doneSeqNum);
419
420 while (!skidBuffer[tid].empty()) {
421 if (skidBuffer[tid].front()->isLoad() ||
422 skidBuffer[tid].front()->isStore() ) {
423 toRename->iewInfo[tid].dispatchedToLSQ++;
424 }
425
426 toRename->iewInfo[tid].dispatched++;
427
428 skidBuffer[tid].pop();
429 }
430
431 emptyRenameInsts(tid);
432}
433
434template<class Impl>
435void
436DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
437{
438 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
439 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
440
441 toCommit->squash[tid] = true;
442 toCommit->squashedSeqNum[tid] = inst->seqNum;
443 toCommit->mispredPC[tid] = inst->readPC();
444 toCommit->branchMispredict[tid] = true;
445
446#if ISA_HAS_DELAY_SLOT
447 int instSize = sizeof(TheISA::MachInst);
448 toCommit->branchTaken[tid] =
449 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
450 (inst->readNextPC() == inst->readPC() + instSize ||
451 inst->readNextPC() == inst->readPC() + 2 * instSize));
452#else
453 toCommit->branchTaken[tid] = inst->readNextPC() !=
454 (inst->readPC() + sizeof(TheISA::MachInst));
455#endif
456 toCommit->nextPC[tid] = inst->readNextPC();
457 toCommit->nextNPC[tid] = inst->readNextNPC();
458 toCommit->nextMicroPC[tid] = inst->readNextMicroPC();
459
460 toCommit->includeSquashInst[tid] = false;
461
462 wroteToTimeBuffer = true;
463}
464
465template<class Impl>
466void
467DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
468{
469 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
470 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
471
472 toCommit->squash[tid] = true;
473 toCommit->squashedSeqNum[tid] = inst->seqNum;
474 toCommit->nextPC[tid] = inst->readNextPC();
475 toCommit->nextNPC[tid] = inst->readNextNPC();
476 toCommit->branchMispredict[tid] = false;
477
478 toCommit->includeSquashInst[tid] = false;
479
480 wroteToTimeBuffer = true;
481}
482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
488 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
489
490 toCommit->squash[tid] = true;
491 toCommit->squashedSeqNum[tid] = inst->seqNum;
492 toCommit->nextPC[tid] = inst->readPC();
493 toCommit->nextNPC[tid] = inst->readNextPC();
494 toCommit->branchMispredict[tid] = false;
495
496 // Must include the broadcasted SN in the squash.
497 toCommit->includeSquashInst[tid] = true;
498
499 ldstQueue.setLoadBlockedHandled(tid);
500
501 wroteToTimeBuffer = true;
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::block(unsigned tid)
507{
508 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
509
510 if (dispatchStatus[tid] != Blocked &&
511 dispatchStatus[tid] != Unblocking) {
512 toRename->iewBlock[tid] = true;
513 wroteToTimeBuffer = true;
514 }
515
516 // Add the current inputs to the skid buffer so they can be
517 // reprocessed when this stage unblocks.
518 skidInsert(tid);
519
520 dispatchStatus[tid] = Blocked;
521}
522
523template<class Impl>
524void
525DefaultIEW<Impl>::unblock(unsigned tid)
526{
527 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
528 "buffer %u.\n",tid, tid);
529
530 // If the skid bufffer is empty, signal back to previous stages to unblock.
531 // Also switch status to running.
532 if (skidBuffer[tid].empty()) {
533 toRename->iewUnblock[tid] = true;
534 wroteToTimeBuffer = true;
535 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
536 dispatchStatus[tid] = Running;
537 }
538}
539
540template<class Impl>
541void
542DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
543{
544 instQueue.wakeDependents(inst);
545}
546
547template<class Impl>
548void
549DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
550{
551 instQueue.rescheduleMemInst(inst);
552}
553
554template<class Impl>
555void
556DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
557{
558 instQueue.replayMemInst(inst);
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
564{
565 // This function should not be called after writebackInsts in a
566 // single cycle. That will cause problems with an instruction
567 // being added to the queue to commit without being processed by
568 // writebackInsts prior to being sent to commit.
569
570 // First check the time slot that this instruction will write
571 // to. If there are free write ports at the time, then go ahead
572 // and write the instruction to that time. If there are not,
573 // keep looking back to see where's the first time there's a
574 // free slot.
575 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
576 ++wbNumInst;
577 if (wbNumInst == wbWidth) {
578 ++wbCycle;
579 wbNumInst = 0;
580 }
581
582 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
583 }
584
585 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
586 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
587 // Add finished instruction to queue to commit.
588 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
589 (*iewQueue)[wbCycle].size++;
590}
591
592template <class Impl>
593unsigned
594DefaultIEW<Impl>::validInstsFromRename()
595{
596 unsigned inst_count = 0;
597
598 for (int i=0; i<fromRename->size; i++) {
599 if (!fromRename->insts[i]->isSquashed())
600 inst_count++;
601 }
602
603 return inst_count;
604}
605
606template<class Impl>
607void
608DefaultIEW<Impl>::skidInsert(unsigned tid)
609{
610 DynInstPtr inst = NULL;
611
612 while (!insts[tid].empty()) {
613 inst = insts[tid].front();
614
615 insts[tid].pop();
616
617 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
618 "dispatch skidBuffer %i\n",tid, inst->seqNum,
619 inst->readPC(),tid);
620
621 skidBuffer[tid].push(inst);
622 }
623
624 assert(skidBuffer[tid].size() <= skidBufferMax &&
625 "Skidbuffer Exceeded Max Size");
626}
627
628template<class Impl>
629int
630DefaultIEW<Impl>::skidCount()
631{
632 int max=0;
633
634 std::list<unsigned>::iterator threads = activeThreads->begin();
635 std::list<unsigned>::iterator end = activeThreads->end();
636
637 while (threads != end) {
638 unsigned tid = *threads++;
639 unsigned thread_count = skidBuffer[tid].size();
640 if (max < thread_count)
641 max = thread_count;
642 }
643
644 return max;
645}
646
647template<class Impl>
648bool
649DefaultIEW<Impl>::skidsEmpty()
650{
651 std::list<unsigned>::iterator threads = activeThreads->begin();
652 std::list<unsigned>::iterator end = activeThreads->end();
653
654 while (threads != end) {
655 unsigned tid = *threads++;
656
657 if (!skidBuffer[tid].empty())
658 return false;
659 }
660
661 return true;
662}
663
664template <class Impl>
665void
666DefaultIEW<Impl>::updateStatus()
667{
668 bool any_unblocking = false;
669
670 std::list<unsigned>::iterator threads = activeThreads->begin();
671 std::list<unsigned>::iterator end = activeThreads->end();
672
673 while (threads != end) {
674 unsigned tid = *threads++;
675
676 if (dispatchStatus[tid] == Unblocking) {
677 any_unblocking = true;
678 break;
679 }
680 }
681
682 // If there are no ready instructions waiting to be scheduled by the IQ,
683 // and there's no stores waiting to write back, and dispatch is not
684 // unblocking, then there is no internal activity for the IEW stage.
685 if (_status == Active && !instQueue.hasReadyInsts() &&
686 !ldstQueue.willWB() && !any_unblocking) {
687 DPRINTF(IEW, "IEW switching to idle\n");
688
689 deactivateStage();
690
691 _status = Inactive;
692 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
693 ldstQueue.willWB() ||
694 any_unblocking)) {
695 // Otherwise there is internal activity. Set to active.
696 DPRINTF(IEW, "IEW switching to active\n");
697
698 activateStage();
699
700 _status = Active;
701 }
702}
703
704template <class Impl>
705void
706DefaultIEW<Impl>::resetEntries()
707{
708 instQueue.resetEntries();
709 ldstQueue.resetEntries();
710}
711
712template <class Impl>
713void
714DefaultIEW<Impl>::readStallSignals(unsigned tid)
715{
716 if (fromCommit->commitBlock[tid]) {
717 stalls[tid].commit = true;
718 }
719
720 if (fromCommit->commitUnblock[tid]) {
721 assert(stalls[tid].commit);
722 stalls[tid].commit = false;
723 }
724}
725
726template <class Impl>
727bool
728DefaultIEW<Impl>::checkStall(unsigned tid)
729{
730 bool ret_val(false);
731
732 if (stalls[tid].commit) {
733 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
734 ret_val = true;
735 } else if (instQueue.isFull(tid)) {
736 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
737 ret_val = true;
738 } else if (ldstQueue.isFull(tid)) {
739 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
740
741 if (ldstQueue.numLoads(tid) > 0 ) {
742
743 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
744 tid,ldstQueue.getLoadHeadSeqNum(tid));
745 }
746
747 if (ldstQueue.numStores(tid) > 0) {
748
749 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
750 tid,ldstQueue.getStoreHeadSeqNum(tid));
751 }
752
753 ret_val = true;
754 } else if (ldstQueue.isStalled(tid)) {
755 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
756 ret_val = true;
757 }
758
759 return ret_val;
760}
761
762template <class Impl>
763void
764DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
765{
766 // Check if there's a squash signal, squash if there is
767 // Check stall signals, block if there is.
768 // If status was Blocked
769 // if so then go to unblocking
770 // If status was Squashing
771 // check if squashing is not high. Switch to running this cycle.
772
773 readStallSignals(tid);
774
775 if (fromCommit->commitInfo[tid].squash) {
776 squash(tid);
777
778 if (dispatchStatus[tid] == Blocked ||
779 dispatchStatus[tid] == Unblocking) {
780 toRename->iewUnblock[tid] = true;
781 wroteToTimeBuffer = true;
782 }
783
784 dispatchStatus[tid] = Squashing;
785
786 fetchRedirect[tid] = false;
787 return;
788 }
789
790 if (fromCommit->commitInfo[tid].robSquashing) {
791 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
792
793 dispatchStatus[tid] = Squashing;
794
795 emptyRenameInsts(tid);
796 wroteToTimeBuffer = true;
797 return;
798 }
799
800 if (checkStall(tid)) {
801 block(tid);
802 dispatchStatus[tid] = Blocked;
803 return;
804 }
805
806 if (dispatchStatus[tid] == Blocked) {
807 // Status from previous cycle was blocked, but there are no more stall
808 // conditions. Switch over to unblocking.
809 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
810 tid);
811
812 dispatchStatus[tid] = Unblocking;
813
814 unblock(tid);
815
816 return;
817 }
818
819 if (dispatchStatus[tid] == Squashing) {
820 // Switch status to running if rename isn't being told to block or
821 // squash this cycle.
822 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
823 tid);
824
825 dispatchStatus[tid] = Running;
826
827 return;
828 }
829}
830
831template <class Impl>
832void
833DefaultIEW<Impl>::sortInsts()
834{
835 int insts_from_rename = fromRename->size;
836#ifdef DEBUG
837 for (int i = 0; i < numThreads; i++)
838 assert(insts[i].empty());
839#endif
840 for (int i = 0; i < insts_from_rename; ++i) {
841 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
842 }
843}
844
845template <class Impl>
846void
847DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
848{
849 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
850
851 while (!insts[tid].empty()) {
852
853 if (insts[tid].front()->isLoad() ||
854 insts[tid].front()->isStore() ) {
855 toRename->iewInfo[tid].dispatchedToLSQ++;
856 }
857
858 toRename->iewInfo[tid].dispatched++;
859
860 insts[tid].pop();
861 }
862}
863
864template <class Impl>
865void
866DefaultIEW<Impl>::wakeCPU()
867{
868 cpu->wakeCPU();
869}
870
871template <class Impl>
872void
873DefaultIEW<Impl>::activityThisCycle()
874{
875 DPRINTF(Activity, "Activity this cycle.\n");
876 cpu->activityThisCycle();
877}
878
879template <class Impl>
880inline void
881DefaultIEW<Impl>::activateStage()
882{
883 DPRINTF(Activity, "Activating stage.\n");
884 cpu->activateStage(O3CPU::IEWIdx);
885}
886
887template <class Impl>
888inline void
889DefaultIEW<Impl>::deactivateStage()
890{
891 DPRINTF(Activity, "Deactivating stage.\n");
892 cpu->deactivateStage(O3CPU::IEWIdx);
893}
894
895template<class Impl>
896void
897DefaultIEW<Impl>::dispatch(unsigned tid)
898{
899 // If status is Running or idle,
900 // call dispatchInsts()
901 // If status is Unblocking,
902 // buffer any instructions coming from rename
903 // continue trying to empty skid buffer
904 // check if stall conditions have passed
905
906 if (dispatchStatus[tid] == Blocked) {
907 ++iewBlockCycles;
908
909 } else if (dispatchStatus[tid] == Squashing) {
910 ++iewSquashCycles;
911 }
912
913 // Dispatch should try to dispatch as many instructions as its bandwidth
914 // will allow, as long as it is not currently blocked.
915 if (dispatchStatus[tid] == Running ||
916 dispatchStatus[tid] == Idle) {
917 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
918 "dispatch.\n", tid);
919
920 dispatchInsts(tid);
921 } else if (dispatchStatus[tid] == Unblocking) {
922 // Make sure that the skid buffer has something in it if the
923 // status is unblocking.
924 assert(!skidsEmpty());
925
926 // If the status was unblocking, then instructions from the skid
927 // buffer were used. Remove those instructions and handle
928 // the rest of unblocking.
929 dispatchInsts(tid);
930
931 ++iewUnblockCycles;
932
933 if (validInstsFromRename()) {
934 // Add the current inputs to the skid buffer so they can be
935 // reprocessed when this stage unblocks.
936 skidInsert(tid);
937 }
938
939 unblock(tid);
940 }
941}
942
943template <class Impl>
944void
945DefaultIEW<Impl>::dispatchInsts(unsigned tid)
946{
947 // Obtain instructions from skid buffer if unblocking, or queue from rename
948 // otherwise.
949 std::queue<DynInstPtr> &insts_to_dispatch =
950 dispatchStatus[tid] == Unblocking ?
951 skidBuffer[tid] : insts[tid];
952
953 int insts_to_add = insts_to_dispatch.size();
954
955 DynInstPtr inst;
956 bool add_to_iq = false;
957 int dis_num_inst = 0;
958
959 // Loop through the instructions, putting them in the instruction
960 // queue.
961 for ( ; dis_num_inst < insts_to_add &&
962 dis_num_inst < dispatchWidth;
963 ++dis_num_inst)
964 {
965 inst = insts_to_dispatch.front();
966
967 if (dispatchStatus[tid] == Unblocking) {
968 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
969 "buffer\n", tid);
970 }
971
972 // Make sure there's a valid instruction there.
973 assert(inst);
974
975 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
976 "IQ.\n",
977 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
978
979 // Be sure to mark these instructions as ready so that the
980 // commit stage can go ahead and execute them, and mark
981 // them as issued so the IQ doesn't reprocess them.
982
983 // Check for squashed instructions.
984 if (inst->isSquashed()) {
985 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
986 "not adding to IQ.\n", tid);
987
988 ++iewDispSquashedInsts;
989
990 insts_to_dispatch.pop();
991
992 //Tell Rename That An Instruction has been processed
993 if (inst->isLoad() || inst->isStore()) {
994 toRename->iewInfo[tid].dispatchedToLSQ++;
995 }
996 toRename->iewInfo[tid].dispatched++;
997
998 continue;
999 }
1000
1001 // Check for full conditions.
1002 if (instQueue.isFull(tid)) {
1003 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1004
1005 // Call function to start blocking.
1006 block(tid);
1007
1008 // Set unblock to false. Special case where we are using
1009 // skidbuffer (unblocking) instructions but then we still
1010 // get full in the IQ.
1011 toRename->iewUnblock[tid] = false;
1012
1013 ++iewIQFullEvents;
1014 break;
1015 } else if (ldstQueue.isFull(tid)) {
1016 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1017
1018 // Call function to start blocking.
1019 block(tid);
1020
1021 // Set unblock to false. Special case where we are using
1022 // skidbuffer (unblocking) instructions but then we still
1023 // get full in the IQ.
1024 toRename->iewUnblock[tid] = false;
1025
1026 ++iewLSQFullEvents;
1027 break;
1028 }
1029
1030 // Otherwise issue the instruction just fine.
1031 if (inst->isLoad()) {
1032 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1033 "encountered, adding to LSQ.\n", tid);
1034
1035 // Reserve a spot in the load store queue for this
1036 // memory access.
1037 ldstQueue.insertLoad(inst);
1038
1039 ++iewDispLoadInsts;
1040
1041 add_to_iq = true;
1042
1043 toRename->iewInfo[tid].dispatchedToLSQ++;
1044 } else if (inst->isStore()) {
1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1046 "encountered, adding to LSQ.\n", tid);
1047
1048 ldstQueue.insertStore(inst);
1049
1050 ++iewDispStoreInsts;
1051
1052 if (inst->isStoreConditional()) {
1053 // Store conditionals need to be set as "canCommit()"
1054 // so that commit can process them when they reach the
1055 // head of commit.
1056 // @todo: This is somewhat specific to Alpha.
1057 inst->setCanCommit();
1058 instQueue.insertNonSpec(inst);
1059 add_to_iq = false;
1060
1061 ++iewDispNonSpecInsts;
1062 } else {
1063 add_to_iq = true;
1064 }
1065
1066 toRename->iewInfo[tid].dispatchedToLSQ++;
1067 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1068 // Same as non-speculative stores.
1069 inst->setCanCommit();
1070 instQueue.insertBarrier(inst);
1071 add_to_iq = false;
1072 } else if (inst->isNop()) {
1073 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1074 "skipping.\n", tid);
1075
1076 inst->setIssued();
1077 inst->setExecuted();
1078 inst->setCanCommit();
1079
1080 instQueue.recordProducer(inst);
1081
1082 iewExecutedNop[tid]++;
1083
1084 add_to_iq = false;
1085 } else if (inst->isExecuted()) {
1086 assert(0 && "Instruction shouldn't be executed.\n");
1087 DPRINTF(IEW, "Issue: Executed branch encountered, "
1088 "skipping.\n");
1089
1090 inst->setIssued();
1091 inst->setCanCommit();
1092
1093 instQueue.recordProducer(inst);
1094
1095 add_to_iq = false;
1096 } else {
1097 add_to_iq = true;
1098 }
1099 if (inst->isNonSpeculative()) {
1100 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1101 "encountered, skipping.\n", tid);
1102
1103 // Same as non-speculative stores.
1104 inst->setCanCommit();
1105
1106 // Specifically insert it as nonspeculative.
1107 instQueue.insertNonSpec(inst);
1108
1109 ++iewDispNonSpecInsts;
1110
1111 add_to_iq = false;
1112 }
1113
1114 // If the instruction queue is not full, then add the
1115 // instruction.
1116 if (add_to_iq) {
1117 instQueue.insert(inst);
1118 }
1119
1120 insts_to_dispatch.pop();
1121
1122 toRename->iewInfo[tid].dispatched++;
1123
1124 ++iewDispatchedInsts;
1125 }
1126
1127 if (!insts_to_dispatch.empty()) {
1128 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1129 block(tid);
1130 toRename->iewUnblock[tid] = false;
1131 }
1132
1133 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1134 dispatchStatus[tid] = Running;
1135
1136 updatedQueues = true;
1137 }
1138
1139 dis_num_inst = 0;
1140}
1141
1142template <class Impl>
1143void
1144DefaultIEW<Impl>::printAvailableInsts()
1145{
1146 int inst = 0;
1147
1148 std::cout << "Available Instructions: ";
1149
1150 while (fromIssue->insts[inst]) {
1151
1152 if (inst%3==0) std::cout << "\n\t";
1153
1154 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1155 << " TN: " << fromIssue->insts[inst]->threadNumber
1156 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1157
1158 inst++;
1159
1160 }
1161
1162 std::cout << "\n";
1163}
1164
1165template <class Impl>
1166void
1167DefaultIEW<Impl>::executeInsts()
1168{
1169 wbNumInst = 0;
1170 wbCycle = 0;
1171
1172 std::list<unsigned>::iterator threads = activeThreads->begin();
1173 std::list<unsigned>::iterator end = activeThreads->end();
1174
1175 while (threads != end) {
1176 unsigned tid = *threads++;
1177 fetchRedirect[tid] = false;
1178 }
1179
1180 // Uncomment this if you want to see all available instructions.
1181// printAvailableInsts();
1182
1183 // Execute/writeback any instructions that are available.
1184 int insts_to_execute = fromIssue->size;
1185 int inst_num = 0;
1186 for (; inst_num < insts_to_execute;
1187 ++inst_num) {
1188
1189 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1190
1191 DynInstPtr inst = instQueue.getInstToExecute();
1192
1193 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1194 inst->readPC(), inst->threadNumber,inst->seqNum);
1195
1196 // Check if the instruction is squashed; if so then skip it
1197 if (inst->isSquashed()) {
1198 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1199
1200 // Consider this instruction executed so that commit can go
1201 // ahead and retire the instruction.
1202 inst->setExecuted();
1203
1204 // Not sure if I should set this here or just let commit try to
1205 // commit any squashed instructions. I like the latter a bit more.
1206 inst->setCanCommit();
1207
1208 ++iewExecSquashedInsts;
1209
1210 decrWb(inst->seqNum);
1211 continue;
1212 }
1213
1214 Fault fault = NoFault;
1215
1216 // Execute instruction.
1217 // Note that if the instruction faults, it will be handled
1218 // at the commit stage.
1219 if (inst->isMemRef() &&
1220 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1221 DPRINTF(IEW, "Execute: Calculating address for memory "
1222 "reference.\n");
1223
1224 // Tell the LDSTQ to execute this instruction (if it is a load).
1225 if (inst->isLoad()) {
1226 // Loads will mark themselves as executed, and their writeback
1227 // event adds the instruction to the queue to commit
1228 fault = ldstQueue.executeLoad(inst);
1229 } else if (inst->isStore()) {
1230 fault = ldstQueue.executeStore(inst);
1231
1232 // If the store had a fault then it may not have a mem req
1233 if (!inst->isStoreConditional() && fault == NoFault) {
1234 inst->setExecuted();
1235
1236 instToCommit(inst);
1237 } else if (fault != NoFault) {
1238 // If the instruction faulted, then we need to send it along to commit
1239 // without the instruction completing.
1240 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1241 fault->name(), inst->seqNum);
1242
1243 // Send this instruction to commit, also make sure iew stage
1244 // realizes there is activity.
1245 inst->setExecuted();
1246
1247 instToCommit(inst);
1248 activityThisCycle();
1249 }
1250
1251 // Store conditionals will mark themselves as
1252 // executed, and their writeback event will add the
1253 // instruction to the queue to commit.
1254 } else {
1255 panic("Unexpected memory type!\n");
1256 }
1257
1258 } else {
1259 inst->execute();
1260
1261 inst->setExecuted();
1262
1263 instToCommit(inst);
1264 }
1265
1266 updateExeInstStats(inst);
1267
1268 // Check if branch prediction was correct, if not then we need
1269 // to tell commit to squash in flight instructions. Only
1270 // handle this if there hasn't already been something that
1271 // redirects fetch in this group of instructions.
1272
1273 // This probably needs to prioritize the redirects if a different
1274 // scheduler is used. Currently the scheduler schedules the oldest
1275 // instruction first, so the branch resolution order will be correct.
1276 unsigned tid = inst->threadNumber;
1277
1278 if (!fetchRedirect[tid] ||
1279 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1280
1281 if (inst->mispredicted()) {
1282 fetchRedirect[tid] = true;
1283
1284 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40#include "params/DerivO3CPU.hh"
41
42template<class Impl>
43DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
44 : issueToExecQueue(params->backComSize, params->forwardComSize),
45 cpu(_cpu),
46 instQueue(_cpu, this, params),
47 ldstQueue(_cpu, this, params),
48 fuPool(params->fuPool),
49 commitToIEWDelay(params->commitToIEWDelay),
50 renameToIEWDelay(params->renameToIEWDelay),
51 issueToExecuteDelay(params->issueToExecuteDelay),
52 dispatchWidth(params->dispatchWidth),
53 issueWidth(params->issueWidth),
54 wbOutstanding(0),
55 wbWidth(params->wbWidth),
56 numThreads(params->numThreads),
57 switchedOut(false)
58{
59 _status = Active;
60 exeStatus = Running;
61 wbStatus = Idle;
62
63 // Setup wire to read instructions coming from issue.
64 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66 // Instruction queue needs the queue between issue and execute.
67 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69 for (int i=0; i < numThreads; i++) {
70 dispatchStatus[i] = Running;
71 stalls[i].commit = false;
72 fetchRedirect[i] = false;
73 }
74
75 wbMax = wbWidth * params->wbDepth;
76
77 updateLSQNextCycle = false;
78
79 ableToIssue = true;
80
81 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
82}
83
84template <class Impl>
85std::string
86DefaultIEW<Impl>::name() const
87{
88 return cpu->name() + ".iew";
89}
90
91template <class Impl>
92void
93DefaultIEW<Impl>::regStats()
94{
95 using namespace Stats;
96
97 instQueue.regStats();
98 ldstQueue.regStats();
99
100 iewIdleCycles
101 .name(name() + ".iewIdleCycles")
102 .desc("Number of cycles IEW is idle");
103
104 iewSquashCycles
105 .name(name() + ".iewSquashCycles")
106 .desc("Number of cycles IEW is squashing");
107
108 iewBlockCycles
109 .name(name() + ".iewBlockCycles")
110 .desc("Number of cycles IEW is blocking");
111
112 iewUnblockCycles
113 .name(name() + ".iewUnblockCycles")
114 .desc("Number of cycles IEW is unblocking");
115
116 iewDispatchedInsts
117 .name(name() + ".iewDispatchedInsts")
118 .desc("Number of instructions dispatched to IQ");
119
120 iewDispSquashedInsts
121 .name(name() + ".iewDispSquashedInsts")
122 .desc("Number of squashed instructions skipped by dispatch");
123
124 iewDispLoadInsts
125 .name(name() + ".iewDispLoadInsts")
126 .desc("Number of dispatched load instructions");
127
128 iewDispStoreInsts
129 .name(name() + ".iewDispStoreInsts")
130 .desc("Number of dispatched store instructions");
131
132 iewDispNonSpecInsts
133 .name(name() + ".iewDispNonSpecInsts")
134 .desc("Number of dispatched non-speculative instructions");
135
136 iewIQFullEvents
137 .name(name() + ".iewIQFullEvents")
138 .desc("Number of times the IQ has become full, causing a stall");
139
140 iewLSQFullEvents
141 .name(name() + ".iewLSQFullEvents")
142 .desc("Number of times the LSQ has become full, causing a stall");
143
144 memOrderViolationEvents
145 .name(name() + ".memOrderViolationEvents")
146 .desc("Number of memory order violations");
147
148 predictedTakenIncorrect
149 .name(name() + ".predictedTakenIncorrect")
150 .desc("Number of branches that were predicted taken incorrectly");
151
152 predictedNotTakenIncorrect
153 .name(name() + ".predictedNotTakenIncorrect")
154 .desc("Number of branches that were predicted not taken incorrectly");
155
156 branchMispredicts
157 .name(name() + ".branchMispredicts")
158 .desc("Number of branch mispredicts detected at execute");
159
160 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
161
162 iewExecutedInsts
163 .name(name() + ".iewExecutedInsts")
164 .desc("Number of executed instructions");
165
166 iewExecLoadInsts
167 .init(cpu->number_of_threads)
168 .name(name() + ".iewExecLoadInsts")
169 .desc("Number of load instructions executed")
170 .flags(total);
171
172 iewExecSquashedInsts
173 .name(name() + ".iewExecSquashedInsts")
174 .desc("Number of squashed instructions skipped in execute");
175
176 iewExecutedSwp
177 .init(cpu->number_of_threads)
178 .name(name() + ".EXEC:swp")
179 .desc("number of swp insts executed")
180 .flags(total);
181
182 iewExecutedNop
183 .init(cpu->number_of_threads)
184 .name(name() + ".EXEC:nop")
185 .desc("number of nop insts executed")
186 .flags(total);
187
188 iewExecutedRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".EXEC:refs")
191 .desc("number of memory reference insts executed")
192 .flags(total);
193
194 iewExecutedBranches
195 .init(cpu->number_of_threads)
196 .name(name() + ".EXEC:branches")
197 .desc("Number of branches executed")
198 .flags(total);
199
200 iewExecStoreInsts
201 .name(name() + ".EXEC:stores")
202 .desc("Number of stores executed")
203 .flags(total);
204 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
205
206 iewExecRate
207 .name(name() + ".EXEC:rate")
208 .desc("Inst execution rate")
209 .flags(total);
210
211 iewExecRate = iewExecutedInsts / cpu->numCycles;
212
213 iewInstsToCommit
214 .init(cpu->number_of_threads)
215 .name(name() + ".WB:sent")
216 .desc("cumulative count of insts sent to commit")
217 .flags(total);
218
219 writebackCount
220 .init(cpu->number_of_threads)
221 .name(name() + ".WB:count")
222 .desc("cumulative count of insts written-back")
223 .flags(total);
224
225 producerInst
226 .init(cpu->number_of_threads)
227 .name(name() + ".WB:producers")
228 .desc("num instructions producing a value")
229 .flags(total);
230
231 consumerInst
232 .init(cpu->number_of_threads)
233 .name(name() + ".WB:consumers")
234 .desc("num instructions consuming a value")
235 .flags(total);
236
237 wbPenalized
238 .init(cpu->number_of_threads)
239 .name(name() + ".WB:penalized")
240 .desc("number of instrctions required to write to 'other' IQ")
241 .flags(total);
242
243 wbPenalizedRate
244 .name(name() + ".WB:penalized_rate")
245 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
246 .flags(total);
247
248 wbPenalizedRate = wbPenalized / writebackCount;
249
250 wbFanout
251 .name(name() + ".WB:fanout")
252 .desc("average fanout of values written-back")
253 .flags(total);
254
255 wbFanout = producerInst / consumerInst;
256
257 wbRate
258 .name(name() + ".WB:rate")
259 .desc("insts written-back per cycle")
260 .flags(total);
261 wbRate = writebackCount / cpu->numCycles;
262}
263
264template<class Impl>
265void
266DefaultIEW<Impl>::initStage()
267{
268 for (int tid=0; tid < numThreads; tid++) {
269 toRename->iewInfo[tid].usedIQ = true;
270 toRename->iewInfo[tid].freeIQEntries =
271 instQueue.numFreeEntries(tid);
272
273 toRename->iewInfo[tid].usedLSQ = true;
274 toRename->iewInfo[tid].freeLSQEntries =
275 ldstQueue.numFreeEntries(tid);
276 }
277
278 cpu->activateStage(O3CPU::IEWIdx);
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
284{
285 timeBuffer = tb_ptr;
286
287 // Setup wire to read information from time buffer, from commit.
288 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
289
290 // Setup wire to write information back to previous stages.
291 toRename = timeBuffer->getWire(0);
292
293 toFetch = timeBuffer->getWire(0);
294
295 // Instruction queue also needs main time buffer.
296 instQueue.setTimeBuffer(tb_ptr);
297}
298
299template<class Impl>
300void
301DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
302{
303 renameQueue = rq_ptr;
304
305 // Setup wire to read information from rename queue.
306 fromRename = renameQueue->getWire(-renameToIEWDelay);
307}
308
309template<class Impl>
310void
311DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
312{
313 iewQueue = iq_ptr;
314
315 // Setup wire to write instructions to commit.
316 toCommit = iewQueue->getWire(0);
317}
318
319template<class Impl>
320void
321DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
322{
323 activeThreads = at_ptr;
324
325 ldstQueue.setActiveThreads(at_ptr);
326 instQueue.setActiveThreads(at_ptr);
327}
328
329template<class Impl>
330void
331DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
332{
333 scoreboard = sb_ptr;
334}
335
336template <class Impl>
337bool
338DefaultIEW<Impl>::drain()
339{
340 // IEW is ready to drain at any time.
341 cpu->signalDrained();
342 return true;
343}
344
345template <class Impl>
346void
347DefaultIEW<Impl>::resume()
348{
349}
350
351template <class Impl>
352void
353DefaultIEW<Impl>::switchOut()
354{
355 // Clear any state.
356 switchedOut = true;
357 assert(insts[0].empty());
358 assert(skidBuffer[0].empty());
359
360 instQueue.switchOut();
361 ldstQueue.switchOut();
362 fuPool->switchOut();
363
364 for (int i = 0; i < numThreads; i++) {
365 while (!insts[i].empty())
366 insts[i].pop();
367 while (!skidBuffer[i].empty())
368 skidBuffer[i].pop();
369 }
370}
371
372template <class Impl>
373void
374DefaultIEW<Impl>::takeOverFrom()
375{
376 // Reset all state.
377 _status = Active;
378 exeStatus = Running;
379 wbStatus = Idle;
380 switchedOut = false;
381
382 instQueue.takeOverFrom();
383 ldstQueue.takeOverFrom();
384 fuPool->takeOverFrom();
385
386 initStage();
387 cpu->activityThisCycle();
388
389 for (int i=0; i < numThreads; i++) {
390 dispatchStatus[i] = Running;
391 stalls[i].commit = false;
392 fetchRedirect[i] = false;
393 }
394
395 updateLSQNextCycle = false;
396
397 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
398 issueToExecQueue.advance();
399 }
400}
401
402template<class Impl>
403void
404DefaultIEW<Impl>::squash(unsigned tid)
405{
406 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
407 tid);
408
409 // Tell the IQ to start squashing.
410 instQueue.squash(tid);
411
412 // Tell the LDSTQ to start squashing.
413 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
414 updatedQueues = true;
415
416 // Clear the skid buffer in case it has any data in it.
417 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
418 tid, fromCommit->commitInfo[tid].doneSeqNum);
419
420 while (!skidBuffer[tid].empty()) {
421 if (skidBuffer[tid].front()->isLoad() ||
422 skidBuffer[tid].front()->isStore() ) {
423 toRename->iewInfo[tid].dispatchedToLSQ++;
424 }
425
426 toRename->iewInfo[tid].dispatched++;
427
428 skidBuffer[tid].pop();
429 }
430
431 emptyRenameInsts(tid);
432}
433
434template<class Impl>
435void
436DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
437{
438 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
439 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
440
441 toCommit->squash[tid] = true;
442 toCommit->squashedSeqNum[tid] = inst->seqNum;
443 toCommit->mispredPC[tid] = inst->readPC();
444 toCommit->branchMispredict[tid] = true;
445
446#if ISA_HAS_DELAY_SLOT
447 int instSize = sizeof(TheISA::MachInst);
448 toCommit->branchTaken[tid] =
449 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
450 (inst->readNextPC() == inst->readPC() + instSize ||
451 inst->readNextPC() == inst->readPC() + 2 * instSize));
452#else
453 toCommit->branchTaken[tid] = inst->readNextPC() !=
454 (inst->readPC() + sizeof(TheISA::MachInst));
455#endif
456 toCommit->nextPC[tid] = inst->readNextPC();
457 toCommit->nextNPC[tid] = inst->readNextNPC();
458 toCommit->nextMicroPC[tid] = inst->readNextMicroPC();
459
460 toCommit->includeSquashInst[tid] = false;
461
462 wroteToTimeBuffer = true;
463}
464
465template<class Impl>
466void
467DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
468{
469 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
470 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
471
472 toCommit->squash[tid] = true;
473 toCommit->squashedSeqNum[tid] = inst->seqNum;
474 toCommit->nextPC[tid] = inst->readNextPC();
475 toCommit->nextNPC[tid] = inst->readNextNPC();
476 toCommit->branchMispredict[tid] = false;
477
478 toCommit->includeSquashInst[tid] = false;
479
480 wroteToTimeBuffer = true;
481}
482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
488 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
489
490 toCommit->squash[tid] = true;
491 toCommit->squashedSeqNum[tid] = inst->seqNum;
492 toCommit->nextPC[tid] = inst->readPC();
493 toCommit->nextNPC[tid] = inst->readNextPC();
494 toCommit->branchMispredict[tid] = false;
495
496 // Must include the broadcasted SN in the squash.
497 toCommit->includeSquashInst[tid] = true;
498
499 ldstQueue.setLoadBlockedHandled(tid);
500
501 wroteToTimeBuffer = true;
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::block(unsigned tid)
507{
508 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
509
510 if (dispatchStatus[tid] != Blocked &&
511 dispatchStatus[tid] != Unblocking) {
512 toRename->iewBlock[tid] = true;
513 wroteToTimeBuffer = true;
514 }
515
516 // Add the current inputs to the skid buffer so they can be
517 // reprocessed when this stage unblocks.
518 skidInsert(tid);
519
520 dispatchStatus[tid] = Blocked;
521}
522
523template<class Impl>
524void
525DefaultIEW<Impl>::unblock(unsigned tid)
526{
527 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
528 "buffer %u.\n",tid, tid);
529
530 // If the skid bufffer is empty, signal back to previous stages to unblock.
531 // Also switch status to running.
532 if (skidBuffer[tid].empty()) {
533 toRename->iewUnblock[tid] = true;
534 wroteToTimeBuffer = true;
535 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
536 dispatchStatus[tid] = Running;
537 }
538}
539
540template<class Impl>
541void
542DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
543{
544 instQueue.wakeDependents(inst);
545}
546
547template<class Impl>
548void
549DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
550{
551 instQueue.rescheduleMemInst(inst);
552}
553
554template<class Impl>
555void
556DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
557{
558 instQueue.replayMemInst(inst);
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
564{
565 // This function should not be called after writebackInsts in a
566 // single cycle. That will cause problems with an instruction
567 // being added to the queue to commit without being processed by
568 // writebackInsts prior to being sent to commit.
569
570 // First check the time slot that this instruction will write
571 // to. If there are free write ports at the time, then go ahead
572 // and write the instruction to that time. If there are not,
573 // keep looking back to see where's the first time there's a
574 // free slot.
575 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
576 ++wbNumInst;
577 if (wbNumInst == wbWidth) {
578 ++wbCycle;
579 wbNumInst = 0;
580 }
581
582 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
583 }
584
585 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
586 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
587 // Add finished instruction to queue to commit.
588 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
589 (*iewQueue)[wbCycle].size++;
590}
591
592template <class Impl>
593unsigned
594DefaultIEW<Impl>::validInstsFromRename()
595{
596 unsigned inst_count = 0;
597
598 for (int i=0; i<fromRename->size; i++) {
599 if (!fromRename->insts[i]->isSquashed())
600 inst_count++;
601 }
602
603 return inst_count;
604}
605
606template<class Impl>
607void
608DefaultIEW<Impl>::skidInsert(unsigned tid)
609{
610 DynInstPtr inst = NULL;
611
612 while (!insts[tid].empty()) {
613 inst = insts[tid].front();
614
615 insts[tid].pop();
616
617 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
618 "dispatch skidBuffer %i\n",tid, inst->seqNum,
619 inst->readPC(),tid);
620
621 skidBuffer[tid].push(inst);
622 }
623
624 assert(skidBuffer[tid].size() <= skidBufferMax &&
625 "Skidbuffer Exceeded Max Size");
626}
627
628template<class Impl>
629int
630DefaultIEW<Impl>::skidCount()
631{
632 int max=0;
633
634 std::list<unsigned>::iterator threads = activeThreads->begin();
635 std::list<unsigned>::iterator end = activeThreads->end();
636
637 while (threads != end) {
638 unsigned tid = *threads++;
639 unsigned thread_count = skidBuffer[tid].size();
640 if (max < thread_count)
641 max = thread_count;
642 }
643
644 return max;
645}
646
647template<class Impl>
648bool
649DefaultIEW<Impl>::skidsEmpty()
650{
651 std::list<unsigned>::iterator threads = activeThreads->begin();
652 std::list<unsigned>::iterator end = activeThreads->end();
653
654 while (threads != end) {
655 unsigned tid = *threads++;
656
657 if (!skidBuffer[tid].empty())
658 return false;
659 }
660
661 return true;
662}
663
664template <class Impl>
665void
666DefaultIEW<Impl>::updateStatus()
667{
668 bool any_unblocking = false;
669
670 std::list<unsigned>::iterator threads = activeThreads->begin();
671 std::list<unsigned>::iterator end = activeThreads->end();
672
673 while (threads != end) {
674 unsigned tid = *threads++;
675
676 if (dispatchStatus[tid] == Unblocking) {
677 any_unblocking = true;
678 break;
679 }
680 }
681
682 // If there are no ready instructions waiting to be scheduled by the IQ,
683 // and there's no stores waiting to write back, and dispatch is not
684 // unblocking, then there is no internal activity for the IEW stage.
685 if (_status == Active && !instQueue.hasReadyInsts() &&
686 !ldstQueue.willWB() && !any_unblocking) {
687 DPRINTF(IEW, "IEW switching to idle\n");
688
689 deactivateStage();
690
691 _status = Inactive;
692 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
693 ldstQueue.willWB() ||
694 any_unblocking)) {
695 // Otherwise there is internal activity. Set to active.
696 DPRINTF(IEW, "IEW switching to active\n");
697
698 activateStage();
699
700 _status = Active;
701 }
702}
703
704template <class Impl>
705void
706DefaultIEW<Impl>::resetEntries()
707{
708 instQueue.resetEntries();
709 ldstQueue.resetEntries();
710}
711
712template <class Impl>
713void
714DefaultIEW<Impl>::readStallSignals(unsigned tid)
715{
716 if (fromCommit->commitBlock[tid]) {
717 stalls[tid].commit = true;
718 }
719
720 if (fromCommit->commitUnblock[tid]) {
721 assert(stalls[tid].commit);
722 stalls[tid].commit = false;
723 }
724}
725
726template <class Impl>
727bool
728DefaultIEW<Impl>::checkStall(unsigned tid)
729{
730 bool ret_val(false);
731
732 if (stalls[tid].commit) {
733 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
734 ret_val = true;
735 } else if (instQueue.isFull(tid)) {
736 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
737 ret_val = true;
738 } else if (ldstQueue.isFull(tid)) {
739 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
740
741 if (ldstQueue.numLoads(tid) > 0 ) {
742
743 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
744 tid,ldstQueue.getLoadHeadSeqNum(tid));
745 }
746
747 if (ldstQueue.numStores(tid) > 0) {
748
749 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
750 tid,ldstQueue.getStoreHeadSeqNum(tid));
751 }
752
753 ret_val = true;
754 } else if (ldstQueue.isStalled(tid)) {
755 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
756 ret_val = true;
757 }
758
759 return ret_val;
760}
761
762template <class Impl>
763void
764DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
765{
766 // Check if there's a squash signal, squash if there is
767 // Check stall signals, block if there is.
768 // If status was Blocked
769 // if so then go to unblocking
770 // If status was Squashing
771 // check if squashing is not high. Switch to running this cycle.
772
773 readStallSignals(tid);
774
775 if (fromCommit->commitInfo[tid].squash) {
776 squash(tid);
777
778 if (dispatchStatus[tid] == Blocked ||
779 dispatchStatus[tid] == Unblocking) {
780 toRename->iewUnblock[tid] = true;
781 wroteToTimeBuffer = true;
782 }
783
784 dispatchStatus[tid] = Squashing;
785
786 fetchRedirect[tid] = false;
787 return;
788 }
789
790 if (fromCommit->commitInfo[tid].robSquashing) {
791 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
792
793 dispatchStatus[tid] = Squashing;
794
795 emptyRenameInsts(tid);
796 wroteToTimeBuffer = true;
797 return;
798 }
799
800 if (checkStall(tid)) {
801 block(tid);
802 dispatchStatus[tid] = Blocked;
803 return;
804 }
805
806 if (dispatchStatus[tid] == Blocked) {
807 // Status from previous cycle was blocked, but there are no more stall
808 // conditions. Switch over to unblocking.
809 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
810 tid);
811
812 dispatchStatus[tid] = Unblocking;
813
814 unblock(tid);
815
816 return;
817 }
818
819 if (dispatchStatus[tid] == Squashing) {
820 // Switch status to running if rename isn't being told to block or
821 // squash this cycle.
822 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
823 tid);
824
825 dispatchStatus[tid] = Running;
826
827 return;
828 }
829}
830
831template <class Impl>
832void
833DefaultIEW<Impl>::sortInsts()
834{
835 int insts_from_rename = fromRename->size;
836#ifdef DEBUG
837 for (int i = 0; i < numThreads; i++)
838 assert(insts[i].empty());
839#endif
840 for (int i = 0; i < insts_from_rename; ++i) {
841 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
842 }
843}
844
845template <class Impl>
846void
847DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
848{
849 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
850
851 while (!insts[tid].empty()) {
852
853 if (insts[tid].front()->isLoad() ||
854 insts[tid].front()->isStore() ) {
855 toRename->iewInfo[tid].dispatchedToLSQ++;
856 }
857
858 toRename->iewInfo[tid].dispatched++;
859
860 insts[tid].pop();
861 }
862}
863
864template <class Impl>
865void
866DefaultIEW<Impl>::wakeCPU()
867{
868 cpu->wakeCPU();
869}
870
871template <class Impl>
872void
873DefaultIEW<Impl>::activityThisCycle()
874{
875 DPRINTF(Activity, "Activity this cycle.\n");
876 cpu->activityThisCycle();
877}
878
879template <class Impl>
880inline void
881DefaultIEW<Impl>::activateStage()
882{
883 DPRINTF(Activity, "Activating stage.\n");
884 cpu->activateStage(O3CPU::IEWIdx);
885}
886
887template <class Impl>
888inline void
889DefaultIEW<Impl>::deactivateStage()
890{
891 DPRINTF(Activity, "Deactivating stage.\n");
892 cpu->deactivateStage(O3CPU::IEWIdx);
893}
894
895template<class Impl>
896void
897DefaultIEW<Impl>::dispatch(unsigned tid)
898{
899 // If status is Running or idle,
900 // call dispatchInsts()
901 // If status is Unblocking,
902 // buffer any instructions coming from rename
903 // continue trying to empty skid buffer
904 // check if stall conditions have passed
905
906 if (dispatchStatus[tid] == Blocked) {
907 ++iewBlockCycles;
908
909 } else if (dispatchStatus[tid] == Squashing) {
910 ++iewSquashCycles;
911 }
912
913 // Dispatch should try to dispatch as many instructions as its bandwidth
914 // will allow, as long as it is not currently blocked.
915 if (dispatchStatus[tid] == Running ||
916 dispatchStatus[tid] == Idle) {
917 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
918 "dispatch.\n", tid);
919
920 dispatchInsts(tid);
921 } else if (dispatchStatus[tid] == Unblocking) {
922 // Make sure that the skid buffer has something in it if the
923 // status is unblocking.
924 assert(!skidsEmpty());
925
926 // If the status was unblocking, then instructions from the skid
927 // buffer were used. Remove those instructions and handle
928 // the rest of unblocking.
929 dispatchInsts(tid);
930
931 ++iewUnblockCycles;
932
933 if (validInstsFromRename()) {
934 // Add the current inputs to the skid buffer so they can be
935 // reprocessed when this stage unblocks.
936 skidInsert(tid);
937 }
938
939 unblock(tid);
940 }
941}
942
943template <class Impl>
944void
945DefaultIEW<Impl>::dispatchInsts(unsigned tid)
946{
947 // Obtain instructions from skid buffer if unblocking, or queue from rename
948 // otherwise.
949 std::queue<DynInstPtr> &insts_to_dispatch =
950 dispatchStatus[tid] == Unblocking ?
951 skidBuffer[tid] : insts[tid];
952
953 int insts_to_add = insts_to_dispatch.size();
954
955 DynInstPtr inst;
956 bool add_to_iq = false;
957 int dis_num_inst = 0;
958
959 // Loop through the instructions, putting them in the instruction
960 // queue.
961 for ( ; dis_num_inst < insts_to_add &&
962 dis_num_inst < dispatchWidth;
963 ++dis_num_inst)
964 {
965 inst = insts_to_dispatch.front();
966
967 if (dispatchStatus[tid] == Unblocking) {
968 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
969 "buffer\n", tid);
970 }
971
972 // Make sure there's a valid instruction there.
973 assert(inst);
974
975 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
976 "IQ.\n",
977 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
978
979 // Be sure to mark these instructions as ready so that the
980 // commit stage can go ahead and execute them, and mark
981 // them as issued so the IQ doesn't reprocess them.
982
983 // Check for squashed instructions.
984 if (inst->isSquashed()) {
985 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
986 "not adding to IQ.\n", tid);
987
988 ++iewDispSquashedInsts;
989
990 insts_to_dispatch.pop();
991
992 //Tell Rename That An Instruction has been processed
993 if (inst->isLoad() || inst->isStore()) {
994 toRename->iewInfo[tid].dispatchedToLSQ++;
995 }
996 toRename->iewInfo[tid].dispatched++;
997
998 continue;
999 }
1000
1001 // Check for full conditions.
1002 if (instQueue.isFull(tid)) {
1003 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1004
1005 // Call function to start blocking.
1006 block(tid);
1007
1008 // Set unblock to false. Special case where we are using
1009 // skidbuffer (unblocking) instructions but then we still
1010 // get full in the IQ.
1011 toRename->iewUnblock[tid] = false;
1012
1013 ++iewIQFullEvents;
1014 break;
1015 } else if (ldstQueue.isFull(tid)) {
1016 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1017
1018 // Call function to start blocking.
1019 block(tid);
1020
1021 // Set unblock to false. Special case where we are using
1022 // skidbuffer (unblocking) instructions but then we still
1023 // get full in the IQ.
1024 toRename->iewUnblock[tid] = false;
1025
1026 ++iewLSQFullEvents;
1027 break;
1028 }
1029
1030 // Otherwise issue the instruction just fine.
1031 if (inst->isLoad()) {
1032 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1033 "encountered, adding to LSQ.\n", tid);
1034
1035 // Reserve a spot in the load store queue for this
1036 // memory access.
1037 ldstQueue.insertLoad(inst);
1038
1039 ++iewDispLoadInsts;
1040
1041 add_to_iq = true;
1042
1043 toRename->iewInfo[tid].dispatchedToLSQ++;
1044 } else if (inst->isStore()) {
1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1046 "encountered, adding to LSQ.\n", tid);
1047
1048 ldstQueue.insertStore(inst);
1049
1050 ++iewDispStoreInsts;
1051
1052 if (inst->isStoreConditional()) {
1053 // Store conditionals need to be set as "canCommit()"
1054 // so that commit can process them when they reach the
1055 // head of commit.
1056 // @todo: This is somewhat specific to Alpha.
1057 inst->setCanCommit();
1058 instQueue.insertNonSpec(inst);
1059 add_to_iq = false;
1060
1061 ++iewDispNonSpecInsts;
1062 } else {
1063 add_to_iq = true;
1064 }
1065
1066 toRename->iewInfo[tid].dispatchedToLSQ++;
1067 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1068 // Same as non-speculative stores.
1069 inst->setCanCommit();
1070 instQueue.insertBarrier(inst);
1071 add_to_iq = false;
1072 } else if (inst->isNop()) {
1073 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1074 "skipping.\n", tid);
1075
1076 inst->setIssued();
1077 inst->setExecuted();
1078 inst->setCanCommit();
1079
1080 instQueue.recordProducer(inst);
1081
1082 iewExecutedNop[tid]++;
1083
1084 add_to_iq = false;
1085 } else if (inst->isExecuted()) {
1086 assert(0 && "Instruction shouldn't be executed.\n");
1087 DPRINTF(IEW, "Issue: Executed branch encountered, "
1088 "skipping.\n");
1089
1090 inst->setIssued();
1091 inst->setCanCommit();
1092
1093 instQueue.recordProducer(inst);
1094
1095 add_to_iq = false;
1096 } else {
1097 add_to_iq = true;
1098 }
1099 if (inst->isNonSpeculative()) {
1100 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1101 "encountered, skipping.\n", tid);
1102
1103 // Same as non-speculative stores.
1104 inst->setCanCommit();
1105
1106 // Specifically insert it as nonspeculative.
1107 instQueue.insertNonSpec(inst);
1108
1109 ++iewDispNonSpecInsts;
1110
1111 add_to_iq = false;
1112 }
1113
1114 // If the instruction queue is not full, then add the
1115 // instruction.
1116 if (add_to_iq) {
1117 instQueue.insert(inst);
1118 }
1119
1120 insts_to_dispatch.pop();
1121
1122 toRename->iewInfo[tid].dispatched++;
1123
1124 ++iewDispatchedInsts;
1125 }
1126
1127 if (!insts_to_dispatch.empty()) {
1128 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1129 block(tid);
1130 toRename->iewUnblock[tid] = false;
1131 }
1132
1133 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1134 dispatchStatus[tid] = Running;
1135
1136 updatedQueues = true;
1137 }
1138
1139 dis_num_inst = 0;
1140}
1141
1142template <class Impl>
1143void
1144DefaultIEW<Impl>::printAvailableInsts()
1145{
1146 int inst = 0;
1147
1148 std::cout << "Available Instructions: ";
1149
1150 while (fromIssue->insts[inst]) {
1151
1152 if (inst%3==0) std::cout << "\n\t";
1153
1154 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1155 << " TN: " << fromIssue->insts[inst]->threadNumber
1156 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1157
1158 inst++;
1159
1160 }
1161
1162 std::cout << "\n";
1163}
1164
1165template <class Impl>
1166void
1167DefaultIEW<Impl>::executeInsts()
1168{
1169 wbNumInst = 0;
1170 wbCycle = 0;
1171
1172 std::list<unsigned>::iterator threads = activeThreads->begin();
1173 std::list<unsigned>::iterator end = activeThreads->end();
1174
1175 while (threads != end) {
1176 unsigned tid = *threads++;
1177 fetchRedirect[tid] = false;
1178 }
1179
1180 // Uncomment this if you want to see all available instructions.
1181// printAvailableInsts();
1182
1183 // Execute/writeback any instructions that are available.
1184 int insts_to_execute = fromIssue->size;
1185 int inst_num = 0;
1186 for (; inst_num < insts_to_execute;
1187 ++inst_num) {
1188
1189 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1190
1191 DynInstPtr inst = instQueue.getInstToExecute();
1192
1193 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1194 inst->readPC(), inst->threadNumber,inst->seqNum);
1195
1196 // Check if the instruction is squashed; if so then skip it
1197 if (inst->isSquashed()) {
1198 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1199
1200 // Consider this instruction executed so that commit can go
1201 // ahead and retire the instruction.
1202 inst->setExecuted();
1203
1204 // Not sure if I should set this here or just let commit try to
1205 // commit any squashed instructions. I like the latter a bit more.
1206 inst->setCanCommit();
1207
1208 ++iewExecSquashedInsts;
1209
1210 decrWb(inst->seqNum);
1211 continue;
1212 }
1213
1214 Fault fault = NoFault;
1215
1216 // Execute instruction.
1217 // Note that if the instruction faults, it will be handled
1218 // at the commit stage.
1219 if (inst->isMemRef() &&
1220 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1221 DPRINTF(IEW, "Execute: Calculating address for memory "
1222 "reference.\n");
1223
1224 // Tell the LDSTQ to execute this instruction (if it is a load).
1225 if (inst->isLoad()) {
1226 // Loads will mark themselves as executed, and their writeback
1227 // event adds the instruction to the queue to commit
1228 fault = ldstQueue.executeLoad(inst);
1229 } else if (inst->isStore()) {
1230 fault = ldstQueue.executeStore(inst);
1231
1232 // If the store had a fault then it may not have a mem req
1233 if (!inst->isStoreConditional() && fault == NoFault) {
1234 inst->setExecuted();
1235
1236 instToCommit(inst);
1237 } else if (fault != NoFault) {
1238 // If the instruction faulted, then we need to send it along to commit
1239 // without the instruction completing.
1240 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1241 fault->name(), inst->seqNum);
1242
1243 // Send this instruction to commit, also make sure iew stage
1244 // realizes there is activity.
1245 inst->setExecuted();
1246
1247 instToCommit(inst);
1248 activityThisCycle();
1249 }
1250
1251 // Store conditionals will mark themselves as
1252 // executed, and their writeback event will add the
1253 // instruction to the queue to commit.
1254 } else {
1255 panic("Unexpected memory type!\n");
1256 }
1257
1258 } else {
1259 inst->execute();
1260
1261 inst->setExecuted();
1262
1263 instToCommit(inst);
1264 }
1265
1266 updateExeInstStats(inst);
1267
1268 // Check if branch prediction was correct, if not then we need
1269 // to tell commit to squash in flight instructions. Only
1270 // handle this if there hasn't already been something that
1271 // redirects fetch in this group of instructions.
1272
1273 // This probably needs to prioritize the redirects if a different
1274 // scheduler is used. Currently the scheduler schedules the oldest
1275 // instruction first, so the branch resolution order will be correct.
1276 unsigned tid = inst->threadNumber;
1277
1278 if (!fetchRedirect[tid] ||
1279 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1280
1281 if (inst->mispredicted()) {
1282 fetchRedirect[tid] = true;
1283
1284 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
|
1286 inst->readPredPC(), inst->readPredNPC());
1287 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1288 " NPC: %#x.\n", inst->readNextPC(),
1289 inst->readNextNPC());
1290 // If incorrect, then signal the ROB that it must be squashed.
1291 squashDueToBranch(inst, tid);
1292
1293 if (inst->readPredTaken()) {
1294 predictedTakenIncorrect++;
1295 } else {
1296 predictedNotTakenIncorrect++;
1297 }
1298 } else if (ldstQueue.violation(tid)) {
1299 assert(inst->isMemRef());
1300 // If there was an ordering violation, then get the
1301 // DynInst that caused the violation. Note that this
1302 // clears the violation signal.
1303 DynInstPtr violator;
1304 violator = ldstQueue.getMemDepViolator(tid);
1305
1306 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1307 "%#x, inst PC: %#x. Addr is: %#x.\n",
1308 violator->readPC(), inst->readPC(), inst->physEffAddr);
1309
1310 // Ensure the violating instruction is older than
1311 // current squash
1312/* if (fetchRedirect[tid] &&
1313 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
1314 continue;
1315*/
1316 fetchRedirect[tid] = true;
1317
1318 // Tell the instruction queue that a violation has occured.
1319 instQueue.violation(inst, violator);
1320
1321 // Squash.
1322 squashDueToMemOrder(inst,tid);
1323
1324 ++memOrderViolationEvents;
1325 } else if (ldstQueue.loadBlocked(tid) &&
1326 !ldstQueue.isLoadBlockedHandled(tid)) {
1327 fetchRedirect[tid] = true;
1328
1329 DPRINTF(IEW, "Load operation couldn't execute because the "
1330 "memory system is blocked. PC: %#x [sn:%lli]\n",
1331 inst->readPC(), inst->seqNum);
1332
1333 squashDueToMemBlocked(inst, tid);
1334 }
1335 } else {
1336 // Reset any state associated with redirects that will not
1337 // be used.
1338 if (ldstQueue.violation(tid)) {
1339 assert(inst->isMemRef());
1340
1341 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1342
1343 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1344 "%#x, inst PC: %#x. Addr is: %#x.\n",
1345 violator->readPC(), inst->readPC(), inst->physEffAddr);
1346 DPRINTF(IEW, "Violation will not be handled because "
1347 "already squashing\n");
1348
1349 ++memOrderViolationEvents;
1350 }
1351 if (ldstQueue.loadBlocked(tid) &&
1352 !ldstQueue.isLoadBlockedHandled(tid)) {
1353 DPRINTF(IEW, "Load operation couldn't execute because the "
1354 "memory system is blocked. PC: %#x [sn:%lli]\n",
1355 inst->readPC(), inst->seqNum);
1356 DPRINTF(IEW, "Blocked load will not be handled because "
1357 "already squashing\n");
1358
1359 ldstQueue.setLoadBlockedHandled(tid);
1360 }
1361
1362 }
1363 }
1364
1365 // Update and record activity if we processed any instructions.
1366 if (inst_num) {
1367 if (exeStatus == Idle) {
1368 exeStatus = Running;
1369 }
1370
1371 updatedQueues = true;
1372
1373 cpu->activityThisCycle();
1374 }
1375
1376 // Need to reset this in case a writeback event needs to write into the
1377 // iew queue. That way the writeback event will write into the correct
1378 // spot in the queue.
1379 wbNumInst = 0;
1380}
1381
1382template <class Impl>
1383void
1384DefaultIEW<Impl>::writebackInsts()
1385{
1386 // Loop through the head of the time buffer and wake any
1387 // dependents. These instructions are about to write back. Also
1388 // mark scoreboard that this instruction is finally complete.
1389 // Either have IEW have direct access to scoreboard, or have this
1390 // as part of backwards communication.
1391 for (int inst_num = 0; inst_num < wbWidth &&
1392 toCommit->insts[inst_num]; inst_num++) {
1393 DynInstPtr inst = toCommit->insts[inst_num];
1394 int tid = inst->threadNumber;
1395
1396 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1397 inst->seqNum, inst->readPC());
1398
1399 iewInstsToCommit[tid]++;
1400
1401 // Some instructions will be sent to commit without having
1402 // executed because they need commit to handle them.
1403 // E.g. Uncached loads have not actually executed when they
1404 // are first sent to commit. Instead commit must tell the LSQ
1405 // when it's ready to execute the uncached load.
1406 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1407 int dependents = instQueue.wakeDependents(inst);
1408
1409 for (int i = 0; i < inst->numDestRegs(); i++) {
1410 //mark as Ready
1411 DPRINTF(IEW,"Setting Destination Register %i\n",
1412 inst->renamedDestRegIdx(i));
1413 scoreboard->setReg(inst->renamedDestRegIdx(i));
1414 }
1415
1416 if (dependents) {
1417 producerInst[tid]++;
1418 consumerInst[tid]+= dependents;
1419 }
1420 writebackCount[tid]++;
1421 }
1422
1423 decrWb(inst->seqNum);
1424 }
1425}
1426
1427template<class Impl>
1428void
1429DefaultIEW<Impl>::tick()
1430{
1431 wbNumInst = 0;
1432 wbCycle = 0;
1433
1434 wroteToTimeBuffer = false;
1435 updatedQueues = false;
1436
1437 sortInsts();
1438
1439 // Free function units marked as being freed this cycle.
1440 fuPool->processFreeUnits();
1441
1442 std::list<unsigned>::iterator threads = activeThreads->begin();
1443 std::list<unsigned>::iterator end = activeThreads->end();
1444
1445 // Check stall and squash signals, dispatch any instructions.
1446 while (threads != end) {
1447 unsigned tid = *threads++;
1448
1449 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1450
1451 checkSignalsAndUpdate(tid);
1452 dispatch(tid);
1453 }
1454
1455 if (exeStatus != Squashing) {
1456 executeInsts();
1457
1458 writebackInsts();
1459
1460 // Have the instruction queue try to schedule any ready instructions.
1461 // (In actuality, this scheduling is for instructions that will
1462 // be executed next cycle.)
1463 instQueue.scheduleReadyInsts();
1464
1465 // Also should advance its own time buffers if the stage ran.
1466 // Not the best place for it, but this works (hopefully).
1467 issueToExecQueue.advance();
1468 }
1469
1470 bool broadcast_free_entries = false;
1471
1472 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1473 exeStatus = Idle;
1474 updateLSQNextCycle = false;
1475
1476 broadcast_free_entries = true;
1477 }
1478
1479 // Writeback any stores using any leftover bandwidth.
1480 ldstQueue.writebackStores();
1481
1482 // Check the committed load/store signals to see if there's a load
1483 // or store to commit. Also check if it's being told to execute a
1484 // nonspeculative instruction.
1485 // This is pretty inefficient...
1486
1487 threads = activeThreads->begin();
1488 while (threads != end) {
1489 unsigned tid = (*threads++);
1490
1491 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1492
1493 // Update structures based on instructions committed.
1494 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1495 !fromCommit->commitInfo[tid].squash &&
1496 !fromCommit->commitInfo[tid].robSquashing) {
1497
1498 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1499
1500 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1501
1502 updateLSQNextCycle = true;
1503 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504 }
1505
1506 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1507
1508 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1509 if (fromCommit->commitInfo[tid].uncached) {
1510 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1511 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1512 } else {
1513 instQueue.scheduleNonSpec(
1514 fromCommit->commitInfo[tid].nonSpecSeqNum);
1515 }
1516 }
1517
1518 if (broadcast_free_entries) {
1519 toFetch->iewInfo[tid].iqCount =
1520 instQueue.getCount(tid);
1521 toFetch->iewInfo[tid].ldstqCount =
1522 ldstQueue.getCount(tid);
1523
1524 toRename->iewInfo[tid].usedIQ = true;
1525 toRename->iewInfo[tid].freeIQEntries =
1526 instQueue.numFreeEntries();
1527 toRename->iewInfo[tid].usedLSQ = true;
1528 toRename->iewInfo[tid].freeLSQEntries =
1529 ldstQueue.numFreeEntries(tid);
1530
1531 wroteToTimeBuffer = true;
1532 }
1533
1534 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1535 tid, toRename->iewInfo[tid].dispatched);
1536 }
1537
1538 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1539 "LSQ has %i free entries.\n",
1540 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1541 ldstQueue.numFreeEntries());
1542
1543 updateStatus();
1544
1545 if (wroteToTimeBuffer) {
1546 DPRINTF(Activity, "Activity this cycle.\n");
1547 cpu->activityThisCycle();
1548 }
1549}
1550
1551template <class Impl>
1552void
1553DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1554{
1555 int thread_number = inst->threadNumber;
1556
1557 //
1558 // Pick off the software prefetches
1559 //
1560#ifdef TARGET_ALPHA
1561 if (inst->isDataPrefetch())
1562 iewExecutedSwp[thread_number]++;
1563 else
1564 iewIewExecutedcutedInsts++;
1565#else
1566 iewExecutedInsts++;
1567#endif
1568
1569 //
1570 // Control operations
1571 //
1572 if (inst->isControl())
1573 iewExecutedBranches[thread_number]++;
1574
1575 //
1576 // Memory operations
1577 //
1578 if (inst->isMemRef()) {
1579 iewExecutedRefs[thread_number]++;
1580
1581 if (inst->isLoad()) {
1582 iewExecLoadInsts[thread_number]++;
1583 }
1584 }
1585}
| 1286 inst->readPredPC(), inst->readPredNPC());
1287 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1288 " NPC: %#x.\n", inst->readNextPC(),
1289 inst->readNextNPC());
1290 // If incorrect, then signal the ROB that it must be squashed.
1291 squashDueToBranch(inst, tid);
1292
1293 if (inst->readPredTaken()) {
1294 predictedTakenIncorrect++;
1295 } else {
1296 predictedNotTakenIncorrect++;
1297 }
1298 } else if (ldstQueue.violation(tid)) {
1299 assert(inst->isMemRef());
1300 // If there was an ordering violation, then get the
1301 // DynInst that caused the violation. Note that this
1302 // clears the violation signal.
1303 DynInstPtr violator;
1304 violator = ldstQueue.getMemDepViolator(tid);
1305
1306 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1307 "%#x, inst PC: %#x. Addr is: %#x.\n",
1308 violator->readPC(), inst->readPC(), inst->physEffAddr);
1309
1310 // Ensure the violating instruction is older than
1311 // current squash
1312/* if (fetchRedirect[tid] &&
1313 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
1314 continue;
1315*/
1316 fetchRedirect[tid] = true;
1317
1318 // Tell the instruction queue that a violation has occured.
1319 instQueue.violation(inst, violator);
1320
1321 // Squash.
1322 squashDueToMemOrder(inst,tid);
1323
1324 ++memOrderViolationEvents;
1325 } else if (ldstQueue.loadBlocked(tid) &&
1326 !ldstQueue.isLoadBlockedHandled(tid)) {
1327 fetchRedirect[tid] = true;
1328
1329 DPRINTF(IEW, "Load operation couldn't execute because the "
1330 "memory system is blocked. PC: %#x [sn:%lli]\n",
1331 inst->readPC(), inst->seqNum);
1332
1333 squashDueToMemBlocked(inst, tid);
1334 }
1335 } else {
1336 // Reset any state associated with redirects that will not
1337 // be used.
1338 if (ldstQueue.violation(tid)) {
1339 assert(inst->isMemRef());
1340
1341 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1342
1343 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1344 "%#x, inst PC: %#x. Addr is: %#x.\n",
1345 violator->readPC(), inst->readPC(), inst->physEffAddr);
1346 DPRINTF(IEW, "Violation will not be handled because "
1347 "already squashing\n");
1348
1349 ++memOrderViolationEvents;
1350 }
1351 if (ldstQueue.loadBlocked(tid) &&
1352 !ldstQueue.isLoadBlockedHandled(tid)) {
1353 DPRINTF(IEW, "Load operation couldn't execute because the "
1354 "memory system is blocked. PC: %#x [sn:%lli]\n",
1355 inst->readPC(), inst->seqNum);
1356 DPRINTF(IEW, "Blocked load will not be handled because "
1357 "already squashing\n");
1358
1359 ldstQueue.setLoadBlockedHandled(tid);
1360 }
1361
1362 }
1363 }
1364
1365 // Update and record activity if we processed any instructions.
1366 if (inst_num) {
1367 if (exeStatus == Idle) {
1368 exeStatus = Running;
1369 }
1370
1371 updatedQueues = true;
1372
1373 cpu->activityThisCycle();
1374 }
1375
1376 // Need to reset this in case a writeback event needs to write into the
1377 // iew queue. That way the writeback event will write into the correct
1378 // spot in the queue.
1379 wbNumInst = 0;
1380}
1381
1382template <class Impl>
1383void
1384DefaultIEW<Impl>::writebackInsts()
1385{
1386 // Loop through the head of the time buffer and wake any
1387 // dependents. These instructions are about to write back. Also
1388 // mark scoreboard that this instruction is finally complete.
1389 // Either have IEW have direct access to scoreboard, or have this
1390 // as part of backwards communication.
1391 for (int inst_num = 0; inst_num < wbWidth &&
1392 toCommit->insts[inst_num]; inst_num++) {
1393 DynInstPtr inst = toCommit->insts[inst_num];
1394 int tid = inst->threadNumber;
1395
1396 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1397 inst->seqNum, inst->readPC());
1398
1399 iewInstsToCommit[tid]++;
1400
1401 // Some instructions will be sent to commit without having
1402 // executed because they need commit to handle them.
1403 // E.g. Uncached loads have not actually executed when they
1404 // are first sent to commit. Instead commit must tell the LSQ
1405 // when it's ready to execute the uncached load.
1406 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1407 int dependents = instQueue.wakeDependents(inst);
1408
1409 for (int i = 0; i < inst->numDestRegs(); i++) {
1410 //mark as Ready
1411 DPRINTF(IEW,"Setting Destination Register %i\n",
1412 inst->renamedDestRegIdx(i));
1413 scoreboard->setReg(inst->renamedDestRegIdx(i));
1414 }
1415
1416 if (dependents) {
1417 producerInst[tid]++;
1418 consumerInst[tid]+= dependents;
1419 }
1420 writebackCount[tid]++;
1421 }
1422
1423 decrWb(inst->seqNum);
1424 }
1425}
1426
1427template<class Impl>
1428void
1429DefaultIEW<Impl>::tick()
1430{
1431 wbNumInst = 0;
1432 wbCycle = 0;
1433
1434 wroteToTimeBuffer = false;
1435 updatedQueues = false;
1436
1437 sortInsts();
1438
1439 // Free function units marked as being freed this cycle.
1440 fuPool->processFreeUnits();
1441
1442 std::list<unsigned>::iterator threads = activeThreads->begin();
1443 std::list<unsigned>::iterator end = activeThreads->end();
1444
1445 // Check stall and squash signals, dispatch any instructions.
1446 while (threads != end) {
1447 unsigned tid = *threads++;
1448
1449 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1450
1451 checkSignalsAndUpdate(tid);
1452 dispatch(tid);
1453 }
1454
1455 if (exeStatus != Squashing) {
1456 executeInsts();
1457
1458 writebackInsts();
1459
1460 // Have the instruction queue try to schedule any ready instructions.
1461 // (In actuality, this scheduling is for instructions that will
1462 // be executed next cycle.)
1463 instQueue.scheduleReadyInsts();
1464
1465 // Also should advance its own time buffers if the stage ran.
1466 // Not the best place for it, but this works (hopefully).
1467 issueToExecQueue.advance();
1468 }
1469
1470 bool broadcast_free_entries = false;
1471
1472 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1473 exeStatus = Idle;
1474 updateLSQNextCycle = false;
1475
1476 broadcast_free_entries = true;
1477 }
1478
1479 // Writeback any stores using any leftover bandwidth.
1480 ldstQueue.writebackStores();
1481
1482 // Check the committed load/store signals to see if there's a load
1483 // or store to commit. Also check if it's being told to execute a
1484 // nonspeculative instruction.
1485 // This is pretty inefficient...
1486
1487 threads = activeThreads->begin();
1488 while (threads != end) {
1489 unsigned tid = (*threads++);
1490
1491 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1492
1493 // Update structures based on instructions committed.
1494 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1495 !fromCommit->commitInfo[tid].squash &&
1496 !fromCommit->commitInfo[tid].robSquashing) {
1497
1498 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1499
1500 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1501
1502 updateLSQNextCycle = true;
1503 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504 }
1505
1506 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1507
1508 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1509 if (fromCommit->commitInfo[tid].uncached) {
1510 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1511 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1512 } else {
1513 instQueue.scheduleNonSpec(
1514 fromCommit->commitInfo[tid].nonSpecSeqNum);
1515 }
1516 }
1517
1518 if (broadcast_free_entries) {
1519 toFetch->iewInfo[tid].iqCount =
1520 instQueue.getCount(tid);
1521 toFetch->iewInfo[tid].ldstqCount =
1522 ldstQueue.getCount(tid);
1523
1524 toRename->iewInfo[tid].usedIQ = true;
1525 toRename->iewInfo[tid].freeIQEntries =
1526 instQueue.numFreeEntries();
1527 toRename->iewInfo[tid].usedLSQ = true;
1528 toRename->iewInfo[tid].freeLSQEntries =
1529 ldstQueue.numFreeEntries(tid);
1530
1531 wroteToTimeBuffer = true;
1532 }
1533
1534 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1535 tid, toRename->iewInfo[tid].dispatched);
1536 }
1537
1538 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1539 "LSQ has %i free entries.\n",
1540 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1541 ldstQueue.numFreeEntries());
1542
1543 updateStatus();
1544
1545 if (wroteToTimeBuffer) {
1546 DPRINTF(Activity, "Activity this cycle.\n");
1547 cpu->activityThisCycle();
1548 }
1549}
1550
1551template <class Impl>
1552void
1553DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1554{
1555 int thread_number = inst->threadNumber;
1556
1557 //
1558 // Pick off the software prefetches
1559 //
1560#ifdef TARGET_ALPHA
1561 if (inst->isDataPrefetch())
1562 iewExecutedSwp[thread_number]++;
1563 else
1564 iewIewExecutedcutedInsts++;
1565#else
1566 iewExecutedInsts++;
1567#endif
1568
1569 //
1570 // Control operations
1571 //
1572 if (inst->isControl())
1573 iewExecutedBranches[thread_number]++;
1574
1575 //
1576 // Memory operations
1577 //
1578 if (inst->isMemRef()) {
1579 iewExecutedRefs[thread_number]++;
1580
1581 if (inst->isLoad()) {
1582 iewExecLoadInsts[thread_number]++;
1583 }
1584 }
1585}
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