1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43 : issueToExecQueue(params->backComSize, params->forwardComSize),
44 instQueue(params),
45 ldstQueue(params),
46 fuPool(params->fuPool),
47 commitToIEWDelay(params->commitToIEWDelay),
48 renameToIEWDelay(params->renameToIEWDelay),
49 issueToExecuteDelay(params->issueToExecuteDelay),
50 dispatchWidth(params->dispatchWidth),
51 issueWidth(params->issueWidth),
52 wbOutstanding(0),
53 wbWidth(params->wbWidth),
54 numThreads(params->numberOfThreads),
55 switchedOut(false)
56{
57 _status = Active;
58 exeStatus = Running;
59 wbStatus = Idle;
60
61 // Setup wire to read instructions coming from issue.
62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64 // Instruction queue needs the queue between issue and execute.
65 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67 instQueue.setIEW(this);
68 ldstQueue.setIEW(this);
69
70 for (int i=0; i < numThreads; i++) {
71 dispatchStatus[i] = Running;
72 stalls[i].commit = false;
73 fetchRedirect[i] = false;
74 bdelayDoneSeqNum[i] = 0;
75 }
76
77 wbMax = wbWidth * params->wbDepth;
78
79 updateLSQNextCycle = false;
80
81 ableToIssue = true;
82
83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90 return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97 using namespace Stats;
98
99 instQueue.regStats();
100 ldstQueue.regStats();
101
102 iewIdleCycles
103 .name(name() + ".iewIdleCycles")
104 .desc("Number of cycles IEW is idle");
105
106 iewSquashCycles
107 .name(name() + ".iewSquashCycles")
108 .desc("Number of cycles IEW is squashing");
109
110 iewBlockCycles
111 .name(name() + ".iewBlockCycles")
112 .desc("Number of cycles IEW is blocking");
113
114 iewUnblockCycles
115 .name(name() + ".iewUnblockCycles")
116 .desc("Number of cycles IEW is unblocking");
117
118 iewDispatchedInsts
119 .name(name() + ".iewDispatchedInsts")
120 .desc("Number of instructions dispatched to IQ");
121
122 iewDispSquashedInsts
123 .name(name() + ".iewDispSquashedInsts")
124 .desc("Number of squashed instructions skipped by dispatch");
125
126 iewDispLoadInsts
127 .name(name() + ".iewDispLoadInsts")
128 .desc("Number of dispatched load instructions");
129
130 iewDispStoreInsts
131 .name(name() + ".iewDispStoreInsts")
132 .desc("Number of dispatched store instructions");
133
134 iewDispNonSpecInsts
135 .name(name() + ".iewDispNonSpecInsts")
136 .desc("Number of dispatched non-speculative instructions");
137
138 iewIQFullEvents
139 .name(name() + ".iewIQFullEvents")
140 .desc("Number of times the IQ has become full, causing a stall");
141
142 iewLSQFullEvents
143 .name(name() + ".iewLSQFullEvents")
144 .desc("Number of times the LSQ has become full, causing a stall");
145
146 memOrderViolationEvents
147 .name(name() + ".memOrderViolationEvents")
148 .desc("Number of memory order violations");
149
150 predictedTakenIncorrect
151 .name(name() + ".predictedTakenIncorrect")
152 .desc("Number of branches that were predicted taken incorrectly");
153
154 predictedNotTakenIncorrect
155 .name(name() + ".predictedNotTakenIncorrect")
156 .desc("Number of branches that were predicted not taken incorrectly");
157
158 branchMispredicts
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
161
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164 iewExecutedInsts
165 .name(name() + ".iewExecutedInsts")
166 .desc("Number of executed instructions");
167
168 iewExecLoadInsts
169 .init(cpu->number_of_threads)
170 .name(name() + ".iewExecLoadInsts")
171 .desc("Number of load instructions executed")
172 .flags(total);
173
174 iewExecSquashedInsts
175 .name(name() + ".iewExecSquashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
177
178 iewExecutedSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
182 .flags(total);
183
184 iewExecutedNop
185 .init(cpu->number_of_threads)
186 .name(name() + ".EXEC:nop")
187 .desc("number of nop insts executed")
188 .flags(total);
189
190 iewExecutedRefs
191 .init(cpu->number_of_threads)
192 .name(name() + ".EXEC:refs")
193 .desc("number of memory reference insts executed")
194 .flags(total);
195
196 iewExecutedBranches
197 .init(cpu->number_of_threads)
198 .name(name() + ".EXEC:branches")
199 .desc("Number of branches executed")
200 .flags(total);
201
202 iewExecStoreInsts
203 .name(name() + ".EXEC:stores")
204 .desc("Number of stores executed")
205 .flags(total);
206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208 iewExecRate
209 .name(name() + ".EXEC:rate")
210 .desc("Inst execution rate")
211 .flags(total);
212
213 iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215 iewInstsToCommit
216 .init(cpu->number_of_threads)
217 .name(name() + ".WB:sent")
218 .desc("cumulative count of insts sent to commit")
219 .flags(total);
220
221 writebackCount
222 .init(cpu->number_of_threads)
223 .name(name() + ".WB:count")
224 .desc("cumulative count of insts written-back")
225 .flags(total);
226
227 producerInst
228 .init(cpu->number_of_threads)
229 .name(name() + ".WB:producers")
230 .desc("num instructions producing a value")
231 .flags(total);
232
233 consumerInst
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:consumers")
236 .desc("num instructions consuming a value")
237 .flags(total);
238
239 wbPenalized
240 .init(cpu->number_of_threads)
241 .name(name() + ".WB:penalized")
242 .desc("number of instrctions required to write to 'other' IQ")
243 .flags(total);
244
245 wbPenalizedRate
246 .name(name() + ".WB:penalized_rate")
247 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248 .flags(total);
249
250 wbPenalizedRate = wbPenalized / writebackCount;
251
252 wbFanout
253 .name(name() + ".WB:fanout")
254 .desc("average fanout of values written-back")
255 .flags(total);
256
257 wbFanout = producerInst / consumerInst;
258
259 wbRate
260 .name(name() + ".WB:rate")
261 .desc("insts written-back per cycle")
262 .flags(total);
263 wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270 for (int tid=0; tid < numThreads; tid++) {
271 toRename->iewInfo[tid].usedIQ = true;
272 toRename->iewInfo[tid].freeIQEntries =
273 instQueue.numFreeEntries(tid);
274
275 toRename->iewInfo[tid].usedLSQ = true;
276 toRename->iewInfo[tid].freeLSQEntries =
277 ldstQueue.numFreeEntries(tid);
278 }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285 DPRINTF(IEW, "Setting CPU pointer.\n");
286 cpu = cpu_ptr;
287
288 instQueue.setCPU(cpu_ptr);
289 ldstQueue.setCPU(cpu_ptr);
290
291 cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298 DPRINTF(IEW, "Setting time buffer pointer.\n");
299 timeBuffer = tb_ptr;
300
301 // Setup wire to read information from time buffer, from commit.
302 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304 // Setup wire to write information back to previous stages.
305 toRename = timeBuffer->getWire(0);
306
307 toFetch = timeBuffer->getWire(0);
308
309 // Instruction queue also needs main time buffer.
310 instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317 DPRINTF(IEW, "Setting rename queue pointer.\n");
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 DPRINTF(IEW, "Setting IEW queue pointer.\n");
329 iewQueue = iq_ptr;
330
331 // Setup wire to write instructions to commit.
332 toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339 DPRINTF(IEW, "Setting active threads list pointer.\n");
340 activeThreads = at_ptr;
341
342 ldstQueue.setActiveThreads(at_ptr);
343 instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350 DPRINTF(IEW, "Setting scoreboard pointer.\n");
351 scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358 // IEW is ready to drain at any time.
359 cpu->signalDrained();
360 return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373 // Clear any state.
374 switchedOut = true;
375 assert(insts[0].empty());
376 assert(skidBuffer[0].empty());
377
378 instQueue.switchOut();
379 ldstQueue.switchOut();
380 fuPool->switchOut();
381
382 for (int i = 0; i < numThreads; i++) {
383 while (!insts[i].empty())
384 insts[i].pop();
385 while (!skidBuffer[i].empty())
386 skidBuffer[i].pop();
387 }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394 // Reset all state.
395 _status = Active;
396 exeStatus = Running;
397 wbStatus = Idle;
398 switchedOut = false;
399
400 instQueue.takeOverFrom();
401 ldstQueue.takeOverFrom();
402 fuPool->takeOverFrom();
403
404 initStage();
405 cpu->activityThisCycle();
406
407 for (int i=0; i < numThreads; i++) {
408 dispatchStatus[i] = Running;
409 stalls[i].commit = false;
410 fetchRedirect[i] = false;
411 }
412
413 updateLSQNextCycle = false;
414
415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416 issueToExecQueue.advance();
417 }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436 updatedQueues = true;
437
438 // Clear the skid buffer in case it has any data in it.
439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442 while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444 if (skidBuffer[tid].front()->seqNum <=
445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447 "that occur before delay slot [sn:%i].\n",
448 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449 tid);
450 break;
451 } else {
452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454 }
455#endif
456 if (skidBuffer[tid].front()->isLoad() ||
457 skidBuffer[tid].front()->isStore() ) {
458 toRename->iewInfo[tid].dispatchedToLSQ++;
459 }
460
461 toRename->iewInfo[tid].dispatched++;
462
463 skidBuffer[tid].pop();
464 }
465
466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468 emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43 : issueToExecQueue(params->backComSize, params->forwardComSize),
44 instQueue(params),
45 ldstQueue(params),
46 fuPool(params->fuPool),
47 commitToIEWDelay(params->commitToIEWDelay),
48 renameToIEWDelay(params->renameToIEWDelay),
49 issueToExecuteDelay(params->issueToExecuteDelay),
50 dispatchWidth(params->dispatchWidth),
51 issueWidth(params->issueWidth),
52 wbOutstanding(0),
53 wbWidth(params->wbWidth),
54 numThreads(params->numberOfThreads),
55 switchedOut(false)
56{
57 _status = Active;
58 exeStatus = Running;
59 wbStatus = Idle;
60
61 // Setup wire to read instructions coming from issue.
62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64 // Instruction queue needs the queue between issue and execute.
65 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67 instQueue.setIEW(this);
68 ldstQueue.setIEW(this);
69
70 for (int i=0; i < numThreads; i++) {
71 dispatchStatus[i] = Running;
72 stalls[i].commit = false;
73 fetchRedirect[i] = false;
74 bdelayDoneSeqNum[i] = 0;
75 }
76
77 wbMax = wbWidth * params->wbDepth;
78
79 updateLSQNextCycle = false;
80
81 ableToIssue = true;
82
83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90 return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97 using namespace Stats;
98
99 instQueue.regStats();
100 ldstQueue.regStats();
101
102 iewIdleCycles
103 .name(name() + ".iewIdleCycles")
104 .desc("Number of cycles IEW is idle");
105
106 iewSquashCycles
107 .name(name() + ".iewSquashCycles")
108 .desc("Number of cycles IEW is squashing");
109
110 iewBlockCycles
111 .name(name() + ".iewBlockCycles")
112 .desc("Number of cycles IEW is blocking");
113
114 iewUnblockCycles
115 .name(name() + ".iewUnblockCycles")
116 .desc("Number of cycles IEW is unblocking");
117
118 iewDispatchedInsts
119 .name(name() + ".iewDispatchedInsts")
120 .desc("Number of instructions dispatched to IQ");
121
122 iewDispSquashedInsts
123 .name(name() + ".iewDispSquashedInsts")
124 .desc("Number of squashed instructions skipped by dispatch");
125
126 iewDispLoadInsts
127 .name(name() + ".iewDispLoadInsts")
128 .desc("Number of dispatched load instructions");
129
130 iewDispStoreInsts
131 .name(name() + ".iewDispStoreInsts")
132 .desc("Number of dispatched store instructions");
133
134 iewDispNonSpecInsts
135 .name(name() + ".iewDispNonSpecInsts")
136 .desc("Number of dispatched non-speculative instructions");
137
138 iewIQFullEvents
139 .name(name() + ".iewIQFullEvents")
140 .desc("Number of times the IQ has become full, causing a stall");
141
142 iewLSQFullEvents
143 .name(name() + ".iewLSQFullEvents")
144 .desc("Number of times the LSQ has become full, causing a stall");
145
146 memOrderViolationEvents
147 .name(name() + ".memOrderViolationEvents")
148 .desc("Number of memory order violations");
149
150 predictedTakenIncorrect
151 .name(name() + ".predictedTakenIncorrect")
152 .desc("Number of branches that were predicted taken incorrectly");
153
154 predictedNotTakenIncorrect
155 .name(name() + ".predictedNotTakenIncorrect")
156 .desc("Number of branches that were predicted not taken incorrectly");
157
158 branchMispredicts
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
161
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164 iewExecutedInsts
165 .name(name() + ".iewExecutedInsts")
166 .desc("Number of executed instructions");
167
168 iewExecLoadInsts
169 .init(cpu->number_of_threads)
170 .name(name() + ".iewExecLoadInsts")
171 .desc("Number of load instructions executed")
172 .flags(total);
173
174 iewExecSquashedInsts
175 .name(name() + ".iewExecSquashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
177
178 iewExecutedSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
182 .flags(total);
183
184 iewExecutedNop
185 .init(cpu->number_of_threads)
186 .name(name() + ".EXEC:nop")
187 .desc("number of nop insts executed")
188 .flags(total);
189
190 iewExecutedRefs
191 .init(cpu->number_of_threads)
192 .name(name() + ".EXEC:refs")
193 .desc("number of memory reference insts executed")
194 .flags(total);
195
196 iewExecutedBranches
197 .init(cpu->number_of_threads)
198 .name(name() + ".EXEC:branches")
199 .desc("Number of branches executed")
200 .flags(total);
201
202 iewExecStoreInsts
203 .name(name() + ".EXEC:stores")
204 .desc("Number of stores executed")
205 .flags(total);
206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208 iewExecRate
209 .name(name() + ".EXEC:rate")
210 .desc("Inst execution rate")
211 .flags(total);
212
213 iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215 iewInstsToCommit
216 .init(cpu->number_of_threads)
217 .name(name() + ".WB:sent")
218 .desc("cumulative count of insts sent to commit")
219 .flags(total);
220
221 writebackCount
222 .init(cpu->number_of_threads)
223 .name(name() + ".WB:count")
224 .desc("cumulative count of insts written-back")
225 .flags(total);
226
227 producerInst
228 .init(cpu->number_of_threads)
229 .name(name() + ".WB:producers")
230 .desc("num instructions producing a value")
231 .flags(total);
232
233 consumerInst
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:consumers")
236 .desc("num instructions consuming a value")
237 .flags(total);
238
239 wbPenalized
240 .init(cpu->number_of_threads)
241 .name(name() + ".WB:penalized")
242 .desc("number of instrctions required to write to 'other' IQ")
243 .flags(total);
244
245 wbPenalizedRate
246 .name(name() + ".WB:penalized_rate")
247 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248 .flags(total);
249
250 wbPenalizedRate = wbPenalized / writebackCount;
251
252 wbFanout
253 .name(name() + ".WB:fanout")
254 .desc("average fanout of values written-back")
255 .flags(total);
256
257 wbFanout = producerInst / consumerInst;
258
259 wbRate
260 .name(name() + ".WB:rate")
261 .desc("insts written-back per cycle")
262 .flags(total);
263 wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270 for (int tid=0; tid < numThreads; tid++) {
271 toRename->iewInfo[tid].usedIQ = true;
272 toRename->iewInfo[tid].freeIQEntries =
273 instQueue.numFreeEntries(tid);
274
275 toRename->iewInfo[tid].usedLSQ = true;
276 toRename->iewInfo[tid].freeLSQEntries =
277 ldstQueue.numFreeEntries(tid);
278 }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285 DPRINTF(IEW, "Setting CPU pointer.\n");
286 cpu = cpu_ptr;
287
288 instQueue.setCPU(cpu_ptr);
289 ldstQueue.setCPU(cpu_ptr);
290
291 cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298 DPRINTF(IEW, "Setting time buffer pointer.\n");
299 timeBuffer = tb_ptr;
300
301 // Setup wire to read information from time buffer, from commit.
302 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304 // Setup wire to write information back to previous stages.
305 toRename = timeBuffer->getWire(0);
306
307 toFetch = timeBuffer->getWire(0);
308
309 // Instruction queue also needs main time buffer.
310 instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317 DPRINTF(IEW, "Setting rename queue pointer.\n");
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 DPRINTF(IEW, "Setting IEW queue pointer.\n");
329 iewQueue = iq_ptr;
330
331 // Setup wire to write instructions to commit.
332 toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339 DPRINTF(IEW, "Setting active threads list pointer.\n");
340 activeThreads = at_ptr;
341
342 ldstQueue.setActiveThreads(at_ptr);
343 instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350 DPRINTF(IEW, "Setting scoreboard pointer.\n");
351 scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358 // IEW is ready to drain at any time.
359 cpu->signalDrained();
360 return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373 // Clear any state.
374 switchedOut = true;
375 assert(insts[0].empty());
376 assert(skidBuffer[0].empty());
377
378 instQueue.switchOut();
379 ldstQueue.switchOut();
380 fuPool->switchOut();
381
382 for (int i = 0; i < numThreads; i++) {
383 while (!insts[i].empty())
384 insts[i].pop();
385 while (!skidBuffer[i].empty())
386 skidBuffer[i].pop();
387 }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394 // Reset all state.
395 _status = Active;
396 exeStatus = Running;
397 wbStatus = Idle;
398 switchedOut = false;
399
400 instQueue.takeOverFrom();
401 ldstQueue.takeOverFrom();
402 fuPool->takeOverFrom();
403
404 initStage();
405 cpu->activityThisCycle();
406
407 for (int i=0; i < numThreads; i++) {
408 dispatchStatus[i] = Running;
409 stalls[i].commit = false;
410 fetchRedirect[i] = false;
411 }
412
413 updateLSQNextCycle = false;
414
415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416 issueToExecQueue.advance();
417 }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436 updatedQueues = true;
437
438 // Clear the skid buffer in case it has any data in it.
439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442 while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444 if (skidBuffer[tid].front()->seqNum <=
445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447 "that occur before delay slot [sn:%i].\n",
448 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449 tid);
450 break;
451 } else {
452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454 }
455#endif
456 if (skidBuffer[tid].front()->isLoad() ||
457 skidBuffer[tid].front()->isStore() ) {
458 toRename->iewInfo[tid].dispatchedToLSQ++;
459 }
460
461 toRename->iewInfo[tid].dispatched++;
462
463 skidBuffer[tid].pop();
464 }
465
466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468 emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
|
484 bool branch_taken = inst->readNextNPC() !=
485 (inst->readNextPC() + sizeof(TheISA::MachInst));
| 484 int instSize = sizeof(TheISA::MachInst);
485 bool branch_taken =
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
|
486
487 toCommit->branchTaken[tid] = branch_taken;
488
| 491
492 toCommit->branchTaken[tid] = branch_taken;
493
|
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491 if (inst->isCondDelaySlot() && branch_taken) {
| 494 bool squashDelaySlot = true;
495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
501 //NextNPC.
502 if (squashDelaySlot) {
|
492 toCommit->nextPC[tid] = inst->readNextPC();
| 503 toCommit->nextPC[tid] = inst->readNextPC();
|
493 } else {
| 504 toCommit->nextNPC[tid] = inst->readNextNPC();
505 } else
|
494 toCommit->nextPC[tid] = inst->readNextNPC();
| 506 toCommit->nextPC[tid] = inst->readNextNPC();
|
495 }
| |
496#else
497 toCommit->branchTaken[tid] = inst->readNextPC() !=
498 (inst->readPC() + sizeof(TheISA::MachInst));
499 toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502 toCommit->includeSquashInst[tid] = false;
503
504 wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
| 507#else
508 toCommit->branchTaken[tid] = inst->readNextPC() !=
509 (inst->readPC() + sizeof(TheISA::MachInst));
510 toCommit->nextPC[tid] = inst->readNextPC();
511#endif
512
513 toCommit->includeSquashInst[tid] = false;
514
515 wroteToTimeBuffer = true;
516}
517
518template<class Impl>
519void
520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
521{
522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
524
525 toCommit->squash[tid] = true;
526 toCommit->squashedSeqNum[tid] = inst->seqNum;
527 toCommit->nextPC[tid] = inst->readNextPC();
|
| 528#if ISA_HAS_DELAY_SLOT
529 toCommit->nextNPC[tid] = inst->readNextNPC();
530#endif
|
517 toCommit->branchMispredict[tid] = false;
518
519 toCommit->includeSquashInst[tid] = false;
520
521 wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531 toCommit->squash[tid] = true;
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->nextPC[tid] = inst->readPC();
| 531 toCommit->branchMispredict[tid] = false;
532
533 toCommit->includeSquashInst[tid] = false;
534
535 wroteToTimeBuffer = true;
536}
537
538template<class Impl>
539void
540DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
541{
542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
543 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
544
545 toCommit->squash[tid] = true;
546 toCommit->squashedSeqNum[tid] = inst->seqNum;
547 toCommit->nextPC[tid] = inst->readPC();
|
| 548#if ISA_HAS_DELAY_SLOT
549 toCommit->nextNPC[tid] = inst->readNextNPC();
550#endif
|
534 toCommit->branchMispredict[tid] = false;
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;
542}
543
544template<class Impl>
545void
546DefaultIEW<Impl>::block(unsigned tid)
547{
548 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
549
550 if (dispatchStatus[tid] != Blocked &&
551 dispatchStatus[tid] != Unblocking) {
552 toRename->iewBlock[tid] = true;
553 wroteToTimeBuffer = true;
554 }
555
556 // Add the current inputs to the skid buffer so they can be
557 // reprocessed when this stage unblocks.
558 skidInsert(tid);
559
560 dispatchStatus[tid] = Blocked;
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::unblock(unsigned tid)
566{
567 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
568 "buffer %u.\n",tid, tid);
569
570 // If the skid bufffer is empty, signal back to previous stages to unblock.
571 // Also switch status to running.
572 if (skidBuffer[tid].empty()) {
573 toRename->iewUnblock[tid] = true;
574 wroteToTimeBuffer = true;
575 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
576 dispatchStatus[tid] = Running;
577 }
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
583{
584 instQueue.wakeDependents(inst);
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
590{
591 instQueue.rescheduleMemInst(inst);
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
597{
598 instQueue.replayMemInst(inst);
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604{
605 // This function should not be called after writebackInsts in a
606 // single cycle. That will cause problems with an instruction
607 // being added to the queue to commit without being processed by
608 // writebackInsts prior to being sent to commit.
609
610 // First check the time slot that this instruction will write
611 // to. If there are free write ports at the time, then go ahead
612 // and write the instruction to that time. If there are not,
613 // keep looking back to see where's the first time there's a
614 // free slot.
615 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
616 ++wbNumInst;
617 if (wbNumInst == wbWidth) {
618 ++wbCycle;
619 wbNumInst = 0;
620 }
621
622 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
623 }
624
625 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
626 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
627 // Add finished instruction to queue to commit.
628 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
629 (*iewQueue)[wbCycle].size++;
630}
631
632template <class Impl>
633unsigned
634DefaultIEW<Impl>::validInstsFromRename()
635{
636 unsigned inst_count = 0;
637
638 for (int i=0; i<fromRename->size; i++) {
639 if (!fromRename->insts[i]->isSquashed())
640 inst_count++;
641 }
642
643 return inst_count;
644}
645
646template<class Impl>
647void
648DefaultIEW<Impl>::skidInsert(unsigned tid)
649{
650 DynInstPtr inst = NULL;
651
652 while (!insts[tid].empty()) {
653 inst = insts[tid].front();
654
655 insts[tid].pop();
656
657 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
658 "dispatch skidBuffer %i\n",tid, inst->seqNum,
659 inst->readPC(),tid);
660
661 skidBuffer[tid].push(inst);
662 }
663
664 assert(skidBuffer[tid].size() <= skidBufferMax &&
665 "Skidbuffer Exceeded Max Size");
666}
667
668template<class Impl>
669int
670DefaultIEW<Impl>::skidCount()
671{
672 int max=0;
673
| 551 toCommit->branchMispredict[tid] = false;
552
553 // Must include the broadcasted SN in the squash.
554 toCommit->includeSquashInst[tid] = true;
555
556 ldstQueue.setLoadBlockedHandled(tid);
557
558 wroteToTimeBuffer = true;
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::block(unsigned tid)
564{
565 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
566
567 if (dispatchStatus[tid] != Blocked &&
568 dispatchStatus[tid] != Unblocking) {
569 toRename->iewBlock[tid] = true;
570 wroteToTimeBuffer = true;
571 }
572
573 // Add the current inputs to the skid buffer so they can be
574 // reprocessed when this stage unblocks.
575 skidInsert(tid);
576
577 dispatchStatus[tid] = Blocked;
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::unblock(unsigned tid)
583{
584 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
585 "buffer %u.\n",tid, tid);
586
587 // If the skid bufffer is empty, signal back to previous stages to unblock.
588 // Also switch status to running.
589 if (skidBuffer[tid].empty()) {
590 toRename->iewUnblock[tid] = true;
591 wroteToTimeBuffer = true;
592 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
593 dispatchStatus[tid] = Running;
594 }
595}
596
597template<class Impl>
598void
599DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
600{
601 instQueue.wakeDependents(inst);
602}
603
604template<class Impl>
605void
606DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
607{
608 instQueue.rescheduleMemInst(inst);
609}
610
611template<class Impl>
612void
613DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
614{
615 instQueue.replayMemInst(inst);
616}
617
618template<class Impl>
619void
620DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
621{
622 // This function should not be called after writebackInsts in a
623 // single cycle. That will cause problems with an instruction
624 // being added to the queue to commit without being processed by
625 // writebackInsts prior to being sent to commit.
626
627 // First check the time slot that this instruction will write
628 // to. If there are free write ports at the time, then go ahead
629 // and write the instruction to that time. If there are not,
630 // keep looking back to see where's the first time there's a
631 // free slot.
632 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
633 ++wbNumInst;
634 if (wbNumInst == wbWidth) {
635 ++wbCycle;
636 wbNumInst = 0;
637 }
638
639 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
640 }
641
642 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
643 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
644 // Add finished instruction to queue to commit.
645 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
646 (*iewQueue)[wbCycle].size++;
647}
648
649template <class Impl>
650unsigned
651DefaultIEW<Impl>::validInstsFromRename()
652{
653 unsigned inst_count = 0;
654
655 for (int i=0; i<fromRename->size; i++) {
656 if (!fromRename->insts[i]->isSquashed())
657 inst_count++;
658 }
659
660 return inst_count;
661}
662
663template<class Impl>
664void
665DefaultIEW<Impl>::skidInsert(unsigned tid)
666{
667 DynInstPtr inst = NULL;
668
669 while (!insts[tid].empty()) {
670 inst = insts[tid].front();
671
672 insts[tid].pop();
673
674 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
675 "dispatch skidBuffer %i\n",tid, inst->seqNum,
676 inst->readPC(),tid);
677
678 skidBuffer[tid].push(inst);
679 }
680
681 assert(skidBuffer[tid].size() <= skidBufferMax &&
682 "Skidbuffer Exceeded Max Size");
683}
684
685template<class Impl>
686int
687DefaultIEW<Impl>::skidCount()
688{
689 int max=0;
690
|
674 std::list<unsigned>::iterator threads = activeThreads->begin();
675 std::list<unsigned>::iterator end = activeThreads->end();
| 691 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
676
| 692
|
677 while (threads != end) {
678 unsigned tid = *threads++;
679 unsigned thread_count = skidBuffer[tid].size();
| 693 while (threads != (*activeThreads).end()) {
694 unsigned thread_count = skidBuffer[*threads++].size();
|
680 if (max < thread_count)
681 max = thread_count;
682 }
683
684 return max;
685}
686
687template<class Impl>
688bool
689DefaultIEW<Impl>::skidsEmpty()
690{
| 695 if (max < thread_count)
696 max = thread_count;
697 }
698
699 return max;
700}
701
702template<class Impl>
703bool
704DefaultIEW<Impl>::skidsEmpty()
705{
|
691 std::list<unsigned>::iterator threads = activeThreads->begin();
692 std::list<unsigned>::iterator end = activeThreads->end();
| 706 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
693
| 707
|
694 while (threads != end) {
695 unsigned tid = *threads++;
696
697 if (!skidBuffer[tid].empty())
| 708 while (threads != (*activeThreads).end()) {
709 if (!skidBuffer[*threads++].empty())
|
698 return false;
699 }
700
701 return true;
702}
703
704template <class Impl>
705void
706DefaultIEW<Impl>::updateStatus()
707{
708 bool any_unblocking = false;
709
| 710 return false;
711 }
712
713 return true;
714}
715
716template <class Impl>
717void
718DefaultIEW<Impl>::updateStatus()
719{
720 bool any_unblocking = false;
721
|
710 std::list<unsigned>::iterator threads = activeThreads->begin();
711 std::list<unsigned>::iterator end = activeThreads->end();
| 722 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
712
| 723
|
713 while (threads != end) {
| 724 threads = (*activeThreads).begin();
725
726 while (threads != (*activeThreads).end()) {
|
714 unsigned tid = *threads++;
715
716 if (dispatchStatus[tid] == Unblocking) {
717 any_unblocking = true;
718 break;
719 }
720 }
721
722 // If there are no ready instructions waiting to be scheduled by the IQ,
723 // and there's no stores waiting to write back, and dispatch is not
724 // unblocking, then there is no internal activity for the IEW stage.
725 if (_status == Active && !instQueue.hasReadyInsts() &&
726 !ldstQueue.willWB() && !any_unblocking) {
727 DPRINTF(IEW, "IEW switching to idle\n");
728
729 deactivateStage();
730
731 _status = Inactive;
732 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
733 ldstQueue.willWB() ||
734 any_unblocking)) {
735 // Otherwise there is internal activity. Set to active.
736 DPRINTF(IEW, "IEW switching to active\n");
737
738 activateStage();
739
740 _status = Active;
741 }
742}
743
744template <class Impl>
745void
746DefaultIEW<Impl>::resetEntries()
747{
748 instQueue.resetEntries();
749 ldstQueue.resetEntries();
750}
751
752template <class Impl>
753void
754DefaultIEW<Impl>::readStallSignals(unsigned tid)
755{
756 if (fromCommit->commitBlock[tid]) {
757 stalls[tid].commit = true;
758 }
759
760 if (fromCommit->commitUnblock[tid]) {
761 assert(stalls[tid].commit);
762 stalls[tid].commit = false;
763 }
764}
765
766template <class Impl>
767bool
768DefaultIEW<Impl>::checkStall(unsigned tid)
769{
770 bool ret_val(false);
771
772 if (stalls[tid].commit) {
773 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
774 ret_val = true;
775 } else if (instQueue.isFull(tid)) {
776 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
777 ret_val = true;
778 } else if (ldstQueue.isFull(tid)) {
779 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
780
781 if (ldstQueue.numLoads(tid) > 0 ) {
782
783 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
784 tid,ldstQueue.getLoadHeadSeqNum(tid));
785 }
786
787 if (ldstQueue.numStores(tid) > 0) {
788
789 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
790 tid,ldstQueue.getStoreHeadSeqNum(tid));
791 }
792
793 ret_val = true;
794 } else if (ldstQueue.isStalled(tid)) {
795 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
796 ret_val = true;
797 }
798
799 return ret_val;
800}
801
802template <class Impl>
803void
804DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
805{
806 // Check if there's a squash signal, squash if there is
807 // Check stall signals, block if there is.
808 // If status was Blocked
809 // if so then go to unblocking
810 // If status was Squashing
811 // check if squashing is not high. Switch to running this cycle.
812
813 readStallSignals(tid);
814
815 if (fromCommit->commitInfo[tid].squash) {
816 squash(tid);
817
818 if (dispatchStatus[tid] == Blocked ||
819 dispatchStatus[tid] == Unblocking) {
820 toRename->iewUnblock[tid] = true;
821 wroteToTimeBuffer = true;
822 }
823
824 dispatchStatus[tid] = Squashing;
825
826 fetchRedirect[tid] = false;
827 return;
828 }
829
830 if (fromCommit->commitInfo[tid].robSquashing) {
831 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
832
833 dispatchStatus[tid] = Squashing;
834
835 emptyRenameInsts(tid);
836 wroteToTimeBuffer = true;
837 return;
838 }
839
840 if (checkStall(tid)) {
841 block(tid);
842 dispatchStatus[tid] = Blocked;
843 return;
844 }
845
846 if (dispatchStatus[tid] == Blocked) {
847 // Status from previous cycle was blocked, but there are no more stall
848 // conditions. Switch over to unblocking.
849 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
850 tid);
851
852 dispatchStatus[tid] = Unblocking;
853
854 unblock(tid);
855
856 return;
857 }
858
859 if (dispatchStatus[tid] == Squashing) {
860 // Switch status to running if rename isn't being told to block or
861 // squash this cycle.
862 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
863 tid);
864
865 dispatchStatus[tid] = Running;
866
867 return;
868 }
869}
870
871template <class Impl>
872void
873DefaultIEW<Impl>::sortInsts()
874{
875 int insts_from_rename = fromRename->size;
876#ifdef DEBUG
877#if !ISA_HAS_DELAY_SLOT
878 for (int i = 0; i < numThreads; i++)
879 assert(insts[i].empty());
880#endif
881#endif
882 for (int i = 0; i < insts_from_rename; ++i) {
883 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
884 }
885}
886
887template <class Impl>
888void
889DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
890{
891 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
892 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
893
894 while (!insts[tid].empty()) {
895#if ISA_HAS_DELAY_SLOT
896 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
897 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
898 " that occurs at or before delay slot [sn:%i].\n",
899 tid, bdelayDoneSeqNum[tid]);
900 break;
901 } else {
902 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
903 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
904 }
905#endif
906
907 if (insts[tid].front()->isLoad() ||
908 insts[tid].front()->isStore() ) {
909 toRename->iewInfo[tid].dispatchedToLSQ++;
910 }
911
912 toRename->iewInfo[tid].dispatched++;
913
914 insts[tid].pop();
915 }
916}
917
918template <class Impl>
919void
920DefaultIEW<Impl>::wakeCPU()
921{
922 cpu->wakeCPU();
923}
924
925template <class Impl>
926void
927DefaultIEW<Impl>::activityThisCycle()
928{
929 DPRINTF(Activity, "Activity this cycle.\n");
930 cpu->activityThisCycle();
931}
932
933template <class Impl>
934inline void
935DefaultIEW<Impl>::activateStage()
936{
937 DPRINTF(Activity, "Activating stage.\n");
938 cpu->activateStage(O3CPU::IEWIdx);
939}
940
941template <class Impl>
942inline void
943DefaultIEW<Impl>::deactivateStage()
944{
945 DPRINTF(Activity, "Deactivating stage.\n");
946 cpu->deactivateStage(O3CPU::IEWIdx);
947}
948
949template<class Impl>
950void
951DefaultIEW<Impl>::dispatch(unsigned tid)
952{
953 // If status is Running or idle,
954 // call dispatchInsts()
955 // If status is Unblocking,
956 // buffer any instructions coming from rename
957 // continue trying to empty skid buffer
958 // check if stall conditions have passed
959
960 if (dispatchStatus[tid] == Blocked) {
961 ++iewBlockCycles;
962
963 } else if (dispatchStatus[tid] == Squashing) {
964 ++iewSquashCycles;
965 }
966
967 // Dispatch should try to dispatch as many instructions as its bandwidth
968 // will allow, as long as it is not currently blocked.
969 if (dispatchStatus[tid] == Running ||
970 dispatchStatus[tid] == Idle) {
971 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
972 "dispatch.\n", tid);
973
974 dispatchInsts(tid);
975 } else if (dispatchStatus[tid] == Unblocking) {
976 // Make sure that the skid buffer has something in it if the
977 // status is unblocking.
978 assert(!skidsEmpty());
979
980 // If the status was unblocking, then instructions from the skid
981 // buffer were used. Remove those instructions and handle
982 // the rest of unblocking.
983 dispatchInsts(tid);
984
985 ++iewUnblockCycles;
986
987 if (validInstsFromRename() && dispatchedAllInsts) {
988 // Add the current inputs to the skid buffer so they can be
989 // reprocessed when this stage unblocks.
990 skidInsert(tid);
991 }
992
993 unblock(tid);
994 }
995}
996
997template <class Impl>
998void
999DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1000{
1001 dispatchedAllInsts = true;
1002
1003 // Obtain instructions from skid buffer if unblocking, or queue from rename
1004 // otherwise.
1005 std::queue<DynInstPtr> &insts_to_dispatch =
1006 dispatchStatus[tid] == Unblocking ?
1007 skidBuffer[tid] : insts[tid];
1008
1009 int insts_to_add = insts_to_dispatch.size();
1010
1011 DynInstPtr inst;
1012 bool add_to_iq = false;
1013 int dis_num_inst = 0;
1014
1015 // Loop through the instructions, putting them in the instruction
1016 // queue.
1017 for ( ; dis_num_inst < insts_to_add &&
1018 dis_num_inst < dispatchWidth;
1019 ++dis_num_inst)
1020 {
1021 inst = insts_to_dispatch.front();
1022
1023 if (dispatchStatus[tid] == Unblocking) {
1024 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1025 "buffer\n", tid);
1026 }
1027
1028 // Make sure there's a valid instruction there.
1029 assert(inst);
1030
1031 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1032 "IQ.\n",
1033 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1034
1035 // Be sure to mark these instructions as ready so that the
1036 // commit stage can go ahead and execute them, and mark
1037 // them as issued so the IQ doesn't reprocess them.
1038
1039 // Check for squashed instructions.
1040 if (inst->isSquashed()) {
1041 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1042 "not adding to IQ.\n", tid);
1043
1044 ++iewDispSquashedInsts;
1045
1046 insts_to_dispatch.pop();
1047
1048 //Tell Rename That An Instruction has been processed
1049 if (inst->isLoad() || inst->isStore()) {
1050 toRename->iewInfo[tid].dispatchedToLSQ++;
1051 }
1052 toRename->iewInfo[tid].dispatched++;
1053
1054 continue;
1055 }
1056
1057 // Check for full conditions.
1058 if (instQueue.isFull(tid)) {
1059 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1060
1061 // Call function to start blocking.
1062 block(tid);
1063
1064 // Set unblock to false. Special case where we are using
1065 // skidbuffer (unblocking) instructions but then we still
1066 // get full in the IQ.
1067 toRename->iewUnblock[tid] = false;
1068
1069 dispatchedAllInsts = false;
1070
1071 ++iewIQFullEvents;
1072 break;
1073 } else if (ldstQueue.isFull(tid)) {
1074 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1075
1076 // Call function to start blocking.
1077 block(tid);
1078
1079 // Set unblock to false. Special case where we are using
1080 // skidbuffer (unblocking) instructions but then we still
1081 // get full in the IQ.
1082 toRename->iewUnblock[tid] = false;
1083
1084 dispatchedAllInsts = false;
1085
1086 ++iewLSQFullEvents;
1087 break;
1088 }
1089
1090 // Otherwise issue the instruction just fine.
1091 if (inst->isLoad()) {
1092 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1093 "encountered, adding to LSQ.\n", tid);
1094
1095 // Reserve a spot in the load store queue for this
1096 // memory access.
1097 ldstQueue.insertLoad(inst);
1098
1099 ++iewDispLoadInsts;
1100
1101 add_to_iq = true;
1102
1103 toRename->iewInfo[tid].dispatchedToLSQ++;
1104 } else if (inst->isStore()) {
1105 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1106 "encountered, adding to LSQ.\n", tid);
1107
1108 ldstQueue.insertStore(inst);
1109
1110 ++iewDispStoreInsts;
1111
1112 if (inst->isStoreConditional()) {
1113 // Store conditionals need to be set as "canCommit()"
1114 // so that commit can process them when they reach the
1115 // head of commit.
1116 // @todo: This is somewhat specific to Alpha.
1117 inst->setCanCommit();
1118 instQueue.insertNonSpec(inst);
1119 add_to_iq = false;
1120
1121 ++iewDispNonSpecInsts;
1122 } else {
1123 add_to_iq = true;
1124 }
1125
1126 toRename->iewInfo[tid].dispatchedToLSQ++;
| 727 unsigned tid = *threads++;
728
729 if (dispatchStatus[tid] == Unblocking) {
730 any_unblocking = true;
731 break;
732 }
733 }
734
735 // If there are no ready instructions waiting to be scheduled by the IQ,
736 // and there's no stores waiting to write back, and dispatch is not
737 // unblocking, then there is no internal activity for the IEW stage.
738 if (_status == Active && !instQueue.hasReadyInsts() &&
739 !ldstQueue.willWB() && !any_unblocking) {
740 DPRINTF(IEW, "IEW switching to idle\n");
741
742 deactivateStage();
743
744 _status = Inactive;
745 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
746 ldstQueue.willWB() ||
747 any_unblocking)) {
748 // Otherwise there is internal activity. Set to active.
749 DPRINTF(IEW, "IEW switching to active\n");
750
751 activateStage();
752
753 _status = Active;
754 }
755}
756
757template <class Impl>
758void
759DefaultIEW<Impl>::resetEntries()
760{
761 instQueue.resetEntries();
762 ldstQueue.resetEntries();
763}
764
765template <class Impl>
766void
767DefaultIEW<Impl>::readStallSignals(unsigned tid)
768{
769 if (fromCommit->commitBlock[tid]) {
770 stalls[tid].commit = true;
771 }
772
773 if (fromCommit->commitUnblock[tid]) {
774 assert(stalls[tid].commit);
775 stalls[tid].commit = false;
776 }
777}
778
779template <class Impl>
780bool
781DefaultIEW<Impl>::checkStall(unsigned tid)
782{
783 bool ret_val(false);
784
785 if (stalls[tid].commit) {
786 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
787 ret_val = true;
788 } else if (instQueue.isFull(tid)) {
789 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
790 ret_val = true;
791 } else if (ldstQueue.isFull(tid)) {
792 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
793
794 if (ldstQueue.numLoads(tid) > 0 ) {
795
796 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
797 tid,ldstQueue.getLoadHeadSeqNum(tid));
798 }
799
800 if (ldstQueue.numStores(tid) > 0) {
801
802 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
803 tid,ldstQueue.getStoreHeadSeqNum(tid));
804 }
805
806 ret_val = true;
807 } else if (ldstQueue.isStalled(tid)) {
808 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
809 ret_val = true;
810 }
811
812 return ret_val;
813}
814
815template <class Impl>
816void
817DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
818{
819 // Check if there's a squash signal, squash if there is
820 // Check stall signals, block if there is.
821 // If status was Blocked
822 // if so then go to unblocking
823 // If status was Squashing
824 // check if squashing is not high. Switch to running this cycle.
825
826 readStallSignals(tid);
827
828 if (fromCommit->commitInfo[tid].squash) {
829 squash(tid);
830
831 if (dispatchStatus[tid] == Blocked ||
832 dispatchStatus[tid] == Unblocking) {
833 toRename->iewUnblock[tid] = true;
834 wroteToTimeBuffer = true;
835 }
836
837 dispatchStatus[tid] = Squashing;
838
839 fetchRedirect[tid] = false;
840 return;
841 }
842
843 if (fromCommit->commitInfo[tid].robSquashing) {
844 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
845
846 dispatchStatus[tid] = Squashing;
847
848 emptyRenameInsts(tid);
849 wroteToTimeBuffer = true;
850 return;
851 }
852
853 if (checkStall(tid)) {
854 block(tid);
855 dispatchStatus[tid] = Blocked;
856 return;
857 }
858
859 if (dispatchStatus[tid] == Blocked) {
860 // Status from previous cycle was blocked, but there are no more stall
861 // conditions. Switch over to unblocking.
862 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
863 tid);
864
865 dispatchStatus[tid] = Unblocking;
866
867 unblock(tid);
868
869 return;
870 }
871
872 if (dispatchStatus[tid] == Squashing) {
873 // Switch status to running if rename isn't being told to block or
874 // squash this cycle.
875 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
876 tid);
877
878 dispatchStatus[tid] = Running;
879
880 return;
881 }
882}
883
884template <class Impl>
885void
886DefaultIEW<Impl>::sortInsts()
887{
888 int insts_from_rename = fromRename->size;
889#ifdef DEBUG
890#if !ISA_HAS_DELAY_SLOT
891 for (int i = 0; i < numThreads; i++)
892 assert(insts[i].empty());
893#endif
894#endif
895 for (int i = 0; i < insts_from_rename; ++i) {
896 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
897 }
898}
899
900template <class Impl>
901void
902DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
903{
904 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
905 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
906
907 while (!insts[tid].empty()) {
908#if ISA_HAS_DELAY_SLOT
909 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
910 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
911 " that occurs at or before delay slot [sn:%i].\n",
912 tid, bdelayDoneSeqNum[tid]);
913 break;
914 } else {
915 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
916 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
917 }
918#endif
919
920 if (insts[tid].front()->isLoad() ||
921 insts[tid].front()->isStore() ) {
922 toRename->iewInfo[tid].dispatchedToLSQ++;
923 }
924
925 toRename->iewInfo[tid].dispatched++;
926
927 insts[tid].pop();
928 }
929}
930
931template <class Impl>
932void
933DefaultIEW<Impl>::wakeCPU()
934{
935 cpu->wakeCPU();
936}
937
938template <class Impl>
939void
940DefaultIEW<Impl>::activityThisCycle()
941{
942 DPRINTF(Activity, "Activity this cycle.\n");
943 cpu->activityThisCycle();
944}
945
946template <class Impl>
947inline void
948DefaultIEW<Impl>::activateStage()
949{
950 DPRINTF(Activity, "Activating stage.\n");
951 cpu->activateStage(O3CPU::IEWIdx);
952}
953
954template <class Impl>
955inline void
956DefaultIEW<Impl>::deactivateStage()
957{
958 DPRINTF(Activity, "Deactivating stage.\n");
959 cpu->deactivateStage(O3CPU::IEWIdx);
960}
961
962template<class Impl>
963void
964DefaultIEW<Impl>::dispatch(unsigned tid)
965{
966 // If status is Running or idle,
967 // call dispatchInsts()
968 // If status is Unblocking,
969 // buffer any instructions coming from rename
970 // continue trying to empty skid buffer
971 // check if stall conditions have passed
972
973 if (dispatchStatus[tid] == Blocked) {
974 ++iewBlockCycles;
975
976 } else if (dispatchStatus[tid] == Squashing) {
977 ++iewSquashCycles;
978 }
979
980 // Dispatch should try to dispatch as many instructions as its bandwidth
981 // will allow, as long as it is not currently blocked.
982 if (dispatchStatus[tid] == Running ||
983 dispatchStatus[tid] == Idle) {
984 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
985 "dispatch.\n", tid);
986
987 dispatchInsts(tid);
988 } else if (dispatchStatus[tid] == Unblocking) {
989 // Make sure that the skid buffer has something in it if the
990 // status is unblocking.
991 assert(!skidsEmpty());
992
993 // If the status was unblocking, then instructions from the skid
994 // buffer were used. Remove those instructions and handle
995 // the rest of unblocking.
996 dispatchInsts(tid);
997
998 ++iewUnblockCycles;
999
1000 if (validInstsFromRename() && dispatchedAllInsts) {
1001 // Add the current inputs to the skid buffer so they can be
1002 // reprocessed when this stage unblocks.
1003 skidInsert(tid);
1004 }
1005
1006 unblock(tid);
1007 }
1008}
1009
1010template <class Impl>
1011void
1012DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1013{
1014 dispatchedAllInsts = true;
1015
1016 // Obtain instructions from skid buffer if unblocking, or queue from rename
1017 // otherwise.
1018 std::queue<DynInstPtr> &insts_to_dispatch =
1019 dispatchStatus[tid] == Unblocking ?
1020 skidBuffer[tid] : insts[tid];
1021
1022 int insts_to_add = insts_to_dispatch.size();
1023
1024 DynInstPtr inst;
1025 bool add_to_iq = false;
1026 int dis_num_inst = 0;
1027
1028 // Loop through the instructions, putting them in the instruction
1029 // queue.
1030 for ( ; dis_num_inst < insts_to_add &&
1031 dis_num_inst < dispatchWidth;
1032 ++dis_num_inst)
1033 {
1034 inst = insts_to_dispatch.front();
1035
1036 if (dispatchStatus[tid] == Unblocking) {
1037 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1038 "buffer\n", tid);
1039 }
1040
1041 // Make sure there's a valid instruction there.
1042 assert(inst);
1043
1044 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1045 "IQ.\n",
1046 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1047
1048 // Be sure to mark these instructions as ready so that the
1049 // commit stage can go ahead and execute them, and mark
1050 // them as issued so the IQ doesn't reprocess them.
1051
1052 // Check for squashed instructions.
1053 if (inst->isSquashed()) {
1054 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1055 "not adding to IQ.\n", tid);
1056
1057 ++iewDispSquashedInsts;
1058
1059 insts_to_dispatch.pop();
1060
1061 //Tell Rename That An Instruction has been processed
1062 if (inst->isLoad() || inst->isStore()) {
1063 toRename->iewInfo[tid].dispatchedToLSQ++;
1064 }
1065 toRename->iewInfo[tid].dispatched++;
1066
1067 continue;
1068 }
1069
1070 // Check for full conditions.
1071 if (instQueue.isFull(tid)) {
1072 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1073
1074 // Call function to start blocking.
1075 block(tid);
1076
1077 // Set unblock to false. Special case where we are using
1078 // skidbuffer (unblocking) instructions but then we still
1079 // get full in the IQ.
1080 toRename->iewUnblock[tid] = false;
1081
1082 dispatchedAllInsts = false;
1083
1084 ++iewIQFullEvents;
1085 break;
1086 } else if (ldstQueue.isFull(tid)) {
1087 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1088
1089 // Call function to start blocking.
1090 block(tid);
1091
1092 // Set unblock to false. Special case where we are using
1093 // skidbuffer (unblocking) instructions but then we still
1094 // get full in the IQ.
1095 toRename->iewUnblock[tid] = false;
1096
1097 dispatchedAllInsts = false;
1098
1099 ++iewLSQFullEvents;
1100 break;
1101 }
1102
1103 // Otherwise issue the instruction just fine.
1104 if (inst->isLoad()) {
1105 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1106 "encountered, adding to LSQ.\n", tid);
1107
1108 // Reserve a spot in the load store queue for this
1109 // memory access.
1110 ldstQueue.insertLoad(inst);
1111
1112 ++iewDispLoadInsts;
1113
1114 add_to_iq = true;
1115
1116 toRename->iewInfo[tid].dispatchedToLSQ++;
1117 } else if (inst->isStore()) {
1118 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1119 "encountered, adding to LSQ.\n", tid);
1120
1121 ldstQueue.insertStore(inst);
1122
1123 ++iewDispStoreInsts;
1124
1125 if (inst->isStoreConditional()) {
1126 // Store conditionals need to be set as "canCommit()"
1127 // so that commit can process them when they reach the
1128 // head of commit.
1129 // @todo: This is somewhat specific to Alpha.
1130 inst->setCanCommit();
1131 instQueue.insertNonSpec(inst);
1132 add_to_iq = false;
1133
1134 ++iewDispNonSpecInsts;
1135 } else {
1136 add_to_iq = true;
1137 }
1138
1139 toRename->iewInfo[tid].dispatchedToLSQ++;
|
| 1140#if FULL_SYSTEM
|
1127 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1128 // Same as non-speculative stores.
1129 inst->setCanCommit();
1130 instQueue.insertBarrier(inst);
1131 add_to_iq = false;
| 1141 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1142 // Same as non-speculative stores.
1143 inst->setCanCommit();
1144 instQueue.insertBarrier(inst);
1145 add_to_iq = false;
|
| 1146#endif
|
1132 } else if (inst->isNonSpeculative()) {
1133 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1134 "encountered, skipping.\n", tid);
1135
1136 // Same as non-speculative stores.
1137 inst->setCanCommit();
1138
1139 // Specifically insert it as nonspeculative.
1140 instQueue.insertNonSpec(inst);
1141
1142 ++iewDispNonSpecInsts;
1143
1144 add_to_iq = false;
1145 } else if (inst->isNop()) {
1146 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1147 "skipping.\n", tid);
1148
1149 inst->setIssued();
1150 inst->setExecuted();
1151 inst->setCanCommit();
1152
1153 instQueue.recordProducer(inst);
1154
1155 iewExecutedNop[tid]++;
1156
1157 add_to_iq = false;
1158 } else if (inst->isExecuted()) {
1159 assert(0 && "Instruction shouldn't be executed.\n");
1160 DPRINTF(IEW, "Issue: Executed branch encountered, "
1161 "skipping.\n");
1162
1163 inst->setIssued();
1164 inst->setCanCommit();
1165
1166 instQueue.recordProducer(inst);
1167
1168 add_to_iq = false;
1169 } else {
1170 add_to_iq = true;
1171 }
1172
1173 // If the instruction queue is not full, then add the
1174 // instruction.
1175 if (add_to_iq) {
1176 instQueue.insert(inst);
1177 }
1178
1179 insts_to_dispatch.pop();
1180
1181 toRename->iewInfo[tid].dispatched++;
1182
1183 ++iewDispatchedInsts;
1184 }
1185
1186 if (!insts_to_dispatch.empty()) {
1187 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1188 block(tid);
1189 toRename->iewUnblock[tid] = false;
1190 }
1191
1192 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1193 dispatchStatus[tid] = Running;
1194
1195 updatedQueues = true;
1196 }
1197
1198 dis_num_inst = 0;
1199}
1200
1201template <class Impl>
1202void
1203DefaultIEW<Impl>::printAvailableInsts()
1204{
1205 int inst = 0;
1206
1207 std::cout << "Available Instructions: ";
1208
1209 while (fromIssue->insts[inst]) {
1210
1211 if (inst%3==0) std::cout << "\n\t";
1212
1213 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1214 << " TN: " << fromIssue->insts[inst]->threadNumber
1215 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1216
1217 inst++;
1218
1219 }
1220
1221 std::cout << "\n";
1222}
1223
1224template <class Impl>
1225void
1226DefaultIEW<Impl>::executeInsts()
1227{
1228 wbNumInst = 0;
1229 wbCycle = 0;
1230
| 1147 } else if (inst->isNonSpeculative()) {
1148 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1149 "encountered, skipping.\n", tid);
1150
1151 // Same as non-speculative stores.
1152 inst->setCanCommit();
1153
1154 // Specifically insert it as nonspeculative.
1155 instQueue.insertNonSpec(inst);
1156
1157 ++iewDispNonSpecInsts;
1158
1159 add_to_iq = false;
1160 } else if (inst->isNop()) {
1161 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1162 "skipping.\n", tid);
1163
1164 inst->setIssued();
1165 inst->setExecuted();
1166 inst->setCanCommit();
1167
1168 instQueue.recordProducer(inst);
1169
1170 iewExecutedNop[tid]++;
1171
1172 add_to_iq = false;
1173 } else if (inst->isExecuted()) {
1174 assert(0 && "Instruction shouldn't be executed.\n");
1175 DPRINTF(IEW, "Issue: Executed branch encountered, "
1176 "skipping.\n");
1177
1178 inst->setIssued();
1179 inst->setCanCommit();
1180
1181 instQueue.recordProducer(inst);
1182
1183 add_to_iq = false;
1184 } else {
1185 add_to_iq = true;
1186 }
1187
1188 // If the instruction queue is not full, then add the
1189 // instruction.
1190 if (add_to_iq) {
1191 instQueue.insert(inst);
1192 }
1193
1194 insts_to_dispatch.pop();
1195
1196 toRename->iewInfo[tid].dispatched++;
1197
1198 ++iewDispatchedInsts;
1199 }
1200
1201 if (!insts_to_dispatch.empty()) {
1202 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1203 block(tid);
1204 toRename->iewUnblock[tid] = false;
1205 }
1206
1207 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1208 dispatchStatus[tid] = Running;
1209
1210 updatedQueues = true;
1211 }
1212
1213 dis_num_inst = 0;
1214}
1215
1216template <class Impl>
1217void
1218DefaultIEW<Impl>::printAvailableInsts()
1219{
1220 int inst = 0;
1221
1222 std::cout << "Available Instructions: ";
1223
1224 while (fromIssue->insts[inst]) {
1225
1226 if (inst%3==0) std::cout << "\n\t";
1227
1228 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1229 << " TN: " << fromIssue->insts[inst]->threadNumber
1230 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1231
1232 inst++;
1233
1234 }
1235
1236 std::cout << "\n";
1237}
1238
1239template <class Impl>
1240void
1241DefaultIEW<Impl>::executeInsts()
1242{
1243 wbNumInst = 0;
1244 wbCycle = 0;
1245
|
1231 std::list<unsigned>::iterator threads = activeThreads->begin();
1232 std::list<unsigned>::iterator end = activeThreads->end();
| 1246 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
1233
| 1247
|
1234 while (threads != end) {
| 1248 while (threads != (*activeThreads).end()) {
|
1235 unsigned tid = *threads++;
1236 fetchRedirect[tid] = false;
1237 }
1238
1239 // Uncomment this if you want to see all available instructions.
1240// printAvailableInsts();
1241
1242 // Execute/writeback any instructions that are available.
1243 int insts_to_execute = fromIssue->size;
1244 int inst_num = 0;
1245 for (; inst_num < insts_to_execute;
1246 ++inst_num) {
1247
1248 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1249
1250 DynInstPtr inst = instQueue.getInstToExecute();
1251
1252 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1253 inst->readPC(), inst->threadNumber,inst->seqNum);
1254
1255 // Check if the instruction is squashed; if so then skip it
1256 if (inst->isSquashed()) {
1257 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1258
1259 // Consider this instruction executed so that commit can go
1260 // ahead and retire the instruction.
1261 inst->setExecuted();
1262
1263 // Not sure if I should set this here or just let commit try to
1264 // commit any squashed instructions. I like the latter a bit more.
1265 inst->setCanCommit();
1266
1267 ++iewExecSquashedInsts;
1268
1269 decrWb(inst->seqNum);
1270 continue;
1271 }
1272
1273 Fault fault = NoFault;
1274
1275 // Execute instruction.
1276 // Note that if the instruction faults, it will be handled
1277 // at the commit stage.
1278 if (inst->isMemRef() &&
1279 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1280 DPRINTF(IEW, "Execute: Calculating address for memory "
1281 "reference.\n");
1282
1283 // Tell the LDSTQ to execute this instruction (if it is a load).
1284 if (inst->isLoad()) {
1285 // Loads will mark themselves as executed, and their writeback
1286 // event adds the instruction to the queue to commit
1287 fault = ldstQueue.executeLoad(inst);
1288 } else if (inst->isStore()) {
1289 fault = ldstQueue.executeStore(inst);
1290
1291 // If the store had a fault then it may not have a mem req
1292 if (!inst->isStoreConditional() && fault == NoFault) {
1293 inst->setExecuted();
1294
1295 instToCommit(inst);
1296 } else if (fault != NoFault) {
1297 // If the instruction faulted, then we need to send it along to commit
1298 // without the instruction completing.
1299 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1300 fault->name(), inst->seqNum);
1301
1302 // Send this instruction to commit, also make sure iew stage
1303 // realizes there is activity.
1304 inst->setExecuted();
1305
1306 instToCommit(inst);
1307 activityThisCycle();
1308 }
1309
1310 // Store conditionals will mark themselves as
1311 // executed, and their writeback event will add the
1312 // instruction to the queue to commit.
1313 } else {
1314 panic("Unexpected memory type!\n");
1315 }
1316
1317 } else {
1318 inst->execute();
1319
1320 inst->setExecuted();
1321
1322 instToCommit(inst);
1323 }
1324
1325 updateExeInstStats(inst);
1326
1327 // Check if branch prediction was correct, if not then we need
1328 // to tell commit to squash in flight instructions. Only
1329 // handle this if there hasn't already been something that
1330 // redirects fetch in this group of instructions.
1331
1332 // This probably needs to prioritize the redirects if a different
1333 // scheduler is used. Currently the scheduler schedules the oldest
1334 // instruction first, so the branch resolution order will be correct.
1335 unsigned tid = inst->threadNumber;
1336
1337 if (!fetchRedirect[tid] ||
1338 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1339
1340 if (inst->mispredicted()) {
1341 fetchRedirect[tid] = true;
1342
1343 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
| 1249 unsigned tid = *threads++;
1250 fetchRedirect[tid] = false;
1251 }
1252
1253 // Uncomment this if you want to see all available instructions.
1254// printAvailableInsts();
1255
1256 // Execute/writeback any instructions that are available.
1257 int insts_to_execute = fromIssue->size;
1258 int inst_num = 0;
1259 for (; inst_num < insts_to_execute;
1260 ++inst_num) {
1261
1262 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1263
1264 DynInstPtr inst = instQueue.getInstToExecute();
1265
1266 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1267 inst->readPC(), inst->threadNumber,inst->seqNum);
1268
1269 // Check if the instruction is squashed; if so then skip it
1270 if (inst->isSquashed()) {
1271 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1272
1273 // Consider this instruction executed so that commit can go
1274 // ahead and retire the instruction.
1275 inst->setExecuted();
1276
1277 // Not sure if I should set this here or just let commit try to
1278 // commit any squashed instructions. I like the latter a bit more.
1279 inst->setCanCommit();
1280
1281 ++iewExecSquashedInsts;
1282
1283 decrWb(inst->seqNum);
1284 continue;
1285 }
1286
1287 Fault fault = NoFault;
1288
1289 // Execute instruction.
1290 // Note that if the instruction faults, it will be handled
1291 // at the commit stage.
1292 if (inst->isMemRef() &&
1293 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1294 DPRINTF(IEW, "Execute: Calculating address for memory "
1295 "reference.\n");
1296
1297 // Tell the LDSTQ to execute this instruction (if it is a load).
1298 if (inst->isLoad()) {
1299 // Loads will mark themselves as executed, and their writeback
1300 // event adds the instruction to the queue to commit
1301 fault = ldstQueue.executeLoad(inst);
1302 } else if (inst->isStore()) {
1303 fault = ldstQueue.executeStore(inst);
1304
1305 // If the store had a fault then it may not have a mem req
1306 if (!inst->isStoreConditional() && fault == NoFault) {
1307 inst->setExecuted();
1308
1309 instToCommit(inst);
1310 } else if (fault != NoFault) {
1311 // If the instruction faulted, then we need to send it along to commit
1312 // without the instruction completing.
1313 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1314 fault->name(), inst->seqNum);
1315
1316 // Send this instruction to commit, also make sure iew stage
1317 // realizes there is activity.
1318 inst->setExecuted();
1319
1320 instToCommit(inst);
1321 activityThisCycle();
1322 }
1323
1324 // Store conditionals will mark themselves as
1325 // executed, and their writeback event will add the
1326 // instruction to the queue to commit.
1327 } else {
1328 panic("Unexpected memory type!\n");
1329 }
1330
1331 } else {
1332 inst->execute();
1333
1334 inst->setExecuted();
1335
1336 instToCommit(inst);
1337 }
1338
1339 updateExeInstStats(inst);
1340
1341 // Check if branch prediction was correct, if not then we need
1342 // to tell commit to squash in flight instructions. Only
1343 // handle this if there hasn't already been something that
1344 // redirects fetch in this group of instructions.
1345
1346 // This probably needs to prioritize the redirects if a different
1347 // scheduler is used. Currently the scheduler schedules the oldest
1348 // instruction first, so the branch resolution order will be correct.
1349 unsigned tid = inst->threadNumber;
1350
1351 if (!fetchRedirect[tid] ||
1352 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1353
1354 if (inst->mispredicted()) {
1355 fetchRedirect[tid] = true;
1356
1357 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
|
| 1358 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC);
|
1344#if ISA_HAS_DELAY_SLOT
1345 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1346 inst->nextNPC);
1347#else
1348 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1349 inst->nextPC);
1350#endif
1351 // If incorrect, then signal the ROB that it must be squashed.
1352 squashDueToBranch(inst, tid);
1353
| 1359#if ISA_HAS_DELAY_SLOT
1360 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1361 inst->nextNPC);
1362#else
1363 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1364 inst->nextPC);
1365#endif
1366 // If incorrect, then signal the ROB that it must be squashed.
1367 squashDueToBranch(inst, tid);
1368
|
1354 if (inst->predTaken()) {
| 1369 if (inst->readPredTaken()) {
|
1355 predictedTakenIncorrect++;
1356 } else {
1357 predictedNotTakenIncorrect++;
1358 }
1359 } else if (ldstQueue.violation(tid)) {
1360 // If there was an ordering violation, then get the
1361 // DynInst that caused the violation. Note that this
1362 // clears the violation signal.
1363 DynInstPtr violator;
1364 violator = ldstQueue.getMemDepViolator(tid);
1365
1366 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1367 "%#x, inst PC: %#x. Addr is: %#x.\n",
1368 violator->readPC(), inst->readPC(), inst->physEffAddr);
1369
1370 // Ensure the violating instruction is older than
1371 // current squash
1372 if (fetchRedirect[tid] &&
1373 violator->seqNum >= toCommit->squashedSeqNum[tid])
1374 continue;
1375
1376 fetchRedirect[tid] = true;
1377
1378 // Tell the instruction queue that a violation has occured.
1379 instQueue.violation(inst, violator);
1380
1381 // Squash.
1382 squashDueToMemOrder(inst,tid);
1383
1384 ++memOrderViolationEvents;
1385 } else if (ldstQueue.loadBlocked(tid) &&
1386 !ldstQueue.isLoadBlockedHandled(tid)) {
1387 fetchRedirect[tid] = true;
1388
1389 DPRINTF(IEW, "Load operation couldn't execute because the "
1390 "memory system is blocked. PC: %#x [sn:%lli]\n",
1391 inst->readPC(), inst->seqNum);
1392
1393 squashDueToMemBlocked(inst, tid);
1394 }
1395 }
1396 }
1397
1398 // Update and record activity if we processed any instructions.
1399 if (inst_num) {
1400 if (exeStatus == Idle) {
1401 exeStatus = Running;
1402 }
1403
1404 updatedQueues = true;
1405
1406 cpu->activityThisCycle();
1407 }
1408
1409 // Need to reset this in case a writeback event needs to write into the
1410 // iew queue. That way the writeback event will write into the correct
1411 // spot in the queue.
1412 wbNumInst = 0;
1413}
1414
1415template <class Impl>
1416void
1417DefaultIEW<Impl>::writebackInsts()
1418{
1419 // Loop through the head of the time buffer and wake any
1420 // dependents. These instructions are about to write back. Also
1421 // mark scoreboard that this instruction is finally complete.
1422 // Either have IEW have direct access to scoreboard, or have this
1423 // as part of backwards communication.
1424 for (int inst_num = 0; inst_num < issueWidth &&
1425 toCommit->insts[inst_num]; inst_num++) {
1426 DynInstPtr inst = toCommit->insts[inst_num];
1427 int tid = inst->threadNumber;
1428
1429 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1430 inst->seqNum, inst->readPC());
1431
1432 iewInstsToCommit[tid]++;
1433
1434 // Some instructions will be sent to commit without having
1435 // executed because they need commit to handle them.
1436 // E.g. Uncached loads have not actually executed when they
1437 // are first sent to commit. Instead commit must tell the LSQ
1438 // when it's ready to execute the uncached load.
1439 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1440 int dependents = instQueue.wakeDependents(inst);
1441
1442 for (int i = 0; i < inst->numDestRegs(); i++) {
1443 //mark as Ready
1444 DPRINTF(IEW,"Setting Destination Register %i\n",
1445 inst->renamedDestRegIdx(i));
1446 scoreboard->setReg(inst->renamedDestRegIdx(i));
1447 }
1448
1449 if (dependents) {
1450 producerInst[tid]++;
1451 consumerInst[tid]+= dependents;
1452 }
1453 writebackCount[tid]++;
1454 }
1455
1456 decrWb(inst->seqNum);
1457 }
1458}
1459
1460template<class Impl>
1461void
1462DefaultIEW<Impl>::tick()
1463{
1464 wbNumInst = 0;
1465 wbCycle = 0;
1466
1467 wroteToTimeBuffer = false;
1468 updatedQueues = false;
1469
1470 sortInsts();
1471
1472 // Free function units marked as being freed this cycle.
1473 fuPool->processFreeUnits();
1474
| 1370 predictedTakenIncorrect++;
1371 } else {
1372 predictedNotTakenIncorrect++;
1373 }
1374 } else if (ldstQueue.violation(tid)) {
1375 // If there was an ordering violation, then get the
1376 // DynInst that caused the violation. Note that this
1377 // clears the violation signal.
1378 DynInstPtr violator;
1379 violator = ldstQueue.getMemDepViolator(tid);
1380
1381 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1382 "%#x, inst PC: %#x. Addr is: %#x.\n",
1383 violator->readPC(), inst->readPC(), inst->physEffAddr);
1384
1385 // Ensure the violating instruction is older than
1386 // current squash
1387 if (fetchRedirect[tid] &&
1388 violator->seqNum >= toCommit->squashedSeqNum[tid])
1389 continue;
1390
1391 fetchRedirect[tid] = true;
1392
1393 // Tell the instruction queue that a violation has occured.
1394 instQueue.violation(inst, violator);
1395
1396 // Squash.
1397 squashDueToMemOrder(inst,tid);
1398
1399 ++memOrderViolationEvents;
1400 } else if (ldstQueue.loadBlocked(tid) &&
1401 !ldstQueue.isLoadBlockedHandled(tid)) {
1402 fetchRedirect[tid] = true;
1403
1404 DPRINTF(IEW, "Load operation couldn't execute because the "
1405 "memory system is blocked. PC: %#x [sn:%lli]\n",
1406 inst->readPC(), inst->seqNum);
1407
1408 squashDueToMemBlocked(inst, tid);
1409 }
1410 }
1411 }
1412
1413 // Update and record activity if we processed any instructions.
1414 if (inst_num) {
1415 if (exeStatus == Idle) {
1416 exeStatus = Running;
1417 }
1418
1419 updatedQueues = true;
1420
1421 cpu->activityThisCycle();
1422 }
1423
1424 // Need to reset this in case a writeback event needs to write into the
1425 // iew queue. That way the writeback event will write into the correct
1426 // spot in the queue.
1427 wbNumInst = 0;
1428}
1429
1430template <class Impl>
1431void
1432DefaultIEW<Impl>::writebackInsts()
1433{
1434 // Loop through the head of the time buffer and wake any
1435 // dependents. These instructions are about to write back. Also
1436 // mark scoreboard that this instruction is finally complete.
1437 // Either have IEW have direct access to scoreboard, or have this
1438 // as part of backwards communication.
1439 for (int inst_num = 0; inst_num < issueWidth &&
1440 toCommit->insts[inst_num]; inst_num++) {
1441 DynInstPtr inst = toCommit->insts[inst_num];
1442 int tid = inst->threadNumber;
1443
1444 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1445 inst->seqNum, inst->readPC());
1446
1447 iewInstsToCommit[tid]++;
1448
1449 // Some instructions will be sent to commit without having
1450 // executed because they need commit to handle them.
1451 // E.g. Uncached loads have not actually executed when they
1452 // are first sent to commit. Instead commit must tell the LSQ
1453 // when it's ready to execute the uncached load.
1454 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1455 int dependents = instQueue.wakeDependents(inst);
1456
1457 for (int i = 0; i < inst->numDestRegs(); i++) {
1458 //mark as Ready
1459 DPRINTF(IEW,"Setting Destination Register %i\n",
1460 inst->renamedDestRegIdx(i));
1461 scoreboard->setReg(inst->renamedDestRegIdx(i));
1462 }
1463
1464 if (dependents) {
1465 producerInst[tid]++;
1466 consumerInst[tid]+= dependents;
1467 }
1468 writebackCount[tid]++;
1469 }
1470
1471 decrWb(inst->seqNum);
1472 }
1473}
1474
1475template<class Impl>
1476void
1477DefaultIEW<Impl>::tick()
1478{
1479 wbNumInst = 0;
1480 wbCycle = 0;
1481
1482 wroteToTimeBuffer = false;
1483 updatedQueues = false;
1484
1485 sortInsts();
1486
1487 // Free function units marked as being freed this cycle.
1488 fuPool->processFreeUnits();
1489
|
1475 std::list<unsigned>::iterator threads = activeThreads->begin();
1476 std::list<unsigned>::iterator end = activeThreads->end();
| 1490 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
1477
1478 // Check stall and squash signals, dispatch any instructions.
| 1491
1492 // Check stall and squash signals, dispatch any instructions.
|
1479 while (threads != end) {
1480 unsigned tid = *threads++;
| 1493 while (threads != (*activeThreads).end()) {
1494 unsigned tid = *threads++;
|
1481
1482 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1483
1484 checkSignalsAndUpdate(tid);
1485 dispatch(tid);
1486 }
1487
1488 if (exeStatus != Squashing) {
1489 executeInsts();
1490
1491 writebackInsts();
1492
1493 // Have the instruction queue try to schedule any ready instructions.
1494 // (In actuality, this scheduling is for instructions that will
1495 // be executed next cycle.)
1496 instQueue.scheduleReadyInsts();
1497
1498 // Also should advance its own time buffers if the stage ran.
1499 // Not the best place for it, but this works (hopefully).
1500 issueToExecQueue.advance();
1501 }
1502
1503 bool broadcast_free_entries = false;
1504
1505 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1506 exeStatus = Idle;
1507 updateLSQNextCycle = false;
1508
1509 broadcast_free_entries = true;
1510 }
1511
1512 // Writeback any stores using any leftover bandwidth.
1513 ldstQueue.writebackStores();
1514
1515 // Check the committed load/store signals to see if there's a load
1516 // or store to commit. Also check if it's being told to execute a
1517 // nonspeculative instruction.
1518 // This is pretty inefficient...
1519
| 1495
1496 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1497
1498 checkSignalsAndUpdate(tid);
1499 dispatch(tid);
1500 }
1501
1502 if (exeStatus != Squashing) {
1503 executeInsts();
1504
1505 writebackInsts();
1506
1507 // Have the instruction queue try to schedule any ready instructions.
1508 // (In actuality, this scheduling is for instructions that will
1509 // be executed next cycle.)
1510 instQueue.scheduleReadyInsts();
1511
1512 // Also should advance its own time buffers if the stage ran.
1513 // Not the best place for it, but this works (hopefully).
1514 issueToExecQueue.advance();
1515 }
1516
1517 bool broadcast_free_entries = false;
1518
1519 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1520 exeStatus = Idle;
1521 updateLSQNextCycle = false;
1522
1523 broadcast_free_entries = true;
1524 }
1525
1526 // Writeback any stores using any leftover bandwidth.
1527 ldstQueue.writebackStores();
1528
1529 // Check the committed load/store signals to see if there's a load
1530 // or store to commit. Also check if it's being told to execute a
1531 // nonspeculative instruction.
1532 // This is pretty inefficient...
1533
|
1520 threads = activeThreads->begin();
1521 while (threads != end) {
| 1534 threads = (*activeThreads).begin();
1535 while (threads != (*activeThreads).end()) {
|
1522 unsigned tid = (*threads++);
1523
1524 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1525
1526 // Update structures based on instructions committed.
1527 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1528 !fromCommit->commitInfo[tid].squash &&
1529 !fromCommit->commitInfo[tid].robSquashing) {
1530
1531 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1532
1533 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1534
1535 updateLSQNextCycle = true;
1536 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1537 }
1538
1539 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1540
1541 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1542 if (fromCommit->commitInfo[tid].uncached) {
1543 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1544 } else {
1545 instQueue.scheduleNonSpec(
1546 fromCommit->commitInfo[tid].nonSpecSeqNum);
1547 }
1548 }
1549
1550 if (broadcast_free_entries) {
1551 toFetch->iewInfo[tid].iqCount =
1552 instQueue.getCount(tid);
1553 toFetch->iewInfo[tid].ldstqCount =
1554 ldstQueue.getCount(tid);
1555
1556 toRename->iewInfo[tid].usedIQ = true;
1557 toRename->iewInfo[tid].freeIQEntries =
1558 instQueue.numFreeEntries();
1559 toRename->iewInfo[tid].usedLSQ = true;
1560 toRename->iewInfo[tid].freeLSQEntries =
1561 ldstQueue.numFreeEntries(tid);
1562
1563 wroteToTimeBuffer = true;
1564 }
1565
1566 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1567 tid, toRename->iewInfo[tid].dispatched);
1568 }
1569
1570 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1571 "LSQ has %i free entries.\n",
1572 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1573 ldstQueue.numFreeEntries());
1574
1575 updateStatus();
1576
1577 if (wroteToTimeBuffer) {
1578 DPRINTF(Activity, "Activity this cycle.\n");
1579 cpu->activityThisCycle();
1580 }
1581}
1582
1583template <class Impl>
1584void
1585DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1586{
1587 int thread_number = inst->threadNumber;
1588
1589 //
1590 // Pick off the software prefetches
1591 //
1592#ifdef TARGET_ALPHA
1593 if (inst->isDataPrefetch())
1594 iewExecutedSwp[thread_number]++;
1595 else
1596 iewIewExecutedcutedInsts++;
1597#else
1598 iewExecutedInsts++;
1599#endif
1600
1601 //
1602 // Control operations
1603 //
1604 if (inst->isControl())
1605 iewExecutedBranches[thread_number]++;
1606
1607 //
1608 // Memory operations
1609 //
1610 if (inst->isMemRef()) {
1611 iewExecutedRefs[thread_number]++;
1612
1613 if (inst->isLoad()) {
1614 iewExecLoadInsts[thread_number]++;
1615 }
1616 }
1617}
| 1536 unsigned tid = (*threads++);
1537
1538 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1539
1540 // Update structures based on instructions committed.
1541 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1542 !fromCommit->commitInfo[tid].squash &&
1543 !fromCommit->commitInfo[tid].robSquashing) {
1544
1545 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1546
1547 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1548
1549 updateLSQNextCycle = true;
1550 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1551 }
1552
1553 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1554
1555 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1556 if (fromCommit->commitInfo[tid].uncached) {
1557 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1558 } else {
1559 instQueue.scheduleNonSpec(
1560 fromCommit->commitInfo[tid].nonSpecSeqNum);
1561 }
1562 }
1563
1564 if (broadcast_free_entries) {
1565 toFetch->iewInfo[tid].iqCount =
1566 instQueue.getCount(tid);
1567 toFetch->iewInfo[tid].ldstqCount =
1568 ldstQueue.getCount(tid);
1569
1570 toRename->iewInfo[tid].usedIQ = true;
1571 toRename->iewInfo[tid].freeIQEntries =
1572 instQueue.numFreeEntries();
1573 toRename->iewInfo[tid].usedLSQ = true;
1574 toRename->iewInfo[tid].freeLSQEntries =
1575 ldstQueue.numFreeEntries(tid);
1576
1577 wroteToTimeBuffer = true;
1578 }
1579
1580 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1581 tid, toRename->iewInfo[tid].dispatched);
1582 }
1583
1584 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1585 "LSQ has %i free entries.\n",
1586 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1587 ldstQueue.numFreeEntries());
1588
1589 updateStatus();
1590
1591 if (wroteToTimeBuffer) {
1592 DPRINTF(Activity, "Activity this cycle.\n");
1593 cpu->activityThisCycle();
1594 }
1595}
1596
1597template <class Impl>
1598void
1599DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1600{
1601 int thread_number = inst->threadNumber;
1602
1603 //
1604 // Pick off the software prefetches
1605 //
1606#ifdef TARGET_ALPHA
1607 if (inst->isDataPrefetch())
1608 iewExecutedSwp[thread_number]++;
1609 else
1610 iewIewExecutedcutedInsts++;
1611#else
1612 iewExecutedInsts++;
1613#endif
1614
1615 //
1616 // Control operations
1617 //
1618 if (inst->isControl())
1619 iewExecutedBranches[thread_number]++;
1620
1621 //
1622 // Memory operations
1623 //
1624 if (inst->isMemRef()) {
1625 iewExecutedRefs[thread_number]++;
1626
1627 if (inst->isLoad()) {
1628 iewExecLoadInsts[thread_number]++;
1629 }
1630 }
1631}
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