1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43 : issueToExecQueue(params->backComSize, params->forwardComSize),
44 instQueue(params),
45 ldstQueue(params),
46 fuPool(params->fuPool),
47 commitToIEWDelay(params->commitToIEWDelay),
48 renameToIEWDelay(params->renameToIEWDelay),
49 issueToExecuteDelay(params->issueToExecuteDelay),
50 dispatchWidth(params->dispatchWidth),
51 issueWidth(params->issueWidth),
52 wbOutstanding(0),
53 wbWidth(params->wbWidth),
54 numThreads(params->numberOfThreads),
55 switchedOut(false)
56{
57 _status = Active;
58 exeStatus = Running;
59 wbStatus = Idle;
60
61 // Setup wire to read instructions coming from issue.
62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64 // Instruction queue needs the queue between issue and execute.
65 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67 instQueue.setIEW(this);
68 ldstQueue.setIEW(this);
69
70 for (int i=0; i < numThreads; i++) {
71 dispatchStatus[i] = Running;
72 stalls[i].commit = false;
73 fetchRedirect[i] = false;
74 bdelayDoneSeqNum[i] = 0;
75 }
76
77 wbMax = wbWidth * params->wbDepth;
78
79 updateLSQNextCycle = false;
80
81 ableToIssue = true;
82
83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90 return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97 using namespace Stats;
98
99 instQueue.regStats();
100 ldstQueue.regStats();
101
102 iewIdleCycles
103 .name(name() + ".iewIdleCycles")
104 .desc("Number of cycles IEW is idle");
105
106 iewSquashCycles
107 .name(name() + ".iewSquashCycles")
108 .desc("Number of cycles IEW is squashing");
109
110 iewBlockCycles
111 .name(name() + ".iewBlockCycles")
112 .desc("Number of cycles IEW is blocking");
113
114 iewUnblockCycles
115 .name(name() + ".iewUnblockCycles")
116 .desc("Number of cycles IEW is unblocking");
117
118 iewDispatchedInsts
119 .name(name() + ".iewDispatchedInsts")
120 .desc("Number of instructions dispatched to IQ");
121
122 iewDispSquashedInsts
123 .name(name() + ".iewDispSquashedInsts")
124 .desc("Number of squashed instructions skipped by dispatch");
125
126 iewDispLoadInsts
127 .name(name() + ".iewDispLoadInsts")
128 .desc("Number of dispatched load instructions");
129
130 iewDispStoreInsts
131 .name(name() + ".iewDispStoreInsts")
132 .desc("Number of dispatched store instructions");
133
134 iewDispNonSpecInsts
135 .name(name() + ".iewDispNonSpecInsts")
136 .desc("Number of dispatched non-speculative instructions");
137
138 iewIQFullEvents
139 .name(name() + ".iewIQFullEvents")
140 .desc("Number of times the IQ has become full, causing a stall");
141
142 iewLSQFullEvents
143 .name(name() + ".iewLSQFullEvents")
144 .desc("Number of times the LSQ has become full, causing a stall");
145
146 memOrderViolationEvents
147 .name(name() + ".memOrderViolationEvents")
148 .desc("Number of memory order violations");
149
150 predictedTakenIncorrect
151 .name(name() + ".predictedTakenIncorrect")
152 .desc("Number of branches that were predicted taken incorrectly");
153
154 predictedNotTakenIncorrect
155 .name(name() + ".predictedNotTakenIncorrect")
156 .desc("Number of branches that were predicted not taken incorrectly");
157
158 branchMispredicts
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
161
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164 iewExecutedInsts
165 .name(name() + ".iewExecutedInsts")
166 .desc("Number of executed instructions");
167
168 iewExecLoadInsts
169 .init(cpu->number_of_threads)
170 .name(name() + ".iewExecLoadInsts")
171 .desc("Number of load instructions executed")
172 .flags(total);
173
174 iewExecSquashedInsts
175 .name(name() + ".iewExecSquashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
177
178 iewExecutedSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
182 .flags(total);
183
184 iewExecutedNop
185 .init(cpu->number_of_threads)
186 .name(name() + ".EXEC:nop")
187 .desc("number of nop insts executed")
188 .flags(total);
189
190 iewExecutedRefs
191 .init(cpu->number_of_threads)
192 .name(name() + ".EXEC:refs")
193 .desc("number of memory reference insts executed")
194 .flags(total);
195
196 iewExecutedBranches
197 .init(cpu->number_of_threads)
198 .name(name() + ".EXEC:branches")
199 .desc("Number of branches executed")
200 .flags(total);
201
202 iewExecStoreInsts
203 .name(name() + ".EXEC:stores")
204 .desc("Number of stores executed")
205 .flags(total);
206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208 iewExecRate
209 .name(name() + ".EXEC:rate")
210 .desc("Inst execution rate")
211 .flags(total);
212
213 iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215 iewInstsToCommit
216 .init(cpu->number_of_threads)
217 .name(name() + ".WB:sent")
218 .desc("cumulative count of insts sent to commit")
219 .flags(total);
220
221 writebackCount
222 .init(cpu->number_of_threads)
223 .name(name() + ".WB:count")
224 .desc("cumulative count of insts written-back")
225 .flags(total);
226
227 producerInst
228 .init(cpu->number_of_threads)
229 .name(name() + ".WB:producers")
230 .desc("num instructions producing a value")
231 .flags(total);
232
233 consumerInst
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:consumers")
236 .desc("num instructions consuming a value")
237 .flags(total);
238
239 wbPenalized
240 .init(cpu->number_of_threads)
241 .name(name() + ".WB:penalized")
242 .desc("number of instrctions required to write to 'other' IQ")
243 .flags(total);
244
245 wbPenalizedRate
246 .name(name() + ".WB:penalized_rate")
247 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248 .flags(total);
249
250 wbPenalizedRate = wbPenalized / writebackCount;
251
252 wbFanout
253 .name(name() + ".WB:fanout")
254 .desc("average fanout of values written-back")
255 .flags(total);
256
257 wbFanout = producerInst / consumerInst;
258
259 wbRate
260 .name(name() + ".WB:rate")
261 .desc("insts written-back per cycle")
262 .flags(total);
263 wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270 for (int tid=0; tid < numThreads; tid++) {
271 toRename->iewInfo[tid].usedIQ = true;
272 toRename->iewInfo[tid].freeIQEntries =
273 instQueue.numFreeEntries(tid);
274
275 toRename->iewInfo[tid].usedLSQ = true;
276 toRename->iewInfo[tid].freeLSQEntries =
277 ldstQueue.numFreeEntries(tid);
278 }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285 DPRINTF(IEW, "Setting CPU pointer.\n");
286 cpu = cpu_ptr;
287
288 instQueue.setCPU(cpu_ptr);
289 ldstQueue.setCPU(cpu_ptr);
290
291 cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298 DPRINTF(IEW, "Setting time buffer pointer.\n");
299 timeBuffer = tb_ptr;
300
301 // Setup wire to read information from time buffer, from commit.
302 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304 // Setup wire to write information back to previous stages.
305 toRename = timeBuffer->getWire(0);
306
307 toFetch = timeBuffer->getWire(0);
308
309 // Instruction queue also needs main time buffer.
310 instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317 DPRINTF(IEW, "Setting rename queue pointer.\n");
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 DPRINTF(IEW, "Setting IEW queue pointer.\n");
329 iewQueue = iq_ptr;
330
331 // Setup wire to write instructions to commit.
332 toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339 DPRINTF(IEW, "Setting active threads list pointer.\n");
340 activeThreads = at_ptr;
341
342 ldstQueue.setActiveThreads(at_ptr);
343 instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350 DPRINTF(IEW, "Setting scoreboard pointer.\n");
351 scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358 // IEW is ready to drain at any time.
359 cpu->signalDrained();
360 return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373 // Clear any state.
374 switchedOut = true;
375 assert(insts[0].empty());
376 assert(skidBuffer[0].empty());
377
378 instQueue.switchOut();
379 ldstQueue.switchOut();
380 fuPool->switchOut();
381
382 for (int i = 0; i < numThreads; i++) {
383 while (!insts[i].empty())
384 insts[i].pop();
385 while (!skidBuffer[i].empty())
386 skidBuffer[i].pop();
387 }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394 // Reset all state.
395 _status = Active;
396 exeStatus = Running;
397 wbStatus = Idle;
398 switchedOut = false;
399
400 instQueue.takeOverFrom();
401 ldstQueue.takeOverFrom();
402 fuPool->takeOverFrom();
403
404 initStage();
405 cpu->activityThisCycle();
406
407 for (int i=0; i < numThreads; i++) {
408 dispatchStatus[i] = Running;
409 stalls[i].commit = false;
410 fetchRedirect[i] = false;
411 }
412
413 updateLSQNextCycle = false;
414
415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416 issueToExecQueue.advance();
417 }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436 updatedQueues = true;
437
438 // Clear the skid buffer in case it has any data in it.
439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442 while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444 if (skidBuffer[tid].front()->seqNum <=
445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447 "that occur before delay slot [sn:%i].\n",
448 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449 tid);
450 break;
451 } else {
452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454 }
455#endif
456 if (skidBuffer[tid].front()->isLoad() ||
457 skidBuffer[tid].front()->isStore() ) {
458 toRename->iewInfo[tid].dispatchedToLSQ++;
459 }
460
461 toRename->iewInfo[tid].dispatched++;
462
463 skidBuffer[tid].pop();
464 }
465
466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468 emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43 : issueToExecQueue(params->backComSize, params->forwardComSize),
44 instQueue(params),
45 ldstQueue(params),
46 fuPool(params->fuPool),
47 commitToIEWDelay(params->commitToIEWDelay),
48 renameToIEWDelay(params->renameToIEWDelay),
49 issueToExecuteDelay(params->issueToExecuteDelay),
50 dispatchWidth(params->dispatchWidth),
51 issueWidth(params->issueWidth),
52 wbOutstanding(0),
53 wbWidth(params->wbWidth),
54 numThreads(params->numberOfThreads),
55 switchedOut(false)
56{
57 _status = Active;
58 exeStatus = Running;
59 wbStatus = Idle;
60
61 // Setup wire to read instructions coming from issue.
62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64 // Instruction queue needs the queue between issue and execute.
65 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67 instQueue.setIEW(this);
68 ldstQueue.setIEW(this);
69
70 for (int i=0; i < numThreads; i++) {
71 dispatchStatus[i] = Running;
72 stalls[i].commit = false;
73 fetchRedirect[i] = false;
74 bdelayDoneSeqNum[i] = 0;
75 }
76
77 wbMax = wbWidth * params->wbDepth;
78
79 updateLSQNextCycle = false;
80
81 ableToIssue = true;
82
83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90 return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97 using namespace Stats;
98
99 instQueue.regStats();
100 ldstQueue.regStats();
101
102 iewIdleCycles
103 .name(name() + ".iewIdleCycles")
104 .desc("Number of cycles IEW is idle");
105
106 iewSquashCycles
107 .name(name() + ".iewSquashCycles")
108 .desc("Number of cycles IEW is squashing");
109
110 iewBlockCycles
111 .name(name() + ".iewBlockCycles")
112 .desc("Number of cycles IEW is blocking");
113
114 iewUnblockCycles
115 .name(name() + ".iewUnblockCycles")
116 .desc("Number of cycles IEW is unblocking");
117
118 iewDispatchedInsts
119 .name(name() + ".iewDispatchedInsts")
120 .desc("Number of instructions dispatched to IQ");
121
122 iewDispSquashedInsts
123 .name(name() + ".iewDispSquashedInsts")
124 .desc("Number of squashed instructions skipped by dispatch");
125
126 iewDispLoadInsts
127 .name(name() + ".iewDispLoadInsts")
128 .desc("Number of dispatched load instructions");
129
130 iewDispStoreInsts
131 .name(name() + ".iewDispStoreInsts")
132 .desc("Number of dispatched store instructions");
133
134 iewDispNonSpecInsts
135 .name(name() + ".iewDispNonSpecInsts")
136 .desc("Number of dispatched non-speculative instructions");
137
138 iewIQFullEvents
139 .name(name() + ".iewIQFullEvents")
140 .desc("Number of times the IQ has become full, causing a stall");
141
142 iewLSQFullEvents
143 .name(name() + ".iewLSQFullEvents")
144 .desc("Number of times the LSQ has become full, causing a stall");
145
146 memOrderViolationEvents
147 .name(name() + ".memOrderViolationEvents")
148 .desc("Number of memory order violations");
149
150 predictedTakenIncorrect
151 .name(name() + ".predictedTakenIncorrect")
152 .desc("Number of branches that were predicted taken incorrectly");
153
154 predictedNotTakenIncorrect
155 .name(name() + ".predictedNotTakenIncorrect")
156 .desc("Number of branches that were predicted not taken incorrectly");
157
158 branchMispredicts
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
161
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164 iewExecutedInsts
165 .name(name() + ".iewExecutedInsts")
166 .desc("Number of executed instructions");
167
168 iewExecLoadInsts
169 .init(cpu->number_of_threads)
170 .name(name() + ".iewExecLoadInsts")
171 .desc("Number of load instructions executed")
172 .flags(total);
173
174 iewExecSquashedInsts
175 .name(name() + ".iewExecSquashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
177
178 iewExecutedSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
182 .flags(total);
183
184 iewExecutedNop
185 .init(cpu->number_of_threads)
186 .name(name() + ".EXEC:nop")
187 .desc("number of nop insts executed")
188 .flags(total);
189
190 iewExecutedRefs
191 .init(cpu->number_of_threads)
192 .name(name() + ".EXEC:refs")
193 .desc("number of memory reference insts executed")
194 .flags(total);
195
196 iewExecutedBranches
197 .init(cpu->number_of_threads)
198 .name(name() + ".EXEC:branches")
199 .desc("Number of branches executed")
200 .flags(total);
201
202 iewExecStoreInsts
203 .name(name() + ".EXEC:stores")
204 .desc("Number of stores executed")
205 .flags(total);
206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208 iewExecRate
209 .name(name() + ".EXEC:rate")
210 .desc("Inst execution rate")
211 .flags(total);
212
213 iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215 iewInstsToCommit
216 .init(cpu->number_of_threads)
217 .name(name() + ".WB:sent")
218 .desc("cumulative count of insts sent to commit")
219 .flags(total);
220
221 writebackCount
222 .init(cpu->number_of_threads)
223 .name(name() + ".WB:count")
224 .desc("cumulative count of insts written-back")
225 .flags(total);
226
227 producerInst
228 .init(cpu->number_of_threads)
229 .name(name() + ".WB:producers")
230 .desc("num instructions producing a value")
231 .flags(total);
232
233 consumerInst
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:consumers")
236 .desc("num instructions consuming a value")
237 .flags(total);
238
239 wbPenalized
240 .init(cpu->number_of_threads)
241 .name(name() + ".WB:penalized")
242 .desc("number of instrctions required to write to 'other' IQ")
243 .flags(total);
244
245 wbPenalizedRate
246 .name(name() + ".WB:penalized_rate")
247 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248 .flags(total);
249
250 wbPenalizedRate = wbPenalized / writebackCount;
251
252 wbFanout
253 .name(name() + ".WB:fanout")
254 .desc("average fanout of values written-back")
255 .flags(total);
256
257 wbFanout = producerInst / consumerInst;
258
259 wbRate
260 .name(name() + ".WB:rate")
261 .desc("insts written-back per cycle")
262 .flags(total);
263 wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270 for (int tid=0; tid < numThreads; tid++) {
271 toRename->iewInfo[tid].usedIQ = true;
272 toRename->iewInfo[tid].freeIQEntries =
273 instQueue.numFreeEntries(tid);
274
275 toRename->iewInfo[tid].usedLSQ = true;
276 toRename->iewInfo[tid].freeLSQEntries =
277 ldstQueue.numFreeEntries(tid);
278 }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285 DPRINTF(IEW, "Setting CPU pointer.\n");
286 cpu = cpu_ptr;
287
288 instQueue.setCPU(cpu_ptr);
289 ldstQueue.setCPU(cpu_ptr);
290
291 cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298 DPRINTF(IEW, "Setting time buffer pointer.\n");
299 timeBuffer = tb_ptr;
300
301 // Setup wire to read information from time buffer, from commit.
302 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304 // Setup wire to write information back to previous stages.
305 toRename = timeBuffer->getWire(0);
306
307 toFetch = timeBuffer->getWire(0);
308
309 // Instruction queue also needs main time buffer.
310 instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317 DPRINTF(IEW, "Setting rename queue pointer.\n");
318 renameQueue = rq_ptr;
319
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 DPRINTF(IEW, "Setting IEW queue pointer.\n");
329 iewQueue = iq_ptr;
330
331 // Setup wire to write instructions to commit.
332 toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339 DPRINTF(IEW, "Setting active threads list pointer.\n");
340 activeThreads = at_ptr;
341
342 ldstQueue.setActiveThreads(at_ptr);
343 instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350 DPRINTF(IEW, "Setting scoreboard pointer.\n");
351 scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358 // IEW is ready to drain at any time.
359 cpu->signalDrained();
360 return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373 // Clear any state.
374 switchedOut = true;
375 assert(insts[0].empty());
376 assert(skidBuffer[0].empty());
377
378 instQueue.switchOut();
379 ldstQueue.switchOut();
380 fuPool->switchOut();
381
382 for (int i = 0; i < numThreads; i++) {
383 while (!insts[i].empty())
384 insts[i].pop();
385 while (!skidBuffer[i].empty())
386 skidBuffer[i].pop();
387 }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394 // Reset all state.
395 _status = Active;
396 exeStatus = Running;
397 wbStatus = Idle;
398 switchedOut = false;
399
400 instQueue.takeOverFrom();
401 ldstQueue.takeOverFrom();
402 fuPool->takeOverFrom();
403
404 initStage();
405 cpu->activityThisCycle();
406
407 for (int i=0; i < numThreads; i++) {
408 dispatchStatus[i] = Running;
409 stalls[i].commit = false;
410 fetchRedirect[i] = false;
411 }
412
413 updateLSQNextCycle = false;
414
415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416 issueToExecQueue.advance();
417 }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436 updatedQueues = true;
437
438 // Clear the skid buffer in case it has any data in it.
439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442 while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444 if (skidBuffer[tid].front()->seqNum <=
445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447 "that occur before delay slot [sn:%i].\n",
448 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449 tid);
450 break;
451 } else {
452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454 }
455#endif
456 if (skidBuffer[tid].front()->isLoad() ||
457 skidBuffer[tid].front()->isStore() ) {
458 toRename->iewInfo[tid].dispatchedToLSQ++;
459 }
460
461 toRename->iewInfo[tid].dispatched++;
462
463 skidBuffer[tid].pop();
464 }
465
466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468 emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
|
484 bool branch_taken = inst->readNextNPC() !=
485 (inst->readNextPC() + sizeof(TheISA::MachInst));
| 484 bool branch_taken =
485 (inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) &&
486 inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst)));
487 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
488 branch_taken ? "true": "false", inst->seqNum);
|
486
487 toCommit->branchTaken[tid] = branch_taken;
488
| 489
490 toCommit->branchTaken[tid] = branch_taken;
491
|
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491 if (inst->isCondDelaySlot() && branch_taken) {
| 492 bool squashDelaySlot =
493 (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
494 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
495 squashDelaySlot ? "true": "false", inst->seqNum);
496 toCommit->squashDelaySlot[tid] = squashDelaySlot;
497 //If we're squashing the delay slot, we need to pick back up at NextPC.
498 //Otherwise, NextPC isn't being squashed, so we should pick back up at
499 //NextNPC.
500 if (squashDelaySlot)
|
492 toCommit->nextPC[tid] = inst->readNextPC();
| 501 toCommit->nextPC[tid] = inst->readNextPC();
|
493 } else {
| 502 else
|
494 toCommit->nextPC[tid] = inst->readNextNPC();
| 503 toCommit->nextPC[tid] = inst->readNextNPC();
|
495 }
| |
496#else
497 toCommit->branchTaken[tid] = inst->readNextPC() !=
498 (inst->readPC() + sizeof(TheISA::MachInst));
499 toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502 toCommit->includeSquashInst[tid] = false;
503
504 wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
| 504#else
505 toCommit->branchTaken[tid] = inst->readNextPC() !=
506 (inst->readPC() + sizeof(TheISA::MachInst));
507 toCommit->nextPC[tid] = inst->readNextPC();
508#endif
509
510 toCommit->includeSquashInst[tid] = false;
511
512 wroteToTimeBuffer = true;
513}
514
515template<class Impl>
516void
517DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
518{
519 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
520 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
521
522 toCommit->squash[tid] = true;
523 toCommit->squashedSeqNum[tid] = inst->seqNum;
524 toCommit->nextPC[tid] = inst->readNextPC();
|
517 toCommit->branchMispredict[tid] = false;
| |
518
519 toCommit->includeSquashInst[tid] = false;
520
521 wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531 toCommit->squash[tid] = true;
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->nextPC[tid] = inst->readPC();
| 525
526 toCommit->includeSquashInst[tid] = false;
527
528 wroteToTimeBuffer = true;
529}
530
531template<class Impl>
532void
533DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
534{
535 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
536 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
537
538 toCommit->squash[tid] = true;
539 toCommit->squashedSeqNum[tid] = inst->seqNum;
540 toCommit->nextPC[tid] = inst->readPC();
|
534 toCommit->branchMispredict[tid] = false;
| |
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;
542}
543
544template<class Impl>
545void
546DefaultIEW<Impl>::block(unsigned tid)
547{
548 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
549
550 if (dispatchStatus[tid] != Blocked &&
551 dispatchStatus[tid] != Unblocking) {
552 toRename->iewBlock[tid] = true;
553 wroteToTimeBuffer = true;
554 }
555
556 // Add the current inputs to the skid buffer so they can be
557 // reprocessed when this stage unblocks.
558 skidInsert(tid);
559
560 dispatchStatus[tid] = Blocked;
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::unblock(unsigned tid)
566{
567 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
568 "buffer %u.\n",tid, tid);
569
570 // If the skid bufffer is empty, signal back to previous stages to unblock.
571 // Also switch status to running.
572 if (skidBuffer[tid].empty()) {
573 toRename->iewUnblock[tid] = true;
574 wroteToTimeBuffer = true;
575 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
576 dispatchStatus[tid] = Running;
577 }
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
583{
584 instQueue.wakeDependents(inst);
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
590{
591 instQueue.rescheduleMemInst(inst);
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
597{
598 instQueue.replayMemInst(inst);
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604{
605 // This function should not be called after writebackInsts in a
606 // single cycle. That will cause problems with an instruction
607 // being added to the queue to commit without being processed by
608 // writebackInsts prior to being sent to commit.
609
610 // First check the time slot that this instruction will write
611 // to. If there are free write ports at the time, then go ahead
612 // and write the instruction to that time. If there are not,
613 // keep looking back to see where's the first time there's a
614 // free slot.
615 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
616 ++wbNumInst;
617 if (wbNumInst == wbWidth) {
618 ++wbCycle;
619 wbNumInst = 0;
620 }
621
622 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
623 }
624
625 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
626 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
627 // Add finished instruction to queue to commit.
628 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
629 (*iewQueue)[wbCycle].size++;
630}
631
632template <class Impl>
633unsigned
634DefaultIEW<Impl>::validInstsFromRename()
635{
636 unsigned inst_count = 0;
637
638 for (int i=0; i<fromRename->size; i++) {
639 if (!fromRename->insts[i]->isSquashed())
640 inst_count++;
641 }
642
643 return inst_count;
644}
645
646template<class Impl>
647void
648DefaultIEW<Impl>::skidInsert(unsigned tid)
649{
650 DynInstPtr inst = NULL;
651
652 while (!insts[tid].empty()) {
653 inst = insts[tid].front();
654
655 insts[tid].pop();
656
657 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
658 "dispatch skidBuffer %i\n",tid, inst->seqNum,
659 inst->readPC(),tid);
660
661 skidBuffer[tid].push(inst);
662 }
663
664 assert(skidBuffer[tid].size() <= skidBufferMax &&
665 "Skidbuffer Exceeded Max Size");
666}
667
668template<class Impl>
669int
670DefaultIEW<Impl>::skidCount()
671{
672 int max=0;
673
674 std::list<unsigned>::iterator threads = (*activeThreads).begin();
675
676 while (threads != (*activeThreads).end()) {
677 unsigned thread_count = skidBuffer[*threads++].size();
678 if (max < thread_count)
679 max = thread_count;
680 }
681
682 return max;
683}
684
685template<class Impl>
686bool
687DefaultIEW<Impl>::skidsEmpty()
688{
689 std::list<unsigned>::iterator threads = (*activeThreads).begin();
690
691 while (threads != (*activeThreads).end()) {
692 if (!skidBuffer[*threads++].empty())
693 return false;
694 }
695
696 return true;
697}
698
699template <class Impl>
700void
701DefaultIEW<Impl>::updateStatus()
702{
703 bool any_unblocking = false;
704
705 std::list<unsigned>::iterator threads = (*activeThreads).begin();
706
707 threads = (*activeThreads).begin();
708
709 while (threads != (*activeThreads).end()) {
710 unsigned tid = *threads++;
711
712 if (dispatchStatus[tid] == Unblocking) {
713 any_unblocking = true;
714 break;
715 }
716 }
717
718 // If there are no ready instructions waiting to be scheduled by the IQ,
719 // and there's no stores waiting to write back, and dispatch is not
720 // unblocking, then there is no internal activity for the IEW stage.
721 if (_status == Active && !instQueue.hasReadyInsts() &&
722 !ldstQueue.willWB() && !any_unblocking) {
723 DPRINTF(IEW, "IEW switching to idle\n");
724
725 deactivateStage();
726
727 _status = Inactive;
728 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
729 ldstQueue.willWB() ||
730 any_unblocking)) {
731 // Otherwise there is internal activity. Set to active.
732 DPRINTF(IEW, "IEW switching to active\n");
733
734 activateStage();
735
736 _status = Active;
737 }
738}
739
740template <class Impl>
741void
742DefaultIEW<Impl>::resetEntries()
743{
744 instQueue.resetEntries();
745 ldstQueue.resetEntries();
746}
747
748template <class Impl>
749void
750DefaultIEW<Impl>::readStallSignals(unsigned tid)
751{
752 if (fromCommit->commitBlock[tid]) {
753 stalls[tid].commit = true;
754 }
755
756 if (fromCommit->commitUnblock[tid]) {
757 assert(stalls[tid].commit);
758 stalls[tid].commit = false;
759 }
760}
761
762template <class Impl>
763bool
764DefaultIEW<Impl>::checkStall(unsigned tid)
765{
766 bool ret_val(false);
767
768 if (stalls[tid].commit) {
769 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
770 ret_val = true;
771 } else if (instQueue.isFull(tid)) {
772 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
773 ret_val = true;
774 } else if (ldstQueue.isFull(tid)) {
775 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
776
777 if (ldstQueue.numLoads(tid) > 0 ) {
778
779 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
780 tid,ldstQueue.getLoadHeadSeqNum(tid));
781 }
782
783 if (ldstQueue.numStores(tid) > 0) {
784
785 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
786 tid,ldstQueue.getStoreHeadSeqNum(tid));
787 }
788
789 ret_val = true;
790 } else if (ldstQueue.isStalled(tid)) {
791 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
792 ret_val = true;
793 }
794
795 return ret_val;
796}
797
798template <class Impl>
799void
800DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
801{
802 // Check if there's a squash signal, squash if there is
803 // Check stall signals, block if there is.
804 // If status was Blocked
805 // if so then go to unblocking
806 // If status was Squashing
807 // check if squashing is not high. Switch to running this cycle.
808
809 readStallSignals(tid);
810
811 if (fromCommit->commitInfo[tid].squash) {
812 squash(tid);
813
814 if (dispatchStatus[tid] == Blocked ||
815 dispatchStatus[tid] == Unblocking) {
816 toRename->iewUnblock[tid] = true;
817 wroteToTimeBuffer = true;
818 }
819
820 dispatchStatus[tid] = Squashing;
821
822 fetchRedirect[tid] = false;
823 return;
824 }
825
826 if (fromCommit->commitInfo[tid].robSquashing) {
827 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
828
829 dispatchStatus[tid] = Squashing;
830
831 emptyRenameInsts(tid);
832 wroteToTimeBuffer = true;
833 return;
834 }
835
836 if (checkStall(tid)) {
837 block(tid);
838 dispatchStatus[tid] = Blocked;
839 return;
840 }
841
842 if (dispatchStatus[tid] == Blocked) {
843 // Status from previous cycle was blocked, but there are no more stall
844 // conditions. Switch over to unblocking.
845 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
846 tid);
847
848 dispatchStatus[tid] = Unblocking;
849
850 unblock(tid);
851
852 return;
853 }
854
855 if (dispatchStatus[tid] == Squashing) {
856 // Switch status to running if rename isn't being told to block or
857 // squash this cycle.
858 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
859 tid);
860
861 dispatchStatus[tid] = Running;
862
863 return;
864 }
865}
866
867template <class Impl>
868void
869DefaultIEW<Impl>::sortInsts()
870{
871 int insts_from_rename = fromRename->size;
872#ifdef DEBUG
873#if !ISA_HAS_DELAY_SLOT
874 for (int i = 0; i < numThreads; i++)
875 assert(insts[i].empty());
876#endif
877#endif
878 for (int i = 0; i < insts_from_rename; ++i) {
879 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
880 }
881}
882
883template <class Impl>
884void
885DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
886{
887 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
888 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
889
890 while (!insts[tid].empty()) {
891#if ISA_HAS_DELAY_SLOT
892 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
893 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
894 " that occurs at or before delay slot [sn:%i].\n",
895 tid, bdelayDoneSeqNum[tid]);
896 break;
897 } else {
898 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
899 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
900 }
901#endif
902
903 if (insts[tid].front()->isLoad() ||
904 insts[tid].front()->isStore() ) {
905 toRename->iewInfo[tid].dispatchedToLSQ++;
906 }
907
908 toRename->iewInfo[tid].dispatched++;
909
910 insts[tid].pop();
911 }
912}
913
914template <class Impl>
915void
916DefaultIEW<Impl>::wakeCPU()
917{
918 cpu->wakeCPU();
919}
920
921template <class Impl>
922void
923DefaultIEW<Impl>::activityThisCycle()
924{
925 DPRINTF(Activity, "Activity this cycle.\n");
926 cpu->activityThisCycle();
927}
928
929template <class Impl>
930inline void
931DefaultIEW<Impl>::activateStage()
932{
933 DPRINTF(Activity, "Activating stage.\n");
934 cpu->activateStage(O3CPU::IEWIdx);
935}
936
937template <class Impl>
938inline void
939DefaultIEW<Impl>::deactivateStage()
940{
941 DPRINTF(Activity, "Deactivating stage.\n");
942 cpu->deactivateStage(O3CPU::IEWIdx);
943}
944
945template<class Impl>
946void
947DefaultIEW<Impl>::dispatch(unsigned tid)
948{
949 // If status is Running or idle,
950 // call dispatchInsts()
951 // If status is Unblocking,
952 // buffer any instructions coming from rename
953 // continue trying to empty skid buffer
954 // check if stall conditions have passed
955
956 if (dispatchStatus[tid] == Blocked) {
957 ++iewBlockCycles;
958
959 } else if (dispatchStatus[tid] == Squashing) {
960 ++iewSquashCycles;
961 }
962
963 // Dispatch should try to dispatch as many instructions as its bandwidth
964 // will allow, as long as it is not currently blocked.
965 if (dispatchStatus[tid] == Running ||
966 dispatchStatus[tid] == Idle) {
967 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
968 "dispatch.\n", tid);
969
970 dispatchInsts(tid);
971 } else if (dispatchStatus[tid] == Unblocking) {
972 // Make sure that the skid buffer has something in it if the
973 // status is unblocking.
974 assert(!skidsEmpty());
975
976 // If the status was unblocking, then instructions from the skid
977 // buffer were used. Remove those instructions and handle
978 // the rest of unblocking.
979 dispatchInsts(tid);
980
981 ++iewUnblockCycles;
982
983 if (validInstsFromRename() && dispatchedAllInsts) {
984 // Add the current inputs to the skid buffer so they can be
985 // reprocessed when this stage unblocks.
986 skidInsert(tid);
987 }
988
989 unblock(tid);
990 }
991}
992
993template <class Impl>
994void
995DefaultIEW<Impl>::dispatchInsts(unsigned tid)
996{
997 dispatchedAllInsts = true;
998
999 // Obtain instructions from skid buffer if unblocking, or queue from rename
1000 // otherwise.
1001 std::queue<DynInstPtr> &insts_to_dispatch =
1002 dispatchStatus[tid] == Unblocking ?
1003 skidBuffer[tid] : insts[tid];
1004
1005 int insts_to_add = insts_to_dispatch.size();
1006
1007 DynInstPtr inst;
1008 bool add_to_iq = false;
1009 int dis_num_inst = 0;
1010
1011 // Loop through the instructions, putting them in the instruction
1012 // queue.
1013 for ( ; dis_num_inst < insts_to_add &&
1014 dis_num_inst < dispatchWidth;
1015 ++dis_num_inst)
1016 {
1017 inst = insts_to_dispatch.front();
1018
1019 if (dispatchStatus[tid] == Unblocking) {
1020 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1021 "buffer\n", tid);
1022 }
1023
1024 // Make sure there's a valid instruction there.
1025 assert(inst);
1026
1027 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1028 "IQ.\n",
1029 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1030
1031 // Be sure to mark these instructions as ready so that the
1032 // commit stage can go ahead and execute them, and mark
1033 // them as issued so the IQ doesn't reprocess them.
1034
1035 // Check for squashed instructions.
1036 if (inst->isSquashed()) {
1037 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1038 "not adding to IQ.\n", tid);
1039
1040 ++iewDispSquashedInsts;
1041
1042 insts_to_dispatch.pop();
1043
1044 //Tell Rename That An Instruction has been processed
1045 if (inst->isLoad() || inst->isStore()) {
1046 toRename->iewInfo[tid].dispatchedToLSQ++;
1047 }
1048 toRename->iewInfo[tid].dispatched++;
1049
1050 continue;
1051 }
1052
1053 // Check for full conditions.
1054 if (instQueue.isFull(tid)) {
1055 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1056
1057 // Call function to start blocking.
1058 block(tid);
1059
1060 // Set unblock to false. Special case where we are using
1061 // skidbuffer (unblocking) instructions but then we still
1062 // get full in the IQ.
1063 toRename->iewUnblock[tid] = false;
1064
1065 dispatchedAllInsts = false;
1066
1067 ++iewIQFullEvents;
1068 break;
1069 } else if (ldstQueue.isFull(tid)) {
1070 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1071
1072 // Call function to start blocking.
1073 block(tid);
1074
1075 // Set unblock to false. Special case where we are using
1076 // skidbuffer (unblocking) instructions but then we still
1077 // get full in the IQ.
1078 toRename->iewUnblock[tid] = false;
1079
1080 dispatchedAllInsts = false;
1081
1082 ++iewLSQFullEvents;
1083 break;
1084 }
1085
1086 // Otherwise issue the instruction just fine.
1087 if (inst->isLoad()) {
1088 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1089 "encountered, adding to LSQ.\n", tid);
1090
1091 // Reserve a spot in the load store queue for this
1092 // memory access.
1093 ldstQueue.insertLoad(inst);
1094
1095 ++iewDispLoadInsts;
1096
1097 add_to_iq = true;
1098
1099 toRename->iewInfo[tid].dispatchedToLSQ++;
1100 } else if (inst->isStore()) {
1101 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1102 "encountered, adding to LSQ.\n", tid);
1103
1104 ldstQueue.insertStore(inst);
1105
1106 ++iewDispStoreInsts;
1107
1108 if (inst->isStoreConditional()) {
1109 // Store conditionals need to be set as "canCommit()"
1110 // so that commit can process them when they reach the
1111 // head of commit.
1112 // @todo: This is somewhat specific to Alpha.
1113 inst->setCanCommit();
1114 instQueue.insertNonSpec(inst);
1115 add_to_iq = false;
1116
1117 ++iewDispNonSpecInsts;
1118 } else {
1119 add_to_iq = true;
1120 }
1121
1122 toRename->iewInfo[tid].dispatchedToLSQ++;
1123#if FULL_SYSTEM
1124 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1125 // Same as non-speculative stores.
1126 inst->setCanCommit();
1127 instQueue.insertBarrier(inst);
1128 add_to_iq = false;
1129#endif
1130 } else if (inst->isNonSpeculative()) {
1131 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1132 "encountered, skipping.\n", tid);
1133
1134 // Same as non-speculative stores.
1135 inst->setCanCommit();
1136
1137 // Specifically insert it as nonspeculative.
1138 instQueue.insertNonSpec(inst);
1139
1140 ++iewDispNonSpecInsts;
1141
1142 add_to_iq = false;
1143 } else if (inst->isNop()) {
1144 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1145 "skipping.\n", tid);
1146
1147 inst->setIssued();
1148 inst->setExecuted();
1149 inst->setCanCommit();
1150
1151 instQueue.recordProducer(inst);
1152
1153 iewExecutedNop[tid]++;
1154
1155 add_to_iq = false;
1156 } else if (inst->isExecuted()) {
1157 assert(0 && "Instruction shouldn't be executed.\n");
1158 DPRINTF(IEW, "Issue: Executed branch encountered, "
1159 "skipping.\n");
1160
1161 inst->setIssued();
1162 inst->setCanCommit();
1163
1164 instQueue.recordProducer(inst);
1165
1166 add_to_iq = false;
1167 } else {
1168 add_to_iq = true;
1169 }
1170
1171 // If the instruction queue is not full, then add the
1172 // instruction.
1173 if (add_to_iq) {
1174 instQueue.insert(inst);
1175 }
1176
1177 insts_to_dispatch.pop();
1178
1179 toRename->iewInfo[tid].dispatched++;
1180
1181 ++iewDispatchedInsts;
1182 }
1183
1184 if (!insts_to_dispatch.empty()) {
1185 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1186 block(tid);
1187 toRename->iewUnblock[tid] = false;
1188 }
1189
1190 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1191 dispatchStatus[tid] = Running;
1192
1193 updatedQueues = true;
1194 }
1195
1196 dis_num_inst = 0;
1197}
1198
1199template <class Impl>
1200void
1201DefaultIEW<Impl>::printAvailableInsts()
1202{
1203 int inst = 0;
1204
1205 std::cout << "Available Instructions: ";
1206
1207 while (fromIssue->insts[inst]) {
1208
1209 if (inst%3==0) std::cout << "\n\t";
1210
1211 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1212 << " TN: " << fromIssue->insts[inst]->threadNumber
1213 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1214
1215 inst++;
1216
1217 }
1218
1219 std::cout << "\n";
1220}
1221
1222template <class Impl>
1223void
1224DefaultIEW<Impl>::executeInsts()
1225{
1226 wbNumInst = 0;
1227 wbCycle = 0;
1228
1229 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1230
1231 while (threads != (*activeThreads).end()) {
1232 unsigned tid = *threads++;
1233 fetchRedirect[tid] = false;
1234 }
1235
1236 // Uncomment this if you want to see all available instructions.
1237// printAvailableInsts();
1238
1239 // Execute/writeback any instructions that are available.
1240 int insts_to_execute = fromIssue->size;
1241 int inst_num = 0;
1242 for (; inst_num < insts_to_execute;
1243 ++inst_num) {
1244
1245 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1246
1247 DynInstPtr inst = instQueue.getInstToExecute();
1248
1249 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1250 inst->readPC(), inst->threadNumber,inst->seqNum);
1251
1252 // Check if the instruction is squashed; if so then skip it
1253 if (inst->isSquashed()) {
1254 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1255
1256 // Consider this instruction executed so that commit can go
1257 // ahead and retire the instruction.
1258 inst->setExecuted();
1259
1260 // Not sure if I should set this here or just let commit try to
1261 // commit any squashed instructions. I like the latter a bit more.
1262 inst->setCanCommit();
1263
1264 ++iewExecSquashedInsts;
1265
1266 decrWb(inst->seqNum);
1267 continue;
1268 }
1269
1270 Fault fault = NoFault;
1271
1272 // Execute instruction.
1273 // Note that if the instruction faults, it will be handled
1274 // at the commit stage.
1275 if (inst->isMemRef() &&
1276 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1277 DPRINTF(IEW, "Execute: Calculating address for memory "
1278 "reference.\n");
1279
1280 // Tell the LDSTQ to execute this instruction (if it is a load).
1281 if (inst->isLoad()) {
1282 // Loads will mark themselves as executed, and their writeback
1283 // event adds the instruction to the queue to commit
1284 fault = ldstQueue.executeLoad(inst);
1285 } else if (inst->isStore()) {
1286 fault = ldstQueue.executeStore(inst);
1287
1288 // If the store had a fault then it may not have a mem req
1289 if (!inst->isStoreConditional() && fault == NoFault) {
1290 inst->setExecuted();
1291
1292 instToCommit(inst);
1293 } else if (fault != NoFault) {
1294 // If the instruction faulted, then we need to send it along to commit
1295 // without the instruction completing.
| 541
542 // Must include the broadcasted SN in the squash.
543 toCommit->includeSquashInst[tid] = true;
544
545 ldstQueue.setLoadBlockedHandled(tid);
546
547 wroteToTimeBuffer = true;
548}
549
550template<class Impl>
551void
552DefaultIEW<Impl>::block(unsigned tid)
553{
554 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
555
556 if (dispatchStatus[tid] != Blocked &&
557 dispatchStatus[tid] != Unblocking) {
558 toRename->iewBlock[tid] = true;
559 wroteToTimeBuffer = true;
560 }
561
562 // Add the current inputs to the skid buffer so they can be
563 // reprocessed when this stage unblocks.
564 skidInsert(tid);
565
566 dispatchStatus[tid] = Blocked;
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::unblock(unsigned tid)
572{
573 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
574 "buffer %u.\n",tid, tid);
575
576 // If the skid bufffer is empty, signal back to previous stages to unblock.
577 // Also switch status to running.
578 if (skidBuffer[tid].empty()) {
579 toRename->iewUnblock[tid] = true;
580 wroteToTimeBuffer = true;
581 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
582 dispatchStatus[tid] = Running;
583 }
584}
585
586template<class Impl>
587void
588DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
589{
590 instQueue.wakeDependents(inst);
591}
592
593template<class Impl>
594void
595DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
596{
597 instQueue.rescheduleMemInst(inst);
598}
599
600template<class Impl>
601void
602DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
603{
604 instQueue.replayMemInst(inst);
605}
606
607template<class Impl>
608void
609DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
610{
611 // This function should not be called after writebackInsts in a
612 // single cycle. That will cause problems with an instruction
613 // being added to the queue to commit without being processed by
614 // writebackInsts prior to being sent to commit.
615
616 // First check the time slot that this instruction will write
617 // to. If there are free write ports at the time, then go ahead
618 // and write the instruction to that time. If there are not,
619 // keep looking back to see where's the first time there's a
620 // free slot.
621 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
622 ++wbNumInst;
623 if (wbNumInst == wbWidth) {
624 ++wbCycle;
625 wbNumInst = 0;
626 }
627
628 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
629 }
630
631 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
632 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
633 // Add finished instruction to queue to commit.
634 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
635 (*iewQueue)[wbCycle].size++;
636}
637
638template <class Impl>
639unsigned
640DefaultIEW<Impl>::validInstsFromRename()
641{
642 unsigned inst_count = 0;
643
644 for (int i=0; i<fromRename->size; i++) {
645 if (!fromRename->insts[i]->isSquashed())
646 inst_count++;
647 }
648
649 return inst_count;
650}
651
652template<class Impl>
653void
654DefaultIEW<Impl>::skidInsert(unsigned tid)
655{
656 DynInstPtr inst = NULL;
657
658 while (!insts[tid].empty()) {
659 inst = insts[tid].front();
660
661 insts[tid].pop();
662
663 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
664 "dispatch skidBuffer %i\n",tid, inst->seqNum,
665 inst->readPC(),tid);
666
667 skidBuffer[tid].push(inst);
668 }
669
670 assert(skidBuffer[tid].size() <= skidBufferMax &&
671 "Skidbuffer Exceeded Max Size");
672}
673
674template<class Impl>
675int
676DefaultIEW<Impl>::skidCount()
677{
678 int max=0;
679
680 std::list<unsigned>::iterator threads = (*activeThreads).begin();
681
682 while (threads != (*activeThreads).end()) {
683 unsigned thread_count = skidBuffer[*threads++].size();
684 if (max < thread_count)
685 max = thread_count;
686 }
687
688 return max;
689}
690
691template<class Impl>
692bool
693DefaultIEW<Impl>::skidsEmpty()
694{
695 std::list<unsigned>::iterator threads = (*activeThreads).begin();
696
697 while (threads != (*activeThreads).end()) {
698 if (!skidBuffer[*threads++].empty())
699 return false;
700 }
701
702 return true;
703}
704
705template <class Impl>
706void
707DefaultIEW<Impl>::updateStatus()
708{
709 bool any_unblocking = false;
710
711 std::list<unsigned>::iterator threads = (*activeThreads).begin();
712
713 threads = (*activeThreads).begin();
714
715 while (threads != (*activeThreads).end()) {
716 unsigned tid = *threads++;
717
718 if (dispatchStatus[tid] == Unblocking) {
719 any_unblocking = true;
720 break;
721 }
722 }
723
724 // If there are no ready instructions waiting to be scheduled by the IQ,
725 // and there's no stores waiting to write back, and dispatch is not
726 // unblocking, then there is no internal activity for the IEW stage.
727 if (_status == Active && !instQueue.hasReadyInsts() &&
728 !ldstQueue.willWB() && !any_unblocking) {
729 DPRINTF(IEW, "IEW switching to idle\n");
730
731 deactivateStage();
732
733 _status = Inactive;
734 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
735 ldstQueue.willWB() ||
736 any_unblocking)) {
737 // Otherwise there is internal activity. Set to active.
738 DPRINTF(IEW, "IEW switching to active\n");
739
740 activateStage();
741
742 _status = Active;
743 }
744}
745
746template <class Impl>
747void
748DefaultIEW<Impl>::resetEntries()
749{
750 instQueue.resetEntries();
751 ldstQueue.resetEntries();
752}
753
754template <class Impl>
755void
756DefaultIEW<Impl>::readStallSignals(unsigned tid)
757{
758 if (fromCommit->commitBlock[tid]) {
759 stalls[tid].commit = true;
760 }
761
762 if (fromCommit->commitUnblock[tid]) {
763 assert(stalls[tid].commit);
764 stalls[tid].commit = false;
765 }
766}
767
768template <class Impl>
769bool
770DefaultIEW<Impl>::checkStall(unsigned tid)
771{
772 bool ret_val(false);
773
774 if (stalls[tid].commit) {
775 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
776 ret_val = true;
777 } else if (instQueue.isFull(tid)) {
778 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
779 ret_val = true;
780 } else if (ldstQueue.isFull(tid)) {
781 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
782
783 if (ldstQueue.numLoads(tid) > 0 ) {
784
785 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
786 tid,ldstQueue.getLoadHeadSeqNum(tid));
787 }
788
789 if (ldstQueue.numStores(tid) > 0) {
790
791 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
792 tid,ldstQueue.getStoreHeadSeqNum(tid));
793 }
794
795 ret_val = true;
796 } else if (ldstQueue.isStalled(tid)) {
797 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
798 ret_val = true;
799 }
800
801 return ret_val;
802}
803
804template <class Impl>
805void
806DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
807{
808 // Check if there's a squash signal, squash if there is
809 // Check stall signals, block if there is.
810 // If status was Blocked
811 // if so then go to unblocking
812 // If status was Squashing
813 // check if squashing is not high. Switch to running this cycle.
814
815 readStallSignals(tid);
816
817 if (fromCommit->commitInfo[tid].squash) {
818 squash(tid);
819
820 if (dispatchStatus[tid] == Blocked ||
821 dispatchStatus[tid] == Unblocking) {
822 toRename->iewUnblock[tid] = true;
823 wroteToTimeBuffer = true;
824 }
825
826 dispatchStatus[tid] = Squashing;
827
828 fetchRedirect[tid] = false;
829 return;
830 }
831
832 if (fromCommit->commitInfo[tid].robSquashing) {
833 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
834
835 dispatchStatus[tid] = Squashing;
836
837 emptyRenameInsts(tid);
838 wroteToTimeBuffer = true;
839 return;
840 }
841
842 if (checkStall(tid)) {
843 block(tid);
844 dispatchStatus[tid] = Blocked;
845 return;
846 }
847
848 if (dispatchStatus[tid] == Blocked) {
849 // Status from previous cycle was blocked, but there are no more stall
850 // conditions. Switch over to unblocking.
851 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
852 tid);
853
854 dispatchStatus[tid] = Unblocking;
855
856 unblock(tid);
857
858 return;
859 }
860
861 if (dispatchStatus[tid] == Squashing) {
862 // Switch status to running if rename isn't being told to block or
863 // squash this cycle.
864 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
865 tid);
866
867 dispatchStatus[tid] = Running;
868
869 return;
870 }
871}
872
873template <class Impl>
874void
875DefaultIEW<Impl>::sortInsts()
876{
877 int insts_from_rename = fromRename->size;
878#ifdef DEBUG
879#if !ISA_HAS_DELAY_SLOT
880 for (int i = 0; i < numThreads; i++)
881 assert(insts[i].empty());
882#endif
883#endif
884 for (int i = 0; i < insts_from_rename; ++i) {
885 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
886 }
887}
888
889template <class Impl>
890void
891DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
892{
893 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
894 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
895
896 while (!insts[tid].empty()) {
897#if ISA_HAS_DELAY_SLOT
898 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
899 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
900 " that occurs at or before delay slot [sn:%i].\n",
901 tid, bdelayDoneSeqNum[tid]);
902 break;
903 } else {
904 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
905 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
906 }
907#endif
908
909 if (insts[tid].front()->isLoad() ||
910 insts[tid].front()->isStore() ) {
911 toRename->iewInfo[tid].dispatchedToLSQ++;
912 }
913
914 toRename->iewInfo[tid].dispatched++;
915
916 insts[tid].pop();
917 }
918}
919
920template <class Impl>
921void
922DefaultIEW<Impl>::wakeCPU()
923{
924 cpu->wakeCPU();
925}
926
927template <class Impl>
928void
929DefaultIEW<Impl>::activityThisCycle()
930{
931 DPRINTF(Activity, "Activity this cycle.\n");
932 cpu->activityThisCycle();
933}
934
935template <class Impl>
936inline void
937DefaultIEW<Impl>::activateStage()
938{
939 DPRINTF(Activity, "Activating stage.\n");
940 cpu->activateStage(O3CPU::IEWIdx);
941}
942
943template <class Impl>
944inline void
945DefaultIEW<Impl>::deactivateStage()
946{
947 DPRINTF(Activity, "Deactivating stage.\n");
948 cpu->deactivateStage(O3CPU::IEWIdx);
949}
950
951template<class Impl>
952void
953DefaultIEW<Impl>::dispatch(unsigned tid)
954{
955 // If status is Running or idle,
956 // call dispatchInsts()
957 // If status is Unblocking,
958 // buffer any instructions coming from rename
959 // continue trying to empty skid buffer
960 // check if stall conditions have passed
961
962 if (dispatchStatus[tid] == Blocked) {
963 ++iewBlockCycles;
964
965 } else if (dispatchStatus[tid] == Squashing) {
966 ++iewSquashCycles;
967 }
968
969 // Dispatch should try to dispatch as many instructions as its bandwidth
970 // will allow, as long as it is not currently blocked.
971 if (dispatchStatus[tid] == Running ||
972 dispatchStatus[tid] == Idle) {
973 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
974 "dispatch.\n", tid);
975
976 dispatchInsts(tid);
977 } else if (dispatchStatus[tid] == Unblocking) {
978 // Make sure that the skid buffer has something in it if the
979 // status is unblocking.
980 assert(!skidsEmpty());
981
982 // If the status was unblocking, then instructions from the skid
983 // buffer were used. Remove those instructions and handle
984 // the rest of unblocking.
985 dispatchInsts(tid);
986
987 ++iewUnblockCycles;
988
989 if (validInstsFromRename() && dispatchedAllInsts) {
990 // Add the current inputs to the skid buffer so they can be
991 // reprocessed when this stage unblocks.
992 skidInsert(tid);
993 }
994
995 unblock(tid);
996 }
997}
998
999template <class Impl>
1000void
1001DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1002{
1003 dispatchedAllInsts = true;
1004
1005 // Obtain instructions from skid buffer if unblocking, or queue from rename
1006 // otherwise.
1007 std::queue<DynInstPtr> &insts_to_dispatch =
1008 dispatchStatus[tid] == Unblocking ?
1009 skidBuffer[tid] : insts[tid];
1010
1011 int insts_to_add = insts_to_dispatch.size();
1012
1013 DynInstPtr inst;
1014 bool add_to_iq = false;
1015 int dis_num_inst = 0;
1016
1017 // Loop through the instructions, putting them in the instruction
1018 // queue.
1019 for ( ; dis_num_inst < insts_to_add &&
1020 dis_num_inst < dispatchWidth;
1021 ++dis_num_inst)
1022 {
1023 inst = insts_to_dispatch.front();
1024
1025 if (dispatchStatus[tid] == Unblocking) {
1026 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1027 "buffer\n", tid);
1028 }
1029
1030 // Make sure there's a valid instruction there.
1031 assert(inst);
1032
1033 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1034 "IQ.\n",
1035 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1036
1037 // Be sure to mark these instructions as ready so that the
1038 // commit stage can go ahead and execute them, and mark
1039 // them as issued so the IQ doesn't reprocess them.
1040
1041 // Check for squashed instructions.
1042 if (inst->isSquashed()) {
1043 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1044 "not adding to IQ.\n", tid);
1045
1046 ++iewDispSquashedInsts;
1047
1048 insts_to_dispatch.pop();
1049
1050 //Tell Rename That An Instruction has been processed
1051 if (inst->isLoad() || inst->isStore()) {
1052 toRename->iewInfo[tid].dispatchedToLSQ++;
1053 }
1054 toRename->iewInfo[tid].dispatched++;
1055
1056 continue;
1057 }
1058
1059 // Check for full conditions.
1060 if (instQueue.isFull(tid)) {
1061 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1062
1063 // Call function to start blocking.
1064 block(tid);
1065
1066 // Set unblock to false. Special case where we are using
1067 // skidbuffer (unblocking) instructions but then we still
1068 // get full in the IQ.
1069 toRename->iewUnblock[tid] = false;
1070
1071 dispatchedAllInsts = false;
1072
1073 ++iewIQFullEvents;
1074 break;
1075 } else if (ldstQueue.isFull(tid)) {
1076 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1077
1078 // Call function to start blocking.
1079 block(tid);
1080
1081 // Set unblock to false. Special case where we are using
1082 // skidbuffer (unblocking) instructions but then we still
1083 // get full in the IQ.
1084 toRename->iewUnblock[tid] = false;
1085
1086 dispatchedAllInsts = false;
1087
1088 ++iewLSQFullEvents;
1089 break;
1090 }
1091
1092 // Otherwise issue the instruction just fine.
1093 if (inst->isLoad()) {
1094 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1095 "encountered, adding to LSQ.\n", tid);
1096
1097 // Reserve a spot in the load store queue for this
1098 // memory access.
1099 ldstQueue.insertLoad(inst);
1100
1101 ++iewDispLoadInsts;
1102
1103 add_to_iq = true;
1104
1105 toRename->iewInfo[tid].dispatchedToLSQ++;
1106 } else if (inst->isStore()) {
1107 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1108 "encountered, adding to LSQ.\n", tid);
1109
1110 ldstQueue.insertStore(inst);
1111
1112 ++iewDispStoreInsts;
1113
1114 if (inst->isStoreConditional()) {
1115 // Store conditionals need to be set as "canCommit()"
1116 // so that commit can process them when they reach the
1117 // head of commit.
1118 // @todo: This is somewhat specific to Alpha.
1119 inst->setCanCommit();
1120 instQueue.insertNonSpec(inst);
1121 add_to_iq = false;
1122
1123 ++iewDispNonSpecInsts;
1124 } else {
1125 add_to_iq = true;
1126 }
1127
1128 toRename->iewInfo[tid].dispatchedToLSQ++;
1129#if FULL_SYSTEM
1130 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1131 // Same as non-speculative stores.
1132 inst->setCanCommit();
1133 instQueue.insertBarrier(inst);
1134 add_to_iq = false;
1135#endif
1136 } else if (inst->isNonSpeculative()) {
1137 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1138 "encountered, skipping.\n", tid);
1139
1140 // Same as non-speculative stores.
1141 inst->setCanCommit();
1142
1143 // Specifically insert it as nonspeculative.
1144 instQueue.insertNonSpec(inst);
1145
1146 ++iewDispNonSpecInsts;
1147
1148 add_to_iq = false;
1149 } else if (inst->isNop()) {
1150 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1151 "skipping.\n", tid);
1152
1153 inst->setIssued();
1154 inst->setExecuted();
1155 inst->setCanCommit();
1156
1157 instQueue.recordProducer(inst);
1158
1159 iewExecutedNop[tid]++;
1160
1161 add_to_iq = false;
1162 } else if (inst->isExecuted()) {
1163 assert(0 && "Instruction shouldn't be executed.\n");
1164 DPRINTF(IEW, "Issue: Executed branch encountered, "
1165 "skipping.\n");
1166
1167 inst->setIssued();
1168 inst->setCanCommit();
1169
1170 instQueue.recordProducer(inst);
1171
1172 add_to_iq = false;
1173 } else {
1174 add_to_iq = true;
1175 }
1176
1177 // If the instruction queue is not full, then add the
1178 // instruction.
1179 if (add_to_iq) {
1180 instQueue.insert(inst);
1181 }
1182
1183 insts_to_dispatch.pop();
1184
1185 toRename->iewInfo[tid].dispatched++;
1186
1187 ++iewDispatchedInsts;
1188 }
1189
1190 if (!insts_to_dispatch.empty()) {
1191 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1192 block(tid);
1193 toRename->iewUnblock[tid] = false;
1194 }
1195
1196 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1197 dispatchStatus[tid] = Running;
1198
1199 updatedQueues = true;
1200 }
1201
1202 dis_num_inst = 0;
1203}
1204
1205template <class Impl>
1206void
1207DefaultIEW<Impl>::printAvailableInsts()
1208{
1209 int inst = 0;
1210
1211 std::cout << "Available Instructions: ";
1212
1213 while (fromIssue->insts[inst]) {
1214
1215 if (inst%3==0) std::cout << "\n\t";
1216
1217 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1218 << " TN: " << fromIssue->insts[inst]->threadNumber
1219 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1220
1221 inst++;
1222
1223 }
1224
1225 std::cout << "\n";
1226}
1227
1228template <class Impl>
1229void
1230DefaultIEW<Impl>::executeInsts()
1231{
1232 wbNumInst = 0;
1233 wbCycle = 0;
1234
1235 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1236
1237 while (threads != (*activeThreads).end()) {
1238 unsigned tid = *threads++;
1239 fetchRedirect[tid] = false;
1240 }
1241
1242 // Uncomment this if you want to see all available instructions.
1243// printAvailableInsts();
1244
1245 // Execute/writeback any instructions that are available.
1246 int insts_to_execute = fromIssue->size;
1247 int inst_num = 0;
1248 for (; inst_num < insts_to_execute;
1249 ++inst_num) {
1250
1251 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1252
1253 DynInstPtr inst = instQueue.getInstToExecute();
1254
1255 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1256 inst->readPC(), inst->threadNumber,inst->seqNum);
1257
1258 // Check if the instruction is squashed; if so then skip it
1259 if (inst->isSquashed()) {
1260 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1261
1262 // Consider this instruction executed so that commit can go
1263 // ahead and retire the instruction.
1264 inst->setExecuted();
1265
1266 // Not sure if I should set this here or just let commit try to
1267 // commit any squashed instructions. I like the latter a bit more.
1268 inst->setCanCommit();
1269
1270 ++iewExecSquashedInsts;
1271
1272 decrWb(inst->seqNum);
1273 continue;
1274 }
1275
1276 Fault fault = NoFault;
1277
1278 // Execute instruction.
1279 // Note that if the instruction faults, it will be handled
1280 // at the commit stage.
1281 if (inst->isMemRef() &&
1282 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1283 DPRINTF(IEW, "Execute: Calculating address for memory "
1284 "reference.\n");
1285
1286 // Tell the LDSTQ to execute this instruction (if it is a load).
1287 if (inst->isLoad()) {
1288 // Loads will mark themselves as executed, and their writeback
1289 // event adds the instruction to the queue to commit
1290 fault = ldstQueue.executeLoad(inst);
1291 } else if (inst->isStore()) {
1292 fault = ldstQueue.executeStore(inst);
1293
1294 // If the store had a fault then it may not have a mem req
1295 if (!inst->isStoreConditional() && fault == NoFault) {
1296 inst->setExecuted();
1297
1298 instToCommit(inst);
1299 } else if (fault != NoFault) {
1300 // If the instruction faulted, then we need to send it along to commit
1301 // without the instruction completing.
|
1296 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1297 fault->name(), inst->seqNum);
| 1302 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
|
1298
1299 // Send this instruction to commit, also make sure iew stage
1300 // realizes there is activity.
1301 inst->setExecuted();
1302
1303 instToCommit(inst);
1304 activityThisCycle();
1305 }
1306
1307 // Store conditionals will mark themselves as
1308 // executed, and their writeback event will add the
1309 // instruction to the queue to commit.
1310 } else {
1311 panic("Unexpected memory type!\n");
1312 }
1313
1314 } else {
1315 inst->execute();
1316
1317 inst->setExecuted();
1318
1319 instToCommit(inst);
1320 }
1321
1322 updateExeInstStats(inst);
1323
1324 // Check if branch prediction was correct, if not then we need
1325 // to tell commit to squash in flight instructions. Only
1326 // handle this if there hasn't already been something that
1327 // redirects fetch in this group of instructions.
1328
1329 // This probably needs to prioritize the redirects if a different
1330 // scheduler is used. Currently the scheduler schedules the oldest
1331 // instruction first, so the branch resolution order will be correct.
1332 unsigned tid = inst->threadNumber;
1333
| 1303
1304 // Send this instruction to commit, also make sure iew stage
1305 // realizes there is activity.
1306 inst->setExecuted();
1307
1308 instToCommit(inst);
1309 activityThisCycle();
1310 }
1311
1312 // Store conditionals will mark themselves as
1313 // executed, and their writeback event will add the
1314 // instruction to the queue to commit.
1315 } else {
1316 panic("Unexpected memory type!\n");
1317 }
1318
1319 } else {
1320 inst->execute();
1321
1322 inst->setExecuted();
1323
1324 instToCommit(inst);
1325 }
1326
1327 updateExeInstStats(inst);
1328
1329 // Check if branch prediction was correct, if not then we need
1330 // to tell commit to squash in flight instructions. Only
1331 // handle this if there hasn't already been something that
1332 // redirects fetch in this group of instructions.
1333
1334 // This probably needs to prioritize the redirects if a different
1335 // scheduler is used. Currently the scheduler schedules the oldest
1336 // instruction first, so the branch resolution order will be correct.
1337 unsigned tid = inst->threadNumber;
1338
|
1334 if (!fetchRedirect[tid] ||
1335 toCommit->squashedSeqNum[tid] > inst->seqNum) {
| 1339 if (!fetchRedirect[tid]) {
|
1336
1337 if (inst->mispredicted()) {
1338 fetchRedirect[tid] = true;
1339
1340 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1341#if ISA_HAS_DELAY_SLOT
1342 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1343 inst->nextNPC);
1344#else
1345 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1346 inst->nextPC);
1347#endif
1348 // If incorrect, then signal the ROB that it must be squashed.
1349 squashDueToBranch(inst, tid);
1350
1351 if (inst->predTaken()) {
1352 predictedTakenIncorrect++;
1353 } else {
1354 predictedNotTakenIncorrect++;
1355 }
1356 } else if (ldstQueue.violation(tid)) {
| 1340
1341 if (inst->mispredicted()) {
1342 fetchRedirect[tid] = true;
1343
1344 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1345#if ISA_HAS_DELAY_SLOT
1346 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1347 inst->nextNPC);
1348#else
1349 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1350 inst->nextPC);
1351#endif
1352 // If incorrect, then signal the ROB that it must be squashed.
1353 squashDueToBranch(inst, tid);
1354
1355 if (inst->predTaken()) {
1356 predictedTakenIncorrect++;
1357 } else {
1358 predictedNotTakenIncorrect++;
1359 }
1360 } else if (ldstQueue.violation(tid)) {
|
| 1361 fetchRedirect[tid] = true;
1362
|
1357 // If there was an ordering violation, then get the
1358 // DynInst that caused the violation. Note that this
1359 // clears the violation signal.
1360 DynInstPtr violator;
1361 violator = ldstQueue.getMemDepViolator(tid);
1362
1363 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1364 "%#x, inst PC: %#x. Addr is: %#x.\n",
1365 violator->readPC(), inst->readPC(), inst->physEffAddr);
1366
| 1363 // If there was an ordering violation, then get the
1364 // DynInst that caused the violation. Note that this
1365 // clears the violation signal.
1366 DynInstPtr violator;
1367 violator = ldstQueue.getMemDepViolator(tid);
1368
1369 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1370 "%#x, inst PC: %#x. Addr is: %#x.\n",
1371 violator->readPC(), inst->readPC(), inst->physEffAddr);
1372
|
1367 // Ensure the violating instruction is older than
1368 // current squash
1369 if (fetchRedirect[tid] &&
1370 violator->seqNum >= toCommit->squashedSeqNum[tid])
1371 continue;
1372
1373 fetchRedirect[tid] = true;
1374
| |
1375 // Tell the instruction queue that a violation has occured.
1376 instQueue.violation(inst, violator);
1377
1378 // Squash.
1379 squashDueToMemOrder(inst,tid);
1380
1381 ++memOrderViolationEvents;
1382 } else if (ldstQueue.loadBlocked(tid) &&
1383 !ldstQueue.isLoadBlockedHandled(tid)) {
1384 fetchRedirect[tid] = true;
1385
1386 DPRINTF(IEW, "Load operation couldn't execute because the "
1387 "memory system is blocked. PC: %#x [sn:%lli]\n",
1388 inst->readPC(), inst->seqNum);
1389
1390 squashDueToMemBlocked(inst, tid);
1391 }
1392 }
1393 }
1394
1395 // Update and record activity if we processed any instructions.
1396 if (inst_num) {
1397 if (exeStatus == Idle) {
1398 exeStatus = Running;
1399 }
1400
1401 updatedQueues = true;
1402
1403 cpu->activityThisCycle();
1404 }
1405
1406 // Need to reset this in case a writeback event needs to write into the
1407 // iew queue. That way the writeback event will write into the correct
1408 // spot in the queue.
1409 wbNumInst = 0;
1410}
1411
1412template <class Impl>
1413void
1414DefaultIEW<Impl>::writebackInsts()
1415{
1416 // Loop through the head of the time buffer and wake any
1417 // dependents. These instructions are about to write back. Also
1418 // mark scoreboard that this instruction is finally complete.
1419 // Either have IEW have direct access to scoreboard, or have this
1420 // as part of backwards communication.
1421 for (int inst_num = 0; inst_num < issueWidth &&
1422 toCommit->insts[inst_num]; inst_num++) {
1423 DynInstPtr inst = toCommit->insts[inst_num];
1424 int tid = inst->threadNumber;
1425
1426 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1427 inst->seqNum, inst->readPC());
1428
1429 iewInstsToCommit[tid]++;
1430
1431 // Some instructions will be sent to commit without having
1432 // executed because they need commit to handle them.
1433 // E.g. Uncached loads have not actually executed when they
1434 // are first sent to commit. Instead commit must tell the LSQ
1435 // when it's ready to execute the uncached load.
1436 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1437 int dependents = instQueue.wakeDependents(inst);
1438
1439 for (int i = 0; i < inst->numDestRegs(); i++) {
1440 //mark as Ready
1441 DPRINTF(IEW,"Setting Destination Register %i\n",
1442 inst->renamedDestRegIdx(i));
1443 scoreboard->setReg(inst->renamedDestRegIdx(i));
1444 }
1445
1446 if (dependents) {
1447 producerInst[tid]++;
1448 consumerInst[tid]+= dependents;
1449 }
1450 writebackCount[tid]++;
1451 }
1452
1453 decrWb(inst->seqNum);
1454 }
1455}
1456
1457template<class Impl>
1458void
1459DefaultIEW<Impl>::tick()
1460{
1461 wbNumInst = 0;
1462 wbCycle = 0;
1463
1464 wroteToTimeBuffer = false;
1465 updatedQueues = false;
1466
1467 sortInsts();
1468
1469 // Free function units marked as being freed this cycle.
1470 fuPool->processFreeUnits();
1471
1472 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1473
1474 // Check stall and squash signals, dispatch any instructions.
1475 while (threads != (*activeThreads).end()) {
1476 unsigned tid = *threads++;
1477
1478 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1479
1480 checkSignalsAndUpdate(tid);
1481 dispatch(tid);
1482 }
1483
1484 if (exeStatus != Squashing) {
1485 executeInsts();
1486
1487 writebackInsts();
1488
1489 // Have the instruction queue try to schedule any ready instructions.
1490 // (In actuality, this scheduling is for instructions that will
1491 // be executed next cycle.)
1492 instQueue.scheduleReadyInsts();
1493
1494 // Also should advance its own time buffers if the stage ran.
1495 // Not the best place for it, but this works (hopefully).
1496 issueToExecQueue.advance();
1497 }
1498
1499 bool broadcast_free_entries = false;
1500
1501 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1502 exeStatus = Idle;
1503 updateLSQNextCycle = false;
1504
1505 broadcast_free_entries = true;
1506 }
1507
1508 // Writeback any stores using any leftover bandwidth.
1509 ldstQueue.writebackStores();
1510
1511 // Check the committed load/store signals to see if there's a load
1512 // or store to commit. Also check if it's being told to execute a
1513 // nonspeculative instruction.
1514 // This is pretty inefficient...
1515
1516 threads = (*activeThreads).begin();
1517 while (threads != (*activeThreads).end()) {
1518 unsigned tid = (*threads++);
1519
1520 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1521
1522 // Update structures based on instructions committed.
1523 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1524 !fromCommit->commitInfo[tid].squash &&
1525 !fromCommit->commitInfo[tid].robSquashing) {
1526
1527 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1528
1529 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1530
1531 updateLSQNextCycle = true;
1532 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1533 }
1534
1535 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1536
1537 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1538 if (fromCommit->commitInfo[tid].uncached) {
1539 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1540 } else {
1541 instQueue.scheduleNonSpec(
1542 fromCommit->commitInfo[tid].nonSpecSeqNum);
1543 }
1544 }
1545
1546 if (broadcast_free_entries) {
1547 toFetch->iewInfo[tid].iqCount =
1548 instQueue.getCount(tid);
1549 toFetch->iewInfo[tid].ldstqCount =
1550 ldstQueue.getCount(tid);
1551
1552 toRename->iewInfo[tid].usedIQ = true;
1553 toRename->iewInfo[tid].freeIQEntries =
1554 instQueue.numFreeEntries();
1555 toRename->iewInfo[tid].usedLSQ = true;
1556 toRename->iewInfo[tid].freeLSQEntries =
1557 ldstQueue.numFreeEntries(tid);
1558
1559 wroteToTimeBuffer = true;
1560 }
1561
1562 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1563 tid, toRename->iewInfo[tid].dispatched);
1564 }
1565
1566 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1567 "LSQ has %i free entries.\n",
1568 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1569 ldstQueue.numFreeEntries());
1570
1571 updateStatus();
1572
1573 if (wroteToTimeBuffer) {
1574 DPRINTF(Activity, "Activity this cycle.\n");
1575 cpu->activityThisCycle();
1576 }
1577}
1578
1579template <class Impl>
1580void
1581DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1582{
1583 int thread_number = inst->threadNumber;
1584
1585 //
1586 // Pick off the software prefetches
1587 //
1588#ifdef TARGET_ALPHA
1589 if (inst->isDataPrefetch())
1590 iewExecutedSwp[thread_number]++;
1591 else
1592 iewIewExecutedcutedInsts++;
1593#else
1594 iewExecutedInsts++;
1595#endif
1596
1597 //
1598 // Control operations
1599 //
1600 if (inst->isControl())
1601 iewExecutedBranches[thread_number]++;
1602
1603 //
1604 // Memory operations
1605 //
1606 if (inst->isMemRef()) {
1607 iewExecutedRefs[thread_number]++;
1608
1609 if (inst->isLoad()) {
1610 iewExecLoadInsts[thread_number]++;
1611 }
1612 }
1613}
| 1373 // Tell the instruction queue that a violation has occured.
1374 instQueue.violation(inst, violator);
1375
1376 // Squash.
1377 squashDueToMemOrder(inst,tid);
1378
1379 ++memOrderViolationEvents;
1380 } else if (ldstQueue.loadBlocked(tid) &&
1381 !ldstQueue.isLoadBlockedHandled(tid)) {
1382 fetchRedirect[tid] = true;
1383
1384 DPRINTF(IEW, "Load operation couldn't execute because the "
1385 "memory system is blocked. PC: %#x [sn:%lli]\n",
1386 inst->readPC(), inst->seqNum);
1387
1388 squashDueToMemBlocked(inst, tid);
1389 }
1390 }
1391 }
1392
1393 // Update and record activity if we processed any instructions.
1394 if (inst_num) {
1395 if (exeStatus == Idle) {
1396 exeStatus = Running;
1397 }
1398
1399 updatedQueues = true;
1400
1401 cpu->activityThisCycle();
1402 }
1403
1404 // Need to reset this in case a writeback event needs to write into the
1405 // iew queue. That way the writeback event will write into the correct
1406 // spot in the queue.
1407 wbNumInst = 0;
1408}
1409
1410template <class Impl>
1411void
1412DefaultIEW<Impl>::writebackInsts()
1413{
1414 // Loop through the head of the time buffer and wake any
1415 // dependents. These instructions are about to write back. Also
1416 // mark scoreboard that this instruction is finally complete.
1417 // Either have IEW have direct access to scoreboard, or have this
1418 // as part of backwards communication.
1419 for (int inst_num = 0; inst_num < issueWidth &&
1420 toCommit->insts[inst_num]; inst_num++) {
1421 DynInstPtr inst = toCommit->insts[inst_num];
1422 int tid = inst->threadNumber;
1423
1424 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1425 inst->seqNum, inst->readPC());
1426
1427 iewInstsToCommit[tid]++;
1428
1429 // Some instructions will be sent to commit without having
1430 // executed because they need commit to handle them.
1431 // E.g. Uncached loads have not actually executed when they
1432 // are first sent to commit. Instead commit must tell the LSQ
1433 // when it's ready to execute the uncached load.
1434 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1435 int dependents = instQueue.wakeDependents(inst);
1436
1437 for (int i = 0; i < inst->numDestRegs(); i++) {
1438 //mark as Ready
1439 DPRINTF(IEW,"Setting Destination Register %i\n",
1440 inst->renamedDestRegIdx(i));
1441 scoreboard->setReg(inst->renamedDestRegIdx(i));
1442 }
1443
1444 if (dependents) {
1445 producerInst[tid]++;
1446 consumerInst[tid]+= dependents;
1447 }
1448 writebackCount[tid]++;
1449 }
1450
1451 decrWb(inst->seqNum);
1452 }
1453}
1454
1455template<class Impl>
1456void
1457DefaultIEW<Impl>::tick()
1458{
1459 wbNumInst = 0;
1460 wbCycle = 0;
1461
1462 wroteToTimeBuffer = false;
1463 updatedQueues = false;
1464
1465 sortInsts();
1466
1467 // Free function units marked as being freed this cycle.
1468 fuPool->processFreeUnits();
1469
1470 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1471
1472 // Check stall and squash signals, dispatch any instructions.
1473 while (threads != (*activeThreads).end()) {
1474 unsigned tid = *threads++;
1475
1476 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1477
1478 checkSignalsAndUpdate(tid);
1479 dispatch(tid);
1480 }
1481
1482 if (exeStatus != Squashing) {
1483 executeInsts();
1484
1485 writebackInsts();
1486
1487 // Have the instruction queue try to schedule any ready instructions.
1488 // (In actuality, this scheduling is for instructions that will
1489 // be executed next cycle.)
1490 instQueue.scheduleReadyInsts();
1491
1492 // Also should advance its own time buffers if the stage ran.
1493 // Not the best place for it, but this works (hopefully).
1494 issueToExecQueue.advance();
1495 }
1496
1497 bool broadcast_free_entries = false;
1498
1499 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1500 exeStatus = Idle;
1501 updateLSQNextCycle = false;
1502
1503 broadcast_free_entries = true;
1504 }
1505
1506 // Writeback any stores using any leftover bandwidth.
1507 ldstQueue.writebackStores();
1508
1509 // Check the committed load/store signals to see if there's a load
1510 // or store to commit. Also check if it's being told to execute a
1511 // nonspeculative instruction.
1512 // This is pretty inefficient...
1513
1514 threads = (*activeThreads).begin();
1515 while (threads != (*activeThreads).end()) {
1516 unsigned tid = (*threads++);
1517
1518 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1519
1520 // Update structures based on instructions committed.
1521 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1522 !fromCommit->commitInfo[tid].squash &&
1523 !fromCommit->commitInfo[tid].robSquashing) {
1524
1525 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1526
1527 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1528
1529 updateLSQNextCycle = true;
1530 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1531 }
1532
1533 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1534
1535 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1536 if (fromCommit->commitInfo[tid].uncached) {
1537 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1538 } else {
1539 instQueue.scheduleNonSpec(
1540 fromCommit->commitInfo[tid].nonSpecSeqNum);
1541 }
1542 }
1543
1544 if (broadcast_free_entries) {
1545 toFetch->iewInfo[tid].iqCount =
1546 instQueue.getCount(tid);
1547 toFetch->iewInfo[tid].ldstqCount =
1548 ldstQueue.getCount(tid);
1549
1550 toRename->iewInfo[tid].usedIQ = true;
1551 toRename->iewInfo[tid].freeIQEntries =
1552 instQueue.numFreeEntries();
1553 toRename->iewInfo[tid].usedLSQ = true;
1554 toRename->iewInfo[tid].freeLSQEntries =
1555 ldstQueue.numFreeEntries(tid);
1556
1557 wroteToTimeBuffer = true;
1558 }
1559
1560 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1561 tid, toRename->iewInfo[tid].dispatched);
1562 }
1563
1564 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1565 "LSQ has %i free entries.\n",
1566 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1567 ldstQueue.numFreeEntries());
1568
1569 updateStatus();
1570
1571 if (wroteToTimeBuffer) {
1572 DPRINTF(Activity, "Activity this cycle.\n");
1573 cpu->activityThisCycle();
1574 }
1575}
1576
1577template <class Impl>
1578void
1579DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1580{
1581 int thread_number = inst->threadNumber;
1582
1583 //
1584 // Pick off the software prefetches
1585 //
1586#ifdef TARGET_ALPHA
1587 if (inst->isDataPrefetch())
1588 iewExecutedSwp[thread_number]++;
1589 else
1590 iewIewExecutedcutedInsts++;
1591#else
1592 iewExecutedInsts++;
1593#endif
1594
1595 //
1596 // Control operations
1597 //
1598 if (inst->isControl())
1599 iewExecutedBranches[thread_number]++;
1600
1601 //
1602 // Memory operations
1603 //
1604 if (inst->isMemRef()) {
1605 iewExecutedRefs[thread_number]++;
1606
1607 if (inst->isLoad()) {
1608 iewExecLoadInsts[thread_number]++;
1609 }
1610 }
1611}
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