1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 dispatchWidth(params->dispatchWidth),
54 issueWidth(params->issueWidth),
55 wbOutstanding(0),
56 wbWidth(params->wbWidth),
57 numThreads(params->numberOfThreads),
58 switchedOut(false)
59{
60 _status = Active;
61 exeStatus = Running;
62 wbStatus = Idle;
63
64 // Setup wire to read instructions coming from issue.
65 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
66
67 // Instruction queue needs the queue between issue and execute.
68 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
69
70 instQueue.setIEW(this);
71 ldstQueue.setIEW(this);
72
73 for (int i=0; i < numThreads; i++) {
74 dispatchStatus[i] = Running;
75 stalls[i].commit = false;
76 fetchRedirect[i] = false;
77 }
78
79 wbMax = wbWidth * params->wbDepth;
80
81 updateLSQNextCycle = false;
82
83 ableToIssue = true;
84
85 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
86}
87
88template <class Impl>
89std::string
90DefaultIEW<Impl>::name() const
91{
92 return cpu->name() + ".iew";
93}
94
95template <class Impl>
96void
97DefaultIEW<Impl>::regStats()
98{
99 using namespace Stats;
100
101 instQueue.regStats();
102 ldstQueue.regStats();
103
104 iewIdleCycles
105 .name(name() + ".iewIdleCycles")
106 .desc("Number of cycles IEW is idle");
107
108 iewSquashCycles
109 .name(name() + ".iewSquashCycles")
110 .desc("Number of cycles IEW is squashing");
111
112 iewBlockCycles
113 .name(name() + ".iewBlockCycles")
114 .desc("Number of cycles IEW is blocking");
115
116 iewUnblockCycles
117 .name(name() + ".iewUnblockCycles")
118 .desc("Number of cycles IEW is unblocking");
119
120 iewDispatchedInsts
121 .name(name() + ".iewDispatchedInsts")
122 .desc("Number of instructions dispatched to IQ");
123
124 iewDispSquashedInsts
125 .name(name() + ".iewDispSquashedInsts")
126 .desc("Number of squashed instructions skipped by dispatch");
127
128 iewDispLoadInsts
129 .name(name() + ".iewDispLoadInsts")
130 .desc("Number of dispatched load instructions");
131
132 iewDispStoreInsts
133 .name(name() + ".iewDispStoreInsts")
134 .desc("Number of dispatched store instructions");
135
136 iewDispNonSpecInsts
137 .name(name() + ".iewDispNonSpecInsts")
138 .desc("Number of dispatched non-speculative instructions");
139
140 iewIQFullEvents
141 .name(name() + ".iewIQFullEvents")
142 .desc("Number of times the IQ has become full, causing a stall");
143
144 iewLSQFullEvents
145 .name(name() + ".iewLSQFullEvents")
146 .desc("Number of times the LSQ has become full, causing a stall");
147
148 memOrderViolationEvents
149 .name(name() + ".memOrderViolationEvents")
150 .desc("Number of memory order violations");
151
152 predictedTakenIncorrect
153 .name(name() + ".predictedTakenIncorrect")
154 .desc("Number of branches that were predicted taken incorrectly");
155
156 predictedNotTakenIncorrect
157 .name(name() + ".predictedNotTakenIncorrect")
158 .desc("Number of branches that were predicted not taken incorrectly");
159
160 branchMispredicts
161 .name(name() + ".branchMispredicts")
162 .desc("Number of branch mispredicts detected at execute");
163
164 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
165
166 iewExecutedInsts
167 .name(name() + ".EXEC:insts")
168 .desc("Number of executed instructions");
169
170 iewExecLoadInsts
171 .init(cpu->number_of_threads)
172 .name(name() + ".EXEC:loads")
173 .desc("Number of load instructions executed")
174 .flags(total);
175
176 iewExecSquashedInsts
177 .name(name() + ".EXEC:squashedInsts")
178 .desc("Number of squashed instructions skipped in execute");
179
180 iewExecutedSwp
181 .init(cpu->number_of_threads)
182 .name(name() + ".EXEC:swp")
183 .desc("number of swp insts executed")
184 .flags(total);
185
186 iewExecutedNop
187 .init(cpu->number_of_threads)
188 .name(name() + ".EXEC:nop")
189 .desc("number of nop insts executed")
190 .flags(total);
191
192 iewExecutedRefs
193 .init(cpu->number_of_threads)
194 .name(name() + ".EXEC:refs")
195 .desc("number of memory reference insts executed")
196 .flags(total);
197
198 iewExecutedBranches
199 .init(cpu->number_of_threads)
200 .name(name() + ".EXEC:branches")
201 .desc("Number of branches executed")
202 .flags(total);
203
204 iewExecStoreInsts
205 .name(name() + ".EXEC:stores")
206 .desc("Number of stores executed")
207 .flags(total);
208 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
209
210 iewExecRate
211 .name(name() + ".EXEC:rate")
212 .desc("Inst execution rate")
213 .flags(total);
214
215 iewExecRate = iewExecutedInsts / cpu->numCycles;
216
217 iewInstsToCommit
218 .init(cpu->number_of_threads)
219 .name(name() + ".WB:sent")
220 .desc("cumulative count of insts sent to commit")
221 .flags(total);
222
223 writebackCount
224 .init(cpu->number_of_threads)
225 .name(name() + ".WB:count")
226 .desc("cumulative count of insts written-back")
227 .flags(total);
228
229 producerInst
230 .init(cpu->number_of_threads)
231 .name(name() + ".WB:producers")
232 .desc("num instructions producing a value")
233 .flags(total);
234
235 consumerInst
236 .init(cpu->number_of_threads)
237 .name(name() + ".WB:consumers")
238 .desc("num instructions consuming a value")
239 .flags(total);
240
241 wbPenalized
242 .init(cpu->number_of_threads)
243 .name(name() + ".WB:penalized")
244 .desc("number of instrctions required to write to 'other' IQ")
245 .flags(total);
246
247 wbPenalizedRate
248 .name(name() + ".WB:penalized_rate")
249 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
250 .flags(total);
251
252 wbPenalizedRate = wbPenalized / writebackCount;
253
254 wbFanout
255 .name(name() + ".WB:fanout")
256 .desc("average fanout of values written-back")
257 .flags(total);
258
259 wbFanout = producerInst / consumerInst;
260
261 wbRate
262 .name(name() + ".WB:rate")
263 .desc("insts written-back per cycle")
264 .flags(total);
265 wbRate = writebackCount / cpu->numCycles;
266}
267
268template<class Impl>
269void
270DefaultIEW<Impl>::initStage()
271{
272 for (int tid=0; tid < numThreads; tid++) {
273 toRename->iewInfo[tid].usedIQ = true;
274 toRename->iewInfo[tid].freeIQEntries =
275 instQueue.numFreeEntries(tid);
276
277 toRename->iewInfo[tid].usedLSQ = true;
278 toRename->iewInfo[tid].freeLSQEntries =
279 ldstQueue.numFreeEntries(tid);
280 }
281}
282
283template<class Impl>
284void
285DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
286{
287 DPRINTF(IEW, "Setting CPU pointer.\n");
288 cpu = cpu_ptr;
289
290 instQueue.setCPU(cpu_ptr);
291 ldstQueue.setCPU(cpu_ptr);
292
293 cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300 DPRINTF(IEW, "Setting time buffer pointer.\n");
301 timeBuffer = tb_ptr;
302
303 // Setup wire to read information from time buffer, from commit.
304 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
305
306 // Setup wire to write information back to previous stages.
307 toRename = timeBuffer->getWire(0);
308
309 toFetch = timeBuffer->getWire(0);
310
311 // Instruction queue also needs main time buffer.
312 instQueue.setTimeBuffer(tb_ptr);
313}
314
315template<class Impl>
316void
317DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318{
319 DPRINTF(IEW, "Setting rename queue pointer.\n");
320 renameQueue = rq_ptr;
321
322 // Setup wire to read information from rename queue.
323 fromRename = renameQueue->getWire(-renameToIEWDelay);
324}
325
326template<class Impl>
327void
328DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
329{
330 DPRINTF(IEW, "Setting IEW queue pointer.\n");
331 iewQueue = iq_ptr;
332
333 // Setup wire to write instructions to commit.
334 toCommit = iewQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
340{
341 DPRINTF(IEW, "Setting active threads list pointer.\n");
342 activeThreads = at_ptr;
343
344 ldstQueue.setActiveThreads(at_ptr);
345 instQueue.setActiveThreads(at_ptr);
346}
347
348template<class Impl>
349void
350DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
351{
352 DPRINTF(IEW, "Setting scoreboard pointer.\n");
353 scoreboard = sb_ptr;
354}
355
356template <class Impl>
357void
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 dispatchWidth(params->dispatchWidth),
54 issueWidth(params->issueWidth),
55 wbOutstanding(0),
56 wbWidth(params->wbWidth),
57 numThreads(params->numberOfThreads),
58 switchedOut(false)
59{
60 _status = Active;
61 exeStatus = Running;
62 wbStatus = Idle;
63
64 // Setup wire to read instructions coming from issue.
65 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
66
67 // Instruction queue needs the queue between issue and execute.
68 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
69
70 instQueue.setIEW(this);
71 ldstQueue.setIEW(this);
72
73 for (int i=0; i < numThreads; i++) {
74 dispatchStatus[i] = Running;
75 stalls[i].commit = false;
76 fetchRedirect[i] = false;
77 }
78
79 wbMax = wbWidth * params->wbDepth;
80
81 updateLSQNextCycle = false;
82
83 ableToIssue = true;
84
85 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
86}
87
88template <class Impl>
89std::string
90DefaultIEW<Impl>::name() const
91{
92 return cpu->name() + ".iew";
93}
94
95template <class Impl>
96void
97DefaultIEW<Impl>::regStats()
98{
99 using namespace Stats;
100
101 instQueue.regStats();
102 ldstQueue.regStats();
103
104 iewIdleCycles
105 .name(name() + ".iewIdleCycles")
106 .desc("Number of cycles IEW is idle");
107
108 iewSquashCycles
109 .name(name() + ".iewSquashCycles")
110 .desc("Number of cycles IEW is squashing");
111
112 iewBlockCycles
113 .name(name() + ".iewBlockCycles")
114 .desc("Number of cycles IEW is blocking");
115
116 iewUnblockCycles
117 .name(name() + ".iewUnblockCycles")
118 .desc("Number of cycles IEW is unblocking");
119
120 iewDispatchedInsts
121 .name(name() + ".iewDispatchedInsts")
122 .desc("Number of instructions dispatched to IQ");
123
124 iewDispSquashedInsts
125 .name(name() + ".iewDispSquashedInsts")
126 .desc("Number of squashed instructions skipped by dispatch");
127
128 iewDispLoadInsts
129 .name(name() + ".iewDispLoadInsts")
130 .desc("Number of dispatched load instructions");
131
132 iewDispStoreInsts
133 .name(name() + ".iewDispStoreInsts")
134 .desc("Number of dispatched store instructions");
135
136 iewDispNonSpecInsts
137 .name(name() + ".iewDispNonSpecInsts")
138 .desc("Number of dispatched non-speculative instructions");
139
140 iewIQFullEvents
141 .name(name() + ".iewIQFullEvents")
142 .desc("Number of times the IQ has become full, causing a stall");
143
144 iewLSQFullEvents
145 .name(name() + ".iewLSQFullEvents")
146 .desc("Number of times the LSQ has become full, causing a stall");
147
148 memOrderViolationEvents
149 .name(name() + ".memOrderViolationEvents")
150 .desc("Number of memory order violations");
151
152 predictedTakenIncorrect
153 .name(name() + ".predictedTakenIncorrect")
154 .desc("Number of branches that were predicted taken incorrectly");
155
156 predictedNotTakenIncorrect
157 .name(name() + ".predictedNotTakenIncorrect")
158 .desc("Number of branches that were predicted not taken incorrectly");
159
160 branchMispredicts
161 .name(name() + ".branchMispredicts")
162 .desc("Number of branch mispredicts detected at execute");
163
164 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
165
166 iewExecutedInsts
167 .name(name() + ".EXEC:insts")
168 .desc("Number of executed instructions");
169
170 iewExecLoadInsts
171 .init(cpu->number_of_threads)
172 .name(name() + ".EXEC:loads")
173 .desc("Number of load instructions executed")
174 .flags(total);
175
176 iewExecSquashedInsts
177 .name(name() + ".EXEC:squashedInsts")
178 .desc("Number of squashed instructions skipped in execute");
179
180 iewExecutedSwp
181 .init(cpu->number_of_threads)
182 .name(name() + ".EXEC:swp")
183 .desc("number of swp insts executed")
184 .flags(total);
185
186 iewExecutedNop
187 .init(cpu->number_of_threads)
188 .name(name() + ".EXEC:nop")
189 .desc("number of nop insts executed")
190 .flags(total);
191
192 iewExecutedRefs
193 .init(cpu->number_of_threads)
194 .name(name() + ".EXEC:refs")
195 .desc("number of memory reference insts executed")
196 .flags(total);
197
198 iewExecutedBranches
199 .init(cpu->number_of_threads)
200 .name(name() + ".EXEC:branches")
201 .desc("Number of branches executed")
202 .flags(total);
203
204 iewExecStoreInsts
205 .name(name() + ".EXEC:stores")
206 .desc("Number of stores executed")
207 .flags(total);
208 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
209
210 iewExecRate
211 .name(name() + ".EXEC:rate")
212 .desc("Inst execution rate")
213 .flags(total);
214
215 iewExecRate = iewExecutedInsts / cpu->numCycles;
216
217 iewInstsToCommit
218 .init(cpu->number_of_threads)
219 .name(name() + ".WB:sent")
220 .desc("cumulative count of insts sent to commit")
221 .flags(total);
222
223 writebackCount
224 .init(cpu->number_of_threads)
225 .name(name() + ".WB:count")
226 .desc("cumulative count of insts written-back")
227 .flags(total);
228
229 producerInst
230 .init(cpu->number_of_threads)
231 .name(name() + ".WB:producers")
232 .desc("num instructions producing a value")
233 .flags(total);
234
235 consumerInst
236 .init(cpu->number_of_threads)
237 .name(name() + ".WB:consumers")
238 .desc("num instructions consuming a value")
239 .flags(total);
240
241 wbPenalized
242 .init(cpu->number_of_threads)
243 .name(name() + ".WB:penalized")
244 .desc("number of instrctions required to write to 'other' IQ")
245 .flags(total);
246
247 wbPenalizedRate
248 .name(name() + ".WB:penalized_rate")
249 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
250 .flags(total);
251
252 wbPenalizedRate = wbPenalized / writebackCount;
253
254 wbFanout
255 .name(name() + ".WB:fanout")
256 .desc("average fanout of values written-back")
257 .flags(total);
258
259 wbFanout = producerInst / consumerInst;
260
261 wbRate
262 .name(name() + ".WB:rate")
263 .desc("insts written-back per cycle")
264 .flags(total);
265 wbRate = writebackCount / cpu->numCycles;
266}
267
268template<class Impl>
269void
270DefaultIEW<Impl>::initStage()
271{
272 for (int tid=0; tid < numThreads; tid++) {
273 toRename->iewInfo[tid].usedIQ = true;
274 toRename->iewInfo[tid].freeIQEntries =
275 instQueue.numFreeEntries(tid);
276
277 toRename->iewInfo[tid].usedLSQ = true;
278 toRename->iewInfo[tid].freeLSQEntries =
279 ldstQueue.numFreeEntries(tid);
280 }
281}
282
283template<class Impl>
284void
285DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
286{
287 DPRINTF(IEW, "Setting CPU pointer.\n");
288 cpu = cpu_ptr;
289
290 instQueue.setCPU(cpu_ptr);
291 ldstQueue.setCPU(cpu_ptr);
292
293 cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300 DPRINTF(IEW, "Setting time buffer pointer.\n");
301 timeBuffer = tb_ptr;
302
303 // Setup wire to read information from time buffer, from commit.
304 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
305
306 // Setup wire to write information back to previous stages.
307 toRename = timeBuffer->getWire(0);
308
309 toFetch = timeBuffer->getWire(0);
310
311 // Instruction queue also needs main time buffer.
312 instQueue.setTimeBuffer(tb_ptr);
313}
314
315template<class Impl>
316void
317DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318{
319 DPRINTF(IEW, "Setting rename queue pointer.\n");
320 renameQueue = rq_ptr;
321
322 // Setup wire to read information from rename queue.
323 fromRename = renameQueue->getWire(-renameToIEWDelay);
324}
325
326template<class Impl>
327void
328DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
329{
330 DPRINTF(IEW, "Setting IEW queue pointer.\n");
331 iewQueue = iq_ptr;
332
333 // Setup wire to write instructions to commit.
334 toCommit = iewQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
340{
341 DPRINTF(IEW, "Setting active threads list pointer.\n");
342 activeThreads = at_ptr;
343
344 ldstQueue.setActiveThreads(at_ptr);
345 instQueue.setActiveThreads(at_ptr);
346}
347
348template<class Impl>
349void
350DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
351{
352 DPRINTF(IEW, "Setting scoreboard pointer.\n");
353 scoreboard = sb_ptr;
354}
355
356template <class Impl>
357void
|
368 // Clear any state.
369 switchedOut = true;
370
371 instQueue.switchOut();
372 ldstQueue.switchOut();
373 fuPool->switchOut();
374
375 for (int i = 0; i < numThreads; i++) {
376 while (!insts[i].empty())
377 insts[i].pop();
378 while (!skidBuffer[i].empty())
379 skidBuffer[i].pop();
380 }
381}
382
383template <class Impl>
384void
385DefaultIEW<Impl>::takeOverFrom()
386{
387 // Reset all state.
388 _status = Active;
389 exeStatus = Running;
390 wbStatus = Idle;
391 switchedOut = false;
392
393 instQueue.takeOverFrom();
394 ldstQueue.takeOverFrom();
395 fuPool->takeOverFrom();
396
397 initStage();
398 cpu->activityThisCycle();
399
400 for (int i=0; i < numThreads; i++) {
401 dispatchStatus[i] = Running;
402 stalls[i].commit = false;
403 fetchRedirect[i] = false;
404 }
405
406 updateLSQNextCycle = false;
407
408 // @todo: Fix hardcoded number
409 for (int i = 0; i < 6; ++i) {
410 issueToExecQueue.advance();
411 }
412}
413
414template<class Impl>
415void
416DefaultIEW<Impl>::squash(unsigned tid)
417{
418 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
419 tid);
420
421 // Tell the IQ to start squashing.
422 instQueue.squash(tid);
423
424 // Tell the LDSTQ to start squashing.
425 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
426
427 updatedQueues = true;
428
429 // Clear the skid buffer in case it has any data in it.
430 while (!skidBuffer[tid].empty()) {
431
432 if (skidBuffer[tid].front()->isLoad() ||
433 skidBuffer[tid].front()->isStore() ) {
434 toRename->iewInfo[tid].dispatchedToLSQ++;
435 }
436
437 toRename->iewInfo[tid].dispatched++;
438
439 skidBuffer[tid].pop();
440 }
441
442 emptyRenameInsts(tid);
443}
444
445template<class Impl>
446void
447DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
448{
449 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
450 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
451
452 toCommit->squash[tid] = true;
453 toCommit->squashedSeqNum[tid] = inst->seqNum;
454 toCommit->mispredPC[tid] = inst->readPC();
455 toCommit->nextPC[tid] = inst->readNextPC();
456 toCommit->branchMispredict[tid] = true;
457 toCommit->branchTaken[tid] = inst->readNextPC() !=
458 (inst->readPC() + sizeof(TheISA::MachInst));
459
460 toCommit->includeSquashInst[tid] = false;
461
462 wroteToTimeBuffer = true;
463}
464
465template<class Impl>
466void
467DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
468{
469 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
470 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
471
472 toCommit->squash[tid] = true;
473 toCommit->squashedSeqNum[tid] = inst->seqNum;
474 toCommit->nextPC[tid] = inst->readNextPC();
475
476 toCommit->includeSquashInst[tid] = false;
477
478 wroteToTimeBuffer = true;
479}
480
481template<class Impl>
482void
483DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
484{
485 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
486 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
487
488 toCommit->squash[tid] = true;
489 toCommit->squashedSeqNum[tid] = inst->seqNum;
490 toCommit->nextPC[tid] = inst->readPC();
491
492 // Must include the broadcasted SN in the squash.
493 toCommit->includeSquashInst[tid] = true;
494
495 ldstQueue.setLoadBlockedHandled(tid);
496
497 wroteToTimeBuffer = true;
498}
499
500template<class Impl>
501void
502DefaultIEW<Impl>::block(unsigned tid)
503{
504 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
505
506 if (dispatchStatus[tid] != Blocked &&
507 dispatchStatus[tid] != Unblocking) {
508 toRename->iewBlock[tid] = true;
509 wroteToTimeBuffer = true;
510 }
511
512 // Add the current inputs to the skid buffer so they can be
513 // reprocessed when this stage unblocks.
514 skidInsert(tid);
515
516 dispatchStatus[tid] = Blocked;
517}
518
519template<class Impl>
520void
521DefaultIEW<Impl>::unblock(unsigned tid)
522{
523 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
524 "buffer %u.\n",tid, tid);
525
526 // If the skid bufffer is empty, signal back to previous stages to unblock.
527 // Also switch status to running.
528 if (skidBuffer[tid].empty()) {
529 toRename->iewUnblock[tid] = true;
530 wroteToTimeBuffer = true;
531 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
532 dispatchStatus[tid] = Running;
533 }
534}
535
536template<class Impl>
537void
538DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
539{
540 instQueue.wakeDependents(inst);
541}
542
543template<class Impl>
544void
545DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
546{
547 instQueue.rescheduleMemInst(inst);
548}
549
550template<class Impl>
551void
552DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
553{
554 instQueue.replayMemInst(inst);
555}
556
557template<class Impl>
558void
559DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
560{
561 // First check the time slot that this instruction will write
562 // to. If there are free write ports at the time, then go ahead
563 // and write the instruction to that time. If there are not,
564 // keep looking back to see where's the first time there's a
565 // free slot.
566 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
567 ++wbNumInst;
568 if (wbNumInst == wbWidth) {
569 ++wbCycle;
570 wbNumInst = 0;
571 }
572
573 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
574 }
575
576 // Add finished instruction to queue to commit.
577 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
578 (*iewQueue)[wbCycle].size++;
579}
580
581template <class Impl>
582unsigned
583DefaultIEW<Impl>::validInstsFromRename()
584{
585 unsigned inst_count = 0;
586
587 for (int i=0; i<fromRename->size; i++) {
588 if (!fromRename->insts[i]->isSquashed())
589 inst_count++;
590 }
591
592 return inst_count;
593}
594
595template<class Impl>
596void
597DefaultIEW<Impl>::skidInsert(unsigned tid)
598{
599 DynInstPtr inst = NULL;
600
601 while (!insts[tid].empty()) {
602 inst = insts[tid].front();
603
604 insts[tid].pop();
605
606 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
607 "dispatch skidBuffer %i\n",tid, inst->seqNum,
608 inst->readPC(),tid);
609
610 skidBuffer[tid].push(inst);
611 }
612
613 assert(skidBuffer[tid].size() <= skidBufferMax &&
614 "Skidbuffer Exceeded Max Size");
615}
616
617template<class Impl>
618int
619DefaultIEW<Impl>::skidCount()
620{
621 int max=0;
622
623 list<unsigned>::iterator threads = (*activeThreads).begin();
624
625 while (threads != (*activeThreads).end()) {
626 unsigned thread_count = skidBuffer[*threads++].size();
627 if (max < thread_count)
628 max = thread_count;
629 }
630
631 return max;
632}
633
634template<class Impl>
635bool
636DefaultIEW<Impl>::skidsEmpty()
637{
638 list<unsigned>::iterator threads = (*activeThreads).begin();
639
640 while (threads != (*activeThreads).end()) {
641 if (!skidBuffer[*threads++].empty())
642 return false;
643 }
644
645 return true;
646}
647
648template <class Impl>
649void
650DefaultIEW<Impl>::updateStatus()
651{
652 bool any_unblocking = false;
653
654 list<unsigned>::iterator threads = (*activeThreads).begin();
655
656 threads = (*activeThreads).begin();
657
658 while (threads != (*activeThreads).end()) {
659 unsigned tid = *threads++;
660
661 if (dispatchStatus[tid] == Unblocking) {
662 any_unblocking = true;
663 break;
664 }
665 }
666
667 // If there are no ready instructions waiting to be scheduled by the IQ,
668 // and there's no stores waiting to write back, and dispatch is not
669 // unblocking, then there is no internal activity for the IEW stage.
670 if (_status == Active && !instQueue.hasReadyInsts() &&
671 !ldstQueue.willWB() && !any_unblocking) {
672 DPRINTF(IEW, "IEW switching to idle\n");
673
674 deactivateStage();
675
676 _status = Inactive;
677 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
678 ldstQueue.willWB() ||
679 any_unblocking)) {
680 // Otherwise there is internal activity. Set to active.
681 DPRINTF(IEW, "IEW switching to active\n");
682
683 activateStage();
684
685 _status = Active;
686 }
687}
688
689template <class Impl>
690void
691DefaultIEW<Impl>::resetEntries()
692{
693 instQueue.resetEntries();
694 ldstQueue.resetEntries();
695}
696
697template <class Impl>
698void
699DefaultIEW<Impl>::readStallSignals(unsigned tid)
700{
701 if (fromCommit->commitBlock[tid]) {
702 stalls[tid].commit = true;
703 }
704
705 if (fromCommit->commitUnblock[tid]) {
706 assert(stalls[tid].commit);
707 stalls[tid].commit = false;
708 }
709}
710
711template <class Impl>
712bool
713DefaultIEW<Impl>::checkStall(unsigned tid)
714{
715 bool ret_val(false);
716
717 if (stalls[tid].commit) {
718 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
719 ret_val = true;
720 } else if (instQueue.isFull(tid)) {
721 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
722 ret_val = true;
723 } else if (ldstQueue.isFull(tid)) {
724 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
725
726 if (ldstQueue.numLoads(tid) > 0 ) {
727
728 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
729 tid,ldstQueue.getLoadHeadSeqNum(tid));
730 }
731
732 if (ldstQueue.numStores(tid) > 0) {
733
734 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
735 tid,ldstQueue.getStoreHeadSeqNum(tid));
736 }
737
738 ret_val = true;
739 } else if (ldstQueue.isStalled(tid)) {
740 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
741 ret_val = true;
742 }
743
744 return ret_val;
745}
746
747template <class Impl>
748void
749DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
750{
751 // Check if there's a squash signal, squash if there is
752 // Check stall signals, block if there is.
753 // If status was Blocked
754 // if so then go to unblocking
755 // If status was Squashing
756 // check if squashing is not high. Switch to running this cycle.
757
758 readStallSignals(tid);
759
760 if (fromCommit->commitInfo[tid].squash) {
761 squash(tid);
762
763 if (dispatchStatus[tid] == Blocked ||
764 dispatchStatus[tid] == Unblocking) {
765 toRename->iewUnblock[tid] = true;
766 wroteToTimeBuffer = true;
767 }
768
769 dispatchStatus[tid] = Squashing;
770
771 fetchRedirect[tid] = false;
772 return;
773 }
774
775 if (fromCommit->commitInfo[tid].robSquashing) {
776 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
777
778 dispatchStatus[tid] = Squashing;
779
780 emptyRenameInsts(tid);
781 wroteToTimeBuffer = true;
782 return;
783 }
784
785 if (checkStall(tid)) {
786 block(tid);
787 dispatchStatus[tid] = Blocked;
788 return;
789 }
790
791 if (dispatchStatus[tid] == Blocked) {
792 // Status from previous cycle was blocked, but there are no more stall
793 // conditions. Switch over to unblocking.
794 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
795 tid);
796
797 dispatchStatus[tid] = Unblocking;
798
799 unblock(tid);
800
801 return;
802 }
803
804 if (dispatchStatus[tid] == Squashing) {
805 // Switch status to running if rename isn't being told to block or
806 // squash this cycle.
807 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
808 tid);
809
810 dispatchStatus[tid] = Running;
811
812 return;
813 }
814}
815
816template <class Impl>
817void
818DefaultIEW<Impl>::sortInsts()
819{
820 int insts_from_rename = fromRename->size;
821#ifdef DEBUG
822 for (int i = 0; i < numThreads; i++)
823 assert(insts[i].empty());
824#endif
825 for (int i = 0; i < insts_from_rename; ++i) {
826 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
827 }
828}
829
830template <class Impl>
831void
832DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
833{
834 while (!insts[tid].empty()) {
835 if (insts[tid].front()->isLoad() ||
836 insts[tid].front()->isStore() ) {
837 toRename->iewInfo[tid].dispatchedToLSQ++;
838 }
839
840 toRename->iewInfo[tid].dispatched++;
841
842 insts[tid].pop();
843 }
844}
845
846template <class Impl>
847void
848DefaultIEW<Impl>::wakeCPU()
849{
850 cpu->wakeCPU();
851}
852
853template <class Impl>
854void
855DefaultIEW<Impl>::activityThisCycle()
856{
857 DPRINTF(Activity, "Activity this cycle.\n");
858 cpu->activityThisCycle();
859}
860
861template <class Impl>
862inline void
863DefaultIEW<Impl>::activateStage()
864{
865 DPRINTF(Activity, "Activating stage.\n");
866 cpu->activateStage(O3CPU::IEWIdx);
867}
868
869template <class Impl>
870inline void
871DefaultIEW<Impl>::deactivateStage()
872{
873 DPRINTF(Activity, "Deactivating stage.\n");
874 cpu->deactivateStage(O3CPU::IEWIdx);
875}
876
877template<class Impl>
878void
879DefaultIEW<Impl>::dispatch(unsigned tid)
880{
881 // If status is Running or idle,
882 // call dispatchInsts()
883 // If status is Unblocking,
884 // buffer any instructions coming from rename
885 // continue trying to empty skid buffer
886 // check if stall conditions have passed
887
888 if (dispatchStatus[tid] == Blocked) {
889 ++iewBlockCycles;
890
891 } else if (dispatchStatus[tid] == Squashing) {
892 ++iewSquashCycles;
893 }
894
895 // Dispatch should try to dispatch as many instructions as its bandwidth
896 // will allow, as long as it is not currently blocked.
897 if (dispatchStatus[tid] == Running ||
898 dispatchStatus[tid] == Idle) {
899 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
900 "dispatch.\n", tid);
901
902 dispatchInsts(tid);
903 } else if (dispatchStatus[tid] == Unblocking) {
904 // Make sure that the skid buffer has something in it if the
905 // status is unblocking.
906 assert(!skidsEmpty());
907
908 // If the status was unblocking, then instructions from the skid
909 // buffer were used. Remove those instructions and handle
910 // the rest of unblocking.
911 dispatchInsts(tid);
912
913 ++iewUnblockCycles;
914
915 if (validInstsFromRename() && dispatchedAllInsts) {
916 // Add the current inputs to the skid buffer so they can be
917 // reprocessed when this stage unblocks.
918 skidInsert(tid);
919 }
920
921 unblock(tid);
922 }
923}
924
925template <class Impl>
926void
927DefaultIEW<Impl>::dispatchInsts(unsigned tid)
928{
929 dispatchedAllInsts = true;
930
931 // Obtain instructions from skid buffer if unblocking, or queue from rename
932 // otherwise.
933 std::queue<DynInstPtr> &insts_to_dispatch =
934 dispatchStatus[tid] == Unblocking ?
935 skidBuffer[tid] : insts[tid];
936
937 int insts_to_add = insts_to_dispatch.size();
938
939 DynInstPtr inst;
940 bool add_to_iq = false;
941 int dis_num_inst = 0;
942
943 // Loop through the instructions, putting them in the instruction
944 // queue.
945 for ( ; dis_num_inst < insts_to_add &&
946 dis_num_inst < dispatchWidth;
947 ++dis_num_inst)
948 {
949 inst = insts_to_dispatch.front();
950
951 if (dispatchStatus[tid] == Unblocking) {
952 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
953 "buffer\n", tid);
954 }
955
956 // Make sure there's a valid instruction there.
957 assert(inst);
958
959 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
960 "IQ.\n",
961 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
962
963 // Be sure to mark these instructions as ready so that the
964 // commit stage can go ahead and execute them, and mark
965 // them as issued so the IQ doesn't reprocess them.
966
967 // Check for squashed instructions.
968 if (inst->isSquashed()) {
969 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
970 "not adding to IQ.\n", tid);
971
972 ++iewDispSquashedInsts;
973
974 insts_to_dispatch.pop();
975
976 //Tell Rename That An Instruction has been processed
977 if (inst->isLoad() || inst->isStore()) {
978 toRename->iewInfo[tid].dispatchedToLSQ++;
979 }
980 toRename->iewInfo[tid].dispatched++;
981
982 continue;
983 }
984
985 // Check for full conditions.
986 if (instQueue.isFull(tid)) {
987 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
988
989 // Call function to start blocking.
990 block(tid);
991
992 // Set unblock to false. Special case where we are using
993 // skidbuffer (unblocking) instructions but then we still
994 // get full in the IQ.
995 toRename->iewUnblock[tid] = false;
996
997 dispatchedAllInsts = false;
998
999 ++iewIQFullEvents;
1000 break;
1001 } else if (ldstQueue.isFull(tid)) {
1002 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1003
1004 // Call function to start blocking.
1005 block(tid);
1006
1007 // Set unblock to false. Special case where we are using
1008 // skidbuffer (unblocking) instructions but then we still
1009 // get full in the IQ.
1010 toRename->iewUnblock[tid] = false;
1011
1012 dispatchedAllInsts = false;
1013
1014 ++iewLSQFullEvents;
1015 break;
1016 }
1017
1018 // Otherwise issue the instruction just fine.
1019 if (inst->isLoad()) {
1020 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1021 "encountered, adding to LSQ.\n", tid);
1022
1023 // Reserve a spot in the load store queue for this
1024 // memory access.
1025 ldstQueue.insertLoad(inst);
1026
1027 ++iewDispLoadInsts;
1028
1029 add_to_iq = true;
1030
1031 toRename->iewInfo[tid].dispatchedToLSQ++;
1032 } else if (inst->isStore()) {
1033 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1034 "encountered, adding to LSQ.\n", tid);
1035
1036 ldstQueue.insertStore(inst);
1037
1038 ++iewDispStoreInsts;
1039
1040 if (inst->isStoreConditional()) {
1041 // Store conditionals need to be set as "canCommit()"
1042 // so that commit can process them when they reach the
1043 // head of commit.
1044 // @todo: This is somewhat specific to Alpha.
1045 inst->setCanCommit();
1046 instQueue.insertNonSpec(inst);
1047 add_to_iq = false;
1048
1049 ++iewDispNonSpecInsts;
1050 } else {
1051 add_to_iq = true;
1052 }
1053
1054 toRename->iewInfo[tid].dispatchedToLSQ++;
1055#if FULL_SYSTEM
1056 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1057 // Same as non-speculative stores.
1058 inst->setCanCommit();
1059 instQueue.insertBarrier(inst);
1060 add_to_iq = false;
1061#endif
1062 } else if (inst->isNonSpeculative()) {
1063 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1064 "encountered, skipping.\n", tid);
1065
1066 // Same as non-speculative stores.
1067 inst->setCanCommit();
1068
1069 // Specifically insert it as nonspeculative.
1070 instQueue.insertNonSpec(inst);
1071
1072 ++iewDispNonSpecInsts;
1073
1074 add_to_iq = false;
1075 } else if (inst->isNop()) {
1076 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1077 "skipping.\n", tid);
1078
1079 inst->setIssued();
1080 inst->setExecuted();
1081 inst->setCanCommit();
1082
1083 instQueue.recordProducer(inst);
1084
1085 iewExecutedNop[tid]++;
1086
1087 add_to_iq = false;
1088 } else if (inst->isExecuted()) {
1089 assert(0 && "Instruction shouldn't be executed.\n");
1090 DPRINTF(IEW, "Issue: Executed branch encountered, "
1091 "skipping.\n");
1092
1093 inst->setIssued();
1094 inst->setCanCommit();
1095
1096 instQueue.recordProducer(inst);
1097
1098 add_to_iq = false;
1099 } else {
1100 add_to_iq = true;
1101 }
1102
1103 // If the instruction queue is not full, then add the
1104 // instruction.
1105 if (add_to_iq) {
1106 instQueue.insert(inst);
1107 }
1108
1109 insts_to_dispatch.pop();
1110
1111 toRename->iewInfo[tid].dispatched++;
1112
1113 ++iewDispatchedInsts;
1114 }
1115
1116 if (!insts_to_dispatch.empty()) {
1117 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1118 block(tid);
1119 toRename->iewUnblock[tid] = false;
1120 }
1121
1122 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1123 dispatchStatus[tid] = Running;
1124
1125 updatedQueues = true;
1126 }
1127
1128 dis_num_inst = 0;
1129}
1130
1131template <class Impl>
1132void
1133DefaultIEW<Impl>::printAvailableInsts()
1134{
1135 int inst = 0;
1136
1137 cout << "Available Instructions: ";
1138
1139 while (fromIssue->insts[inst]) {
1140
1141 if (inst%3==0) cout << "\n\t";
1142
1143 cout << "PC: " << fromIssue->insts[inst]->readPC()
1144 << " TN: " << fromIssue->insts[inst]->threadNumber
1145 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1146
1147 inst++;
1148
1149 }
1150
1151 cout << "\n";
1152}
1153
1154template <class Impl>
1155void
1156DefaultIEW<Impl>::executeInsts()
1157{
1158 wbNumInst = 0;
1159 wbCycle = 0;
1160
1161 list<unsigned>::iterator threads = (*activeThreads).begin();
1162
1163 while (threads != (*activeThreads).end()) {
1164 unsigned tid = *threads++;
1165 fetchRedirect[tid] = false;
1166 }
1167
1168 // Uncomment this if you want to see all available instructions.
1169// printAvailableInsts();
1170
1171 // Execute/writeback any instructions that are available.
1172 int insts_to_execute = fromIssue->size;
1173 int inst_num = 0;
1174 for (; inst_num < insts_to_execute;
1175 ++inst_num) {
1176
1177 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1178
1179 DynInstPtr inst = instQueue.getInstToExecute();
1180
1181 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1182 inst->readPC(), inst->threadNumber,inst->seqNum);
1183
1184 // Check if the instruction is squashed; if so then skip it
1185 if (inst->isSquashed()) {
1186 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1187
1188 // Consider this instruction executed so that commit can go
1189 // ahead and retire the instruction.
1190 inst->setExecuted();
1191
1192 // Not sure if I should set this here or just let commit try to
1193 // commit any squashed instructions. I like the latter a bit more.
1194 inst->setCanCommit();
1195
1196 ++iewExecSquashedInsts;
1197
1198 decrWb(inst->seqNum);
1199 continue;
1200 }
1201
1202 Fault fault = NoFault;
1203
1204 // Execute instruction.
1205 // Note that if the instruction faults, it will be handled
1206 // at the commit stage.
1207 if (inst->isMemRef() &&
1208 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1209 DPRINTF(IEW, "Execute: Calculating address for memory "
1210 "reference.\n");
1211
1212 // Tell the LDSTQ to execute this instruction (if it is a load).
1213 if (inst->isLoad()) {
1214 // Loads will mark themselves as executed, and their writeback
1215 // event adds the instruction to the queue to commit
1216 fault = ldstQueue.executeLoad(inst);
1217 } else if (inst->isStore()) {
1218 ldstQueue.executeStore(inst);
1219
1220 // If the store had a fault then it may not have a mem req
1221 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1222 inst->setExecuted();
1223
1224 instToCommit(inst);
1225 }
1226
1227 // Store conditionals will mark themselves as
1228 // executed, and their writeback event will add the
1229 // instruction to the queue to commit.
1230 } else {
1231 panic("Unexpected memory type!\n");
1232 }
1233
1234 } else {
1235 inst->execute();
1236
1237 inst->setExecuted();
1238
1239 instToCommit(inst);
1240 }
1241
1242 updateExeInstStats(inst);
1243
1244 // Check if branch prediction was correct, if not then we need
1245 // to tell commit to squash in flight instructions. Only
1246 // handle this if there hasn't already been something that
1247 // redirects fetch in this group of instructions.
1248
1249 // This probably needs to prioritize the redirects if a different
1250 // scheduler is used. Currently the scheduler schedules the oldest
1251 // instruction first, so the branch resolution order will be correct.
1252 unsigned tid = inst->threadNumber;
1253
1254 if (!fetchRedirect[tid]) {
1255
1256 if (inst->mispredicted()) {
1257 fetchRedirect[tid] = true;
1258
1259 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1260 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1261 inst->nextPC);
1262
1263 // If incorrect, then signal the ROB that it must be squashed.
1264 squashDueToBranch(inst, tid);
1265
1266 if (inst->predTaken()) {
1267 predictedTakenIncorrect++;
1268 } else {
1269 predictedNotTakenIncorrect++;
1270 }
1271 } else if (ldstQueue.violation(tid)) {
1272 fetchRedirect[tid] = true;
1273
1274 // If there was an ordering violation, then get the
1275 // DynInst that caused the violation. Note that this
1276 // clears the violation signal.
1277 DynInstPtr violator;
1278 violator = ldstQueue.getMemDepViolator(tid);
1279
1280 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1281 "%#x, inst PC: %#x. Addr is: %#x.\n",
1282 violator->readPC(), inst->readPC(), inst->physEffAddr);
1283
1284 // Tell the instruction queue that a violation has occured.
1285 instQueue.violation(inst, violator);
1286
1287 // Squash.
1288 squashDueToMemOrder(inst,tid);
1289
1290 ++memOrderViolationEvents;
1291 } else if (ldstQueue.loadBlocked(tid) &&
1292 !ldstQueue.isLoadBlockedHandled(tid)) {
1293 fetchRedirect[tid] = true;
1294
1295 DPRINTF(IEW, "Load operation couldn't execute because the "
1296 "memory system is blocked. PC: %#x [sn:%lli]\n",
1297 inst->readPC(), inst->seqNum);
1298
1299 squashDueToMemBlocked(inst, tid);
1300 }
1301 }
1302 }
1303
1304 // Update and record activity if we processed any instructions.
1305 if (inst_num) {
1306 if (exeStatus == Idle) {
1307 exeStatus = Running;
1308 }
1309
1310 updatedQueues = true;
1311
1312 cpu->activityThisCycle();
1313 }
1314
1315 // Need to reset this in case a writeback event needs to write into the
1316 // iew queue. That way the writeback event will write into the correct
1317 // spot in the queue.
1318 wbNumInst = 0;
1319}
1320
1321template <class Impl>
1322void
1323DefaultIEW<Impl>::writebackInsts()
1324{
1325 // Loop through the head of the time buffer and wake any
1326 // dependents. These instructions are about to write back. Also
1327 // mark scoreboard that this instruction is finally complete.
1328 // Either have IEW have direct access to scoreboard, or have this
1329 // as part of backwards communication.
1330 for (int inst_num = 0; inst_num < issueWidth &&
1331 toCommit->insts[inst_num]; inst_num++) {
1332 DynInstPtr inst = toCommit->insts[inst_num];
1333 int tid = inst->threadNumber;
1334
1335 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1336 inst->seqNum, inst->readPC());
1337
1338 iewInstsToCommit[tid]++;
1339
1340 // Some instructions will be sent to commit without having
1341 // executed because they need commit to handle them.
1342 // E.g. Uncached loads have not actually executed when they
1343 // are first sent to commit. Instead commit must tell the LSQ
1344 // when it's ready to execute the uncached load.
1345 if (!inst->isSquashed() && inst->isExecuted()) {
1346 int dependents = instQueue.wakeDependents(inst);
1347
1348 for (int i = 0; i < inst->numDestRegs(); i++) {
1349 //mark as Ready
1350 DPRINTF(IEW,"Setting Destination Register %i\n",
1351 inst->renamedDestRegIdx(i));
1352 scoreboard->setReg(inst->renamedDestRegIdx(i));
1353 }
1354
1355 if (dependents) {
1356 producerInst[tid]++;
1357 consumerInst[tid]+= dependents;
1358 }
1359 writebackCount[tid]++;
1360 }
1361
1362 decrWb(inst->seqNum);
1363 }
1364}
1365
1366template<class Impl>
1367void
1368DefaultIEW<Impl>::tick()
1369{
1370 wbNumInst = 0;
1371 wbCycle = 0;
1372
1373 wroteToTimeBuffer = false;
1374 updatedQueues = false;
1375
1376 sortInsts();
1377
1378 // Free function units marked as being freed this cycle.
1379 fuPool->processFreeUnits();
1380
1381 list<unsigned>::iterator threads = (*activeThreads).begin();
1382
1383 // Check stall and squash signals, dispatch any instructions.
1384 while (threads != (*activeThreads).end()) {
1385 unsigned tid = *threads++;
1386
1387 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1388
1389 checkSignalsAndUpdate(tid);
1390 dispatch(tid);
1391 }
1392
1393 if (exeStatus != Squashing) {
1394 executeInsts();
1395
1396 writebackInsts();
1397
1398 // Have the instruction queue try to schedule any ready instructions.
1399 // (In actuality, this scheduling is for instructions that will
1400 // be executed next cycle.)
1401 instQueue.scheduleReadyInsts();
1402
1403 // Also should advance its own time buffers if the stage ran.
1404 // Not the best place for it, but this works (hopefully).
1405 issueToExecQueue.advance();
1406 }
1407
1408 bool broadcast_free_entries = false;
1409
1410 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1411 exeStatus = Idle;
1412 updateLSQNextCycle = false;
1413
1414 broadcast_free_entries = true;
1415 }
1416
1417 // Writeback any stores using any leftover bandwidth.
1418 ldstQueue.writebackStores();
1419
1420 // Check the committed load/store signals to see if there's a load
1421 // or store to commit. Also check if it's being told to execute a
1422 // nonspeculative instruction.
1423 // This is pretty inefficient...
1424
1425 threads = (*activeThreads).begin();
1426 while (threads != (*activeThreads).end()) {
1427 unsigned tid = (*threads++);
1428
1429 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1430
1431 // Update structures based on instructions committed.
1432 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1433 !fromCommit->commitInfo[tid].squash &&
1434 !fromCommit->commitInfo[tid].robSquashing) {
1435
1436 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1437
1438 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1439
1440 updateLSQNextCycle = true;
1441 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1442 }
1443
1444 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1445
1446 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1447 if (fromCommit->commitInfo[tid].uncached) {
1448 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1449 } else {
1450 instQueue.scheduleNonSpec(
1451 fromCommit->commitInfo[tid].nonSpecSeqNum);
1452 }
1453 }
1454
1455 if (broadcast_free_entries) {
1456 toFetch->iewInfo[tid].iqCount =
1457 instQueue.getCount(tid);
1458 toFetch->iewInfo[tid].ldstqCount =
1459 ldstQueue.getCount(tid);
1460
1461 toRename->iewInfo[tid].usedIQ = true;
1462 toRename->iewInfo[tid].freeIQEntries =
1463 instQueue.numFreeEntries();
1464 toRename->iewInfo[tid].usedLSQ = true;
1465 toRename->iewInfo[tid].freeLSQEntries =
1466 ldstQueue.numFreeEntries(tid);
1467
1468 wroteToTimeBuffer = true;
1469 }
1470
1471 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1472 tid, toRename->iewInfo[tid].dispatched);
1473 }
1474
1475 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1476 "LSQ has %i free entries.\n",
1477 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1478 ldstQueue.numFreeEntries());
1479
1480 updateStatus();
1481
1482 if (wroteToTimeBuffer) {
1483 DPRINTF(Activity, "Activity this cycle.\n");
1484 cpu->activityThisCycle();
1485 }
1486}
1487
1488template <class Impl>
1489void
1490DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1491{
1492 int thread_number = inst->threadNumber;
1493
1494 //
1495 // Pick off the software prefetches
1496 //
1497#ifdef TARGET_ALPHA
1498 if (inst->isDataPrefetch())
1499 iewExecutedSwp[thread_number]++;
1500 else
1501 iewIewExecutedcutedInsts++;
1502#else
1503 iewExecutedInsts++;
1504#endif
1505
1506 //
1507 // Control operations
1508 //
1509 if (inst->isControl())
1510 iewExecutedBranches[thread_number]++;
1511
1512 //
1513 // Memory operations
1514 //
1515 if (inst->isMemRef()) {
1516 iewExecutedRefs[thread_number]++;
1517
1518 if (inst->isLoad()) {
1519 iewExecLoadInsts[thread_number]++;
1520 }
1521 }
1522}
| 374 // Clear any state.
375 switchedOut = true;
376
377 instQueue.switchOut();
378 ldstQueue.switchOut();
379 fuPool->switchOut();
380
381 for (int i = 0; i < numThreads; i++) {
382 while (!insts[i].empty())
383 insts[i].pop();
384 while (!skidBuffer[i].empty())
385 skidBuffer[i].pop();
386 }
387}
388
389template <class Impl>
390void
391DefaultIEW<Impl>::takeOverFrom()
392{
393 // Reset all state.
394 _status = Active;
395 exeStatus = Running;
396 wbStatus = Idle;
397 switchedOut = false;
398
399 instQueue.takeOverFrom();
400 ldstQueue.takeOverFrom();
401 fuPool->takeOverFrom();
402
403 initStage();
404 cpu->activityThisCycle();
405
406 for (int i=0; i < numThreads; i++) {
407 dispatchStatus[i] = Running;
408 stalls[i].commit = false;
409 fetchRedirect[i] = false;
410 }
411
412 updateLSQNextCycle = false;
413
414 // @todo: Fix hardcoded number
415 for (int i = 0; i < 6; ++i) {
416 issueToExecQueue.advance();
417 }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432
433 updatedQueues = true;
434
435 // Clear the skid buffer in case it has any data in it.
436 while (!skidBuffer[tid].empty()) {
437
438 if (skidBuffer[tid].front()->isLoad() ||
439 skidBuffer[tid].front()->isStore() ) {
440 toRename->iewInfo[tid].dispatchedToLSQ++;
441 }
442
443 toRename->iewInfo[tid].dispatched++;
444
445 skidBuffer[tid].pop();
446 }
447
448 emptyRenameInsts(tid);
449}
450
451template<class Impl>
452void
453DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
454{
455 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
456 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
457
458 toCommit->squash[tid] = true;
459 toCommit->squashedSeqNum[tid] = inst->seqNum;
460 toCommit->mispredPC[tid] = inst->readPC();
461 toCommit->nextPC[tid] = inst->readNextPC();
462 toCommit->branchMispredict[tid] = true;
463 toCommit->branchTaken[tid] = inst->readNextPC() !=
464 (inst->readPC() + sizeof(TheISA::MachInst));
465
466 toCommit->includeSquashInst[tid] = false;
467
468 wroteToTimeBuffer = true;
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
476 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->nextPC[tid] = inst->readNextPC();
481
482 toCommit->includeSquashInst[tid] = false;
483
484 wroteToTimeBuffer = true;
485}
486
487template<class Impl>
488void
489DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
490{
491 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
492 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
493
494 toCommit->squash[tid] = true;
495 toCommit->squashedSeqNum[tid] = inst->seqNum;
496 toCommit->nextPC[tid] = inst->readPC();
497
498 // Must include the broadcasted SN in the squash.
499 toCommit->includeSquashInst[tid] = true;
500
501 ldstQueue.setLoadBlockedHandled(tid);
502
503 wroteToTimeBuffer = true;
504}
505
506template<class Impl>
507void
508DefaultIEW<Impl>::block(unsigned tid)
509{
510 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
511
512 if (dispatchStatus[tid] != Blocked &&
513 dispatchStatus[tid] != Unblocking) {
514 toRename->iewBlock[tid] = true;
515 wroteToTimeBuffer = true;
516 }
517
518 // Add the current inputs to the skid buffer so they can be
519 // reprocessed when this stage unblocks.
520 skidInsert(tid);
521
522 dispatchStatus[tid] = Blocked;
523}
524
525template<class Impl>
526void
527DefaultIEW<Impl>::unblock(unsigned tid)
528{
529 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
530 "buffer %u.\n",tid, tid);
531
532 // If the skid bufffer is empty, signal back to previous stages to unblock.
533 // Also switch status to running.
534 if (skidBuffer[tid].empty()) {
535 toRename->iewUnblock[tid] = true;
536 wroteToTimeBuffer = true;
537 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
538 dispatchStatus[tid] = Running;
539 }
540}
541
542template<class Impl>
543void
544DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
545{
546 instQueue.wakeDependents(inst);
547}
548
549template<class Impl>
550void
551DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
552{
553 instQueue.rescheduleMemInst(inst);
554}
555
556template<class Impl>
557void
558DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
559{
560 instQueue.replayMemInst(inst);
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
566{
567 // First check the time slot that this instruction will write
568 // to. If there are free write ports at the time, then go ahead
569 // and write the instruction to that time. If there are not,
570 // keep looking back to see where's the first time there's a
571 // free slot.
572 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
573 ++wbNumInst;
574 if (wbNumInst == wbWidth) {
575 ++wbCycle;
576 wbNumInst = 0;
577 }
578
579 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
580 }
581
582 // Add finished instruction to queue to commit.
583 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
584 (*iewQueue)[wbCycle].size++;
585}
586
587template <class Impl>
588unsigned
589DefaultIEW<Impl>::validInstsFromRename()
590{
591 unsigned inst_count = 0;
592
593 for (int i=0; i<fromRename->size; i++) {
594 if (!fromRename->insts[i]->isSquashed())
595 inst_count++;
596 }
597
598 return inst_count;
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::skidInsert(unsigned tid)
604{
605 DynInstPtr inst = NULL;
606
607 while (!insts[tid].empty()) {
608 inst = insts[tid].front();
609
610 insts[tid].pop();
611
612 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
613 "dispatch skidBuffer %i\n",tid, inst->seqNum,
614 inst->readPC(),tid);
615
616 skidBuffer[tid].push(inst);
617 }
618
619 assert(skidBuffer[tid].size() <= skidBufferMax &&
620 "Skidbuffer Exceeded Max Size");
621}
622
623template<class Impl>
624int
625DefaultIEW<Impl>::skidCount()
626{
627 int max=0;
628
629 list<unsigned>::iterator threads = (*activeThreads).begin();
630
631 while (threads != (*activeThreads).end()) {
632 unsigned thread_count = skidBuffer[*threads++].size();
633 if (max < thread_count)
634 max = thread_count;
635 }
636
637 return max;
638}
639
640template<class Impl>
641bool
642DefaultIEW<Impl>::skidsEmpty()
643{
644 list<unsigned>::iterator threads = (*activeThreads).begin();
645
646 while (threads != (*activeThreads).end()) {
647 if (!skidBuffer[*threads++].empty())
648 return false;
649 }
650
651 return true;
652}
653
654template <class Impl>
655void
656DefaultIEW<Impl>::updateStatus()
657{
658 bool any_unblocking = false;
659
660 list<unsigned>::iterator threads = (*activeThreads).begin();
661
662 threads = (*activeThreads).begin();
663
664 while (threads != (*activeThreads).end()) {
665 unsigned tid = *threads++;
666
667 if (dispatchStatus[tid] == Unblocking) {
668 any_unblocking = true;
669 break;
670 }
671 }
672
673 // If there are no ready instructions waiting to be scheduled by the IQ,
674 // and there's no stores waiting to write back, and dispatch is not
675 // unblocking, then there is no internal activity for the IEW stage.
676 if (_status == Active && !instQueue.hasReadyInsts() &&
677 !ldstQueue.willWB() && !any_unblocking) {
678 DPRINTF(IEW, "IEW switching to idle\n");
679
680 deactivateStage();
681
682 _status = Inactive;
683 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
684 ldstQueue.willWB() ||
685 any_unblocking)) {
686 // Otherwise there is internal activity. Set to active.
687 DPRINTF(IEW, "IEW switching to active\n");
688
689 activateStage();
690
691 _status = Active;
692 }
693}
694
695template <class Impl>
696void
697DefaultIEW<Impl>::resetEntries()
698{
699 instQueue.resetEntries();
700 ldstQueue.resetEntries();
701}
702
703template <class Impl>
704void
705DefaultIEW<Impl>::readStallSignals(unsigned tid)
706{
707 if (fromCommit->commitBlock[tid]) {
708 stalls[tid].commit = true;
709 }
710
711 if (fromCommit->commitUnblock[tid]) {
712 assert(stalls[tid].commit);
713 stalls[tid].commit = false;
714 }
715}
716
717template <class Impl>
718bool
719DefaultIEW<Impl>::checkStall(unsigned tid)
720{
721 bool ret_val(false);
722
723 if (stalls[tid].commit) {
724 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
725 ret_val = true;
726 } else if (instQueue.isFull(tid)) {
727 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
728 ret_val = true;
729 } else if (ldstQueue.isFull(tid)) {
730 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
731
732 if (ldstQueue.numLoads(tid) > 0 ) {
733
734 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
735 tid,ldstQueue.getLoadHeadSeqNum(tid));
736 }
737
738 if (ldstQueue.numStores(tid) > 0) {
739
740 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
741 tid,ldstQueue.getStoreHeadSeqNum(tid));
742 }
743
744 ret_val = true;
745 } else if (ldstQueue.isStalled(tid)) {
746 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
747 ret_val = true;
748 }
749
750 return ret_val;
751}
752
753template <class Impl>
754void
755DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
756{
757 // Check if there's a squash signal, squash if there is
758 // Check stall signals, block if there is.
759 // If status was Blocked
760 // if so then go to unblocking
761 // If status was Squashing
762 // check if squashing is not high. Switch to running this cycle.
763
764 readStallSignals(tid);
765
766 if (fromCommit->commitInfo[tid].squash) {
767 squash(tid);
768
769 if (dispatchStatus[tid] == Blocked ||
770 dispatchStatus[tid] == Unblocking) {
771 toRename->iewUnblock[tid] = true;
772 wroteToTimeBuffer = true;
773 }
774
775 dispatchStatus[tid] = Squashing;
776
777 fetchRedirect[tid] = false;
778 return;
779 }
780
781 if (fromCommit->commitInfo[tid].robSquashing) {
782 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
783
784 dispatchStatus[tid] = Squashing;
785
786 emptyRenameInsts(tid);
787 wroteToTimeBuffer = true;
788 return;
789 }
790
791 if (checkStall(tid)) {
792 block(tid);
793 dispatchStatus[tid] = Blocked;
794 return;
795 }
796
797 if (dispatchStatus[tid] == Blocked) {
798 // Status from previous cycle was blocked, but there are no more stall
799 // conditions. Switch over to unblocking.
800 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
801 tid);
802
803 dispatchStatus[tid] = Unblocking;
804
805 unblock(tid);
806
807 return;
808 }
809
810 if (dispatchStatus[tid] == Squashing) {
811 // Switch status to running if rename isn't being told to block or
812 // squash this cycle.
813 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
814 tid);
815
816 dispatchStatus[tid] = Running;
817
818 return;
819 }
820}
821
822template <class Impl>
823void
824DefaultIEW<Impl>::sortInsts()
825{
826 int insts_from_rename = fromRename->size;
827#ifdef DEBUG
828 for (int i = 0; i < numThreads; i++)
829 assert(insts[i].empty());
830#endif
831 for (int i = 0; i < insts_from_rename; ++i) {
832 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
833 }
834}
835
836template <class Impl>
837void
838DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
839{
840 while (!insts[tid].empty()) {
841 if (insts[tid].front()->isLoad() ||
842 insts[tid].front()->isStore() ) {
843 toRename->iewInfo[tid].dispatchedToLSQ++;
844 }
845
846 toRename->iewInfo[tid].dispatched++;
847
848 insts[tid].pop();
849 }
850}
851
852template <class Impl>
853void
854DefaultIEW<Impl>::wakeCPU()
855{
856 cpu->wakeCPU();
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::activityThisCycle()
862{
863 DPRINTF(Activity, "Activity this cycle.\n");
864 cpu->activityThisCycle();
865}
866
867template <class Impl>
868inline void
869DefaultIEW<Impl>::activateStage()
870{
871 DPRINTF(Activity, "Activating stage.\n");
872 cpu->activateStage(O3CPU::IEWIdx);
873}
874
875template <class Impl>
876inline void
877DefaultIEW<Impl>::deactivateStage()
878{
879 DPRINTF(Activity, "Deactivating stage.\n");
880 cpu->deactivateStage(O3CPU::IEWIdx);
881}
882
883template<class Impl>
884void
885DefaultIEW<Impl>::dispatch(unsigned tid)
886{
887 // If status is Running or idle,
888 // call dispatchInsts()
889 // If status is Unblocking,
890 // buffer any instructions coming from rename
891 // continue trying to empty skid buffer
892 // check if stall conditions have passed
893
894 if (dispatchStatus[tid] == Blocked) {
895 ++iewBlockCycles;
896
897 } else if (dispatchStatus[tid] == Squashing) {
898 ++iewSquashCycles;
899 }
900
901 // Dispatch should try to dispatch as many instructions as its bandwidth
902 // will allow, as long as it is not currently blocked.
903 if (dispatchStatus[tid] == Running ||
904 dispatchStatus[tid] == Idle) {
905 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
906 "dispatch.\n", tid);
907
908 dispatchInsts(tid);
909 } else if (dispatchStatus[tid] == Unblocking) {
910 // Make sure that the skid buffer has something in it if the
911 // status is unblocking.
912 assert(!skidsEmpty());
913
914 // If the status was unblocking, then instructions from the skid
915 // buffer were used. Remove those instructions and handle
916 // the rest of unblocking.
917 dispatchInsts(tid);
918
919 ++iewUnblockCycles;
920
921 if (validInstsFromRename() && dispatchedAllInsts) {
922 // Add the current inputs to the skid buffer so they can be
923 // reprocessed when this stage unblocks.
924 skidInsert(tid);
925 }
926
927 unblock(tid);
928 }
929}
930
931template <class Impl>
932void
933DefaultIEW<Impl>::dispatchInsts(unsigned tid)
934{
935 dispatchedAllInsts = true;
936
937 // Obtain instructions from skid buffer if unblocking, or queue from rename
938 // otherwise.
939 std::queue<DynInstPtr> &insts_to_dispatch =
940 dispatchStatus[tid] == Unblocking ?
941 skidBuffer[tid] : insts[tid];
942
943 int insts_to_add = insts_to_dispatch.size();
944
945 DynInstPtr inst;
946 bool add_to_iq = false;
947 int dis_num_inst = 0;
948
949 // Loop through the instructions, putting them in the instruction
950 // queue.
951 for ( ; dis_num_inst < insts_to_add &&
952 dis_num_inst < dispatchWidth;
953 ++dis_num_inst)
954 {
955 inst = insts_to_dispatch.front();
956
957 if (dispatchStatus[tid] == Unblocking) {
958 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
959 "buffer\n", tid);
960 }
961
962 // Make sure there's a valid instruction there.
963 assert(inst);
964
965 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
966 "IQ.\n",
967 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
968
969 // Be sure to mark these instructions as ready so that the
970 // commit stage can go ahead and execute them, and mark
971 // them as issued so the IQ doesn't reprocess them.
972
973 // Check for squashed instructions.
974 if (inst->isSquashed()) {
975 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
976 "not adding to IQ.\n", tid);
977
978 ++iewDispSquashedInsts;
979
980 insts_to_dispatch.pop();
981
982 //Tell Rename That An Instruction has been processed
983 if (inst->isLoad() || inst->isStore()) {
984 toRename->iewInfo[tid].dispatchedToLSQ++;
985 }
986 toRename->iewInfo[tid].dispatched++;
987
988 continue;
989 }
990
991 // Check for full conditions.
992 if (instQueue.isFull(tid)) {
993 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
994
995 // Call function to start blocking.
996 block(tid);
997
998 // Set unblock to false. Special case where we are using
999 // skidbuffer (unblocking) instructions but then we still
1000 // get full in the IQ.
1001 toRename->iewUnblock[tid] = false;
1002
1003 dispatchedAllInsts = false;
1004
1005 ++iewIQFullEvents;
1006 break;
1007 } else if (ldstQueue.isFull(tid)) {
1008 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1009
1010 // Call function to start blocking.
1011 block(tid);
1012
1013 // Set unblock to false. Special case where we are using
1014 // skidbuffer (unblocking) instructions but then we still
1015 // get full in the IQ.
1016 toRename->iewUnblock[tid] = false;
1017
1018 dispatchedAllInsts = false;
1019
1020 ++iewLSQFullEvents;
1021 break;
1022 }
1023
1024 // Otherwise issue the instruction just fine.
1025 if (inst->isLoad()) {
1026 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1027 "encountered, adding to LSQ.\n", tid);
1028
1029 // Reserve a spot in the load store queue for this
1030 // memory access.
1031 ldstQueue.insertLoad(inst);
1032
1033 ++iewDispLoadInsts;
1034
1035 add_to_iq = true;
1036
1037 toRename->iewInfo[tid].dispatchedToLSQ++;
1038 } else if (inst->isStore()) {
1039 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1040 "encountered, adding to LSQ.\n", tid);
1041
1042 ldstQueue.insertStore(inst);
1043
1044 ++iewDispStoreInsts;
1045
1046 if (inst->isStoreConditional()) {
1047 // Store conditionals need to be set as "canCommit()"
1048 // so that commit can process them when they reach the
1049 // head of commit.
1050 // @todo: This is somewhat specific to Alpha.
1051 inst->setCanCommit();
1052 instQueue.insertNonSpec(inst);
1053 add_to_iq = false;
1054
1055 ++iewDispNonSpecInsts;
1056 } else {
1057 add_to_iq = true;
1058 }
1059
1060 toRename->iewInfo[tid].dispatchedToLSQ++;
1061#if FULL_SYSTEM
1062 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1063 // Same as non-speculative stores.
1064 inst->setCanCommit();
1065 instQueue.insertBarrier(inst);
1066 add_to_iq = false;
1067#endif
1068 } else if (inst->isNonSpeculative()) {
1069 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1070 "encountered, skipping.\n", tid);
1071
1072 // Same as non-speculative stores.
1073 inst->setCanCommit();
1074
1075 // Specifically insert it as nonspeculative.
1076 instQueue.insertNonSpec(inst);
1077
1078 ++iewDispNonSpecInsts;
1079
1080 add_to_iq = false;
1081 } else if (inst->isNop()) {
1082 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1083 "skipping.\n", tid);
1084
1085 inst->setIssued();
1086 inst->setExecuted();
1087 inst->setCanCommit();
1088
1089 instQueue.recordProducer(inst);
1090
1091 iewExecutedNop[tid]++;
1092
1093 add_to_iq = false;
1094 } else if (inst->isExecuted()) {
1095 assert(0 && "Instruction shouldn't be executed.\n");
1096 DPRINTF(IEW, "Issue: Executed branch encountered, "
1097 "skipping.\n");
1098
1099 inst->setIssued();
1100 inst->setCanCommit();
1101
1102 instQueue.recordProducer(inst);
1103
1104 add_to_iq = false;
1105 } else {
1106 add_to_iq = true;
1107 }
1108
1109 // If the instruction queue is not full, then add the
1110 // instruction.
1111 if (add_to_iq) {
1112 instQueue.insert(inst);
1113 }
1114
1115 insts_to_dispatch.pop();
1116
1117 toRename->iewInfo[tid].dispatched++;
1118
1119 ++iewDispatchedInsts;
1120 }
1121
1122 if (!insts_to_dispatch.empty()) {
1123 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1124 block(tid);
1125 toRename->iewUnblock[tid] = false;
1126 }
1127
1128 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1129 dispatchStatus[tid] = Running;
1130
1131 updatedQueues = true;
1132 }
1133
1134 dis_num_inst = 0;
1135}
1136
1137template <class Impl>
1138void
1139DefaultIEW<Impl>::printAvailableInsts()
1140{
1141 int inst = 0;
1142
1143 cout << "Available Instructions: ";
1144
1145 while (fromIssue->insts[inst]) {
1146
1147 if (inst%3==0) cout << "\n\t";
1148
1149 cout << "PC: " << fromIssue->insts[inst]->readPC()
1150 << " TN: " << fromIssue->insts[inst]->threadNumber
1151 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1152
1153 inst++;
1154
1155 }
1156
1157 cout << "\n";
1158}
1159
1160template <class Impl>
1161void
1162DefaultIEW<Impl>::executeInsts()
1163{
1164 wbNumInst = 0;
1165 wbCycle = 0;
1166
1167 list<unsigned>::iterator threads = (*activeThreads).begin();
1168
1169 while (threads != (*activeThreads).end()) {
1170 unsigned tid = *threads++;
1171 fetchRedirect[tid] = false;
1172 }
1173
1174 // Uncomment this if you want to see all available instructions.
1175// printAvailableInsts();
1176
1177 // Execute/writeback any instructions that are available.
1178 int insts_to_execute = fromIssue->size;
1179 int inst_num = 0;
1180 for (; inst_num < insts_to_execute;
1181 ++inst_num) {
1182
1183 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1184
1185 DynInstPtr inst = instQueue.getInstToExecute();
1186
1187 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1188 inst->readPC(), inst->threadNumber,inst->seqNum);
1189
1190 // Check if the instruction is squashed; if so then skip it
1191 if (inst->isSquashed()) {
1192 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1193
1194 // Consider this instruction executed so that commit can go
1195 // ahead and retire the instruction.
1196 inst->setExecuted();
1197
1198 // Not sure if I should set this here or just let commit try to
1199 // commit any squashed instructions. I like the latter a bit more.
1200 inst->setCanCommit();
1201
1202 ++iewExecSquashedInsts;
1203
1204 decrWb(inst->seqNum);
1205 continue;
1206 }
1207
1208 Fault fault = NoFault;
1209
1210 // Execute instruction.
1211 // Note that if the instruction faults, it will be handled
1212 // at the commit stage.
1213 if (inst->isMemRef() &&
1214 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1215 DPRINTF(IEW, "Execute: Calculating address for memory "
1216 "reference.\n");
1217
1218 // Tell the LDSTQ to execute this instruction (if it is a load).
1219 if (inst->isLoad()) {
1220 // Loads will mark themselves as executed, and their writeback
1221 // event adds the instruction to the queue to commit
1222 fault = ldstQueue.executeLoad(inst);
1223 } else if (inst->isStore()) {
1224 ldstQueue.executeStore(inst);
1225
1226 // If the store had a fault then it may not have a mem req
1227 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1228 inst->setExecuted();
1229
1230 instToCommit(inst);
1231 }
1232
1233 // Store conditionals will mark themselves as
1234 // executed, and their writeback event will add the
1235 // instruction to the queue to commit.
1236 } else {
1237 panic("Unexpected memory type!\n");
1238 }
1239
1240 } else {
1241 inst->execute();
1242
1243 inst->setExecuted();
1244
1245 instToCommit(inst);
1246 }
1247
1248 updateExeInstStats(inst);
1249
1250 // Check if branch prediction was correct, if not then we need
1251 // to tell commit to squash in flight instructions. Only
1252 // handle this if there hasn't already been something that
1253 // redirects fetch in this group of instructions.
1254
1255 // This probably needs to prioritize the redirects if a different
1256 // scheduler is used. Currently the scheduler schedules the oldest
1257 // instruction first, so the branch resolution order will be correct.
1258 unsigned tid = inst->threadNumber;
1259
1260 if (!fetchRedirect[tid]) {
1261
1262 if (inst->mispredicted()) {
1263 fetchRedirect[tid] = true;
1264
1265 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1266 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1267 inst->nextPC);
1268
1269 // If incorrect, then signal the ROB that it must be squashed.
1270 squashDueToBranch(inst, tid);
1271
1272 if (inst->predTaken()) {
1273 predictedTakenIncorrect++;
1274 } else {
1275 predictedNotTakenIncorrect++;
1276 }
1277 } else if (ldstQueue.violation(tid)) {
1278 fetchRedirect[tid] = true;
1279
1280 // If there was an ordering violation, then get the
1281 // DynInst that caused the violation. Note that this
1282 // clears the violation signal.
1283 DynInstPtr violator;
1284 violator = ldstQueue.getMemDepViolator(tid);
1285
1286 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1287 "%#x, inst PC: %#x. Addr is: %#x.\n",
1288 violator->readPC(), inst->readPC(), inst->physEffAddr);
1289
1290 // Tell the instruction queue that a violation has occured.
1291 instQueue.violation(inst, violator);
1292
1293 // Squash.
1294 squashDueToMemOrder(inst,tid);
1295
1296 ++memOrderViolationEvents;
1297 } else if (ldstQueue.loadBlocked(tid) &&
1298 !ldstQueue.isLoadBlockedHandled(tid)) {
1299 fetchRedirect[tid] = true;
1300
1301 DPRINTF(IEW, "Load operation couldn't execute because the "
1302 "memory system is blocked. PC: %#x [sn:%lli]\n",
1303 inst->readPC(), inst->seqNum);
1304
1305 squashDueToMemBlocked(inst, tid);
1306 }
1307 }
1308 }
1309
1310 // Update and record activity if we processed any instructions.
1311 if (inst_num) {
1312 if (exeStatus == Idle) {
1313 exeStatus = Running;
1314 }
1315
1316 updatedQueues = true;
1317
1318 cpu->activityThisCycle();
1319 }
1320
1321 // Need to reset this in case a writeback event needs to write into the
1322 // iew queue. That way the writeback event will write into the correct
1323 // spot in the queue.
1324 wbNumInst = 0;
1325}
1326
1327template <class Impl>
1328void
1329DefaultIEW<Impl>::writebackInsts()
1330{
1331 // Loop through the head of the time buffer and wake any
1332 // dependents. These instructions are about to write back. Also
1333 // mark scoreboard that this instruction is finally complete.
1334 // Either have IEW have direct access to scoreboard, or have this
1335 // as part of backwards communication.
1336 for (int inst_num = 0; inst_num < issueWidth &&
1337 toCommit->insts[inst_num]; inst_num++) {
1338 DynInstPtr inst = toCommit->insts[inst_num];
1339 int tid = inst->threadNumber;
1340
1341 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1342 inst->seqNum, inst->readPC());
1343
1344 iewInstsToCommit[tid]++;
1345
1346 // Some instructions will be sent to commit without having
1347 // executed because they need commit to handle them.
1348 // E.g. Uncached loads have not actually executed when they
1349 // are first sent to commit. Instead commit must tell the LSQ
1350 // when it's ready to execute the uncached load.
1351 if (!inst->isSquashed() && inst->isExecuted()) {
1352 int dependents = instQueue.wakeDependents(inst);
1353
1354 for (int i = 0; i < inst->numDestRegs(); i++) {
1355 //mark as Ready
1356 DPRINTF(IEW,"Setting Destination Register %i\n",
1357 inst->renamedDestRegIdx(i));
1358 scoreboard->setReg(inst->renamedDestRegIdx(i));
1359 }
1360
1361 if (dependents) {
1362 producerInst[tid]++;
1363 consumerInst[tid]+= dependents;
1364 }
1365 writebackCount[tid]++;
1366 }
1367
1368 decrWb(inst->seqNum);
1369 }
1370}
1371
1372template<class Impl>
1373void
1374DefaultIEW<Impl>::tick()
1375{
1376 wbNumInst = 0;
1377 wbCycle = 0;
1378
1379 wroteToTimeBuffer = false;
1380 updatedQueues = false;
1381
1382 sortInsts();
1383
1384 // Free function units marked as being freed this cycle.
1385 fuPool->processFreeUnits();
1386
1387 list<unsigned>::iterator threads = (*activeThreads).begin();
1388
1389 // Check stall and squash signals, dispatch any instructions.
1390 while (threads != (*activeThreads).end()) {
1391 unsigned tid = *threads++;
1392
1393 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1394
1395 checkSignalsAndUpdate(tid);
1396 dispatch(tid);
1397 }
1398
1399 if (exeStatus != Squashing) {
1400 executeInsts();
1401
1402 writebackInsts();
1403
1404 // Have the instruction queue try to schedule any ready instructions.
1405 // (In actuality, this scheduling is for instructions that will
1406 // be executed next cycle.)
1407 instQueue.scheduleReadyInsts();
1408
1409 // Also should advance its own time buffers if the stage ran.
1410 // Not the best place for it, but this works (hopefully).
1411 issueToExecQueue.advance();
1412 }
1413
1414 bool broadcast_free_entries = false;
1415
1416 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1417 exeStatus = Idle;
1418 updateLSQNextCycle = false;
1419
1420 broadcast_free_entries = true;
1421 }
1422
1423 // Writeback any stores using any leftover bandwidth.
1424 ldstQueue.writebackStores();
1425
1426 // Check the committed load/store signals to see if there's a load
1427 // or store to commit. Also check if it's being told to execute a
1428 // nonspeculative instruction.
1429 // This is pretty inefficient...
1430
1431 threads = (*activeThreads).begin();
1432 while (threads != (*activeThreads).end()) {
1433 unsigned tid = (*threads++);
1434
1435 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1436
1437 // Update structures based on instructions committed.
1438 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1439 !fromCommit->commitInfo[tid].squash &&
1440 !fromCommit->commitInfo[tid].robSquashing) {
1441
1442 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1443
1444 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1445
1446 updateLSQNextCycle = true;
1447 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1448 }
1449
1450 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1451
1452 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1453 if (fromCommit->commitInfo[tid].uncached) {
1454 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1455 } else {
1456 instQueue.scheduleNonSpec(
1457 fromCommit->commitInfo[tid].nonSpecSeqNum);
1458 }
1459 }
1460
1461 if (broadcast_free_entries) {
1462 toFetch->iewInfo[tid].iqCount =
1463 instQueue.getCount(tid);
1464 toFetch->iewInfo[tid].ldstqCount =
1465 ldstQueue.getCount(tid);
1466
1467 toRename->iewInfo[tid].usedIQ = true;
1468 toRename->iewInfo[tid].freeIQEntries =
1469 instQueue.numFreeEntries();
1470 toRename->iewInfo[tid].usedLSQ = true;
1471 toRename->iewInfo[tid].freeLSQEntries =
1472 ldstQueue.numFreeEntries(tid);
1473
1474 wroteToTimeBuffer = true;
1475 }
1476
1477 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1478 tid, toRename->iewInfo[tid].dispatched);
1479 }
1480
1481 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1482 "LSQ has %i free entries.\n",
1483 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1484 ldstQueue.numFreeEntries());
1485
1486 updateStatus();
1487
1488 if (wroteToTimeBuffer) {
1489 DPRINTF(Activity, "Activity this cycle.\n");
1490 cpu->activityThisCycle();
1491 }
1492}
1493
1494template <class Impl>
1495void
1496DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1497{
1498 int thread_number = inst->threadNumber;
1499
1500 //
1501 // Pick off the software prefetches
1502 //
1503#ifdef TARGET_ALPHA
1504 if (inst->isDataPrefetch())
1505 iewExecutedSwp[thread_number]++;
1506 else
1507 iewIewExecutedcutedInsts++;
1508#else
1509 iewExecutedInsts++;
1510#endif
1511
1512 //
1513 // Control operations
1514 //
1515 if (inst->isControl())
1516 iewExecutedBranches[thread_number]++;
1517
1518 //
1519 // Memory operations
1520 //
1521 if (inst->isMemRef()) {
1522 iewExecutedRefs[thread_number]++;
1523
1524 if (inst->isLoad()) {
1525 iewExecLoadInsts[thread_number]++;
1526 }
1527 }
1528}
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