1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31// @todo: Fix the instantaneous communication among all the stages within 32// iew. There's a clear delay between issue and execute, yet backwards 33// communication happens simultaneously. 34 35#include <queue> 36 37#include "base/timebuf.hh" 38#include "cpu/o3/fu_pool.hh" 39#include "cpu/o3/iew.hh" 40 41using namespace std; 42 43template<class Impl> 44DefaultIEW<Impl>::DefaultIEW(Params *params) 45 : // @todo: Make this into a parameter. 46 issueToExecQueue(5, 5), 47 instQueue(params), 48 ldstQueue(params), 49 fuPool(params->fuPool), 50 commitToIEWDelay(params->commitToIEWDelay), 51 renameToIEWDelay(params->renameToIEWDelay), 52 issueToExecuteDelay(params->issueToExecuteDelay),
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31// @todo: Fix the instantaneous communication among all the stages within 32// iew. There's a clear delay between issue and execute, yet backwards 33// communication happens simultaneously. 34 35#include <queue> 36 37#include "base/timebuf.hh" 38#include "cpu/o3/fu_pool.hh" 39#include "cpu/o3/iew.hh" 40 41using namespace std; 42 43template<class Impl> 44DefaultIEW<Impl>::DefaultIEW(Params *params) 45 : // @todo: Make this into a parameter. 46 issueToExecQueue(5, 5), 47 instQueue(params), 48 ldstQueue(params), 49 fuPool(params->fuPool), 50 commitToIEWDelay(params->commitToIEWDelay), 51 renameToIEWDelay(params->renameToIEWDelay), 52 issueToExecuteDelay(params->issueToExecuteDelay),
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53 issueReadWidth(params->issueWidth),
| 53 dispatchWidth(params->dispatchWidth),
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54 issueWidth(params->issueWidth),
| 54 issueWidth(params->issueWidth),
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| 55 wbOutstanding(0), 56 wbWidth(params->wbWidth),
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55 numThreads(params->numberOfThreads), 56 switchedOut(false) 57{ 58 _status = Active; 59 exeStatus = Running; 60 wbStatus = Idle; 61 62 // Setup wire to read instructions coming from issue. 63 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 64 65 // Instruction queue needs the queue between issue and execute. 66 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 67 68 instQueue.setIEW(this); 69 ldstQueue.setIEW(this); 70 71 for (int i=0; i < numThreads; i++) { 72 dispatchStatus[i] = Running; 73 stalls[i].commit = false; 74 fetchRedirect[i] = false; 75 } 76
| 57 numThreads(params->numberOfThreads), 58 switchedOut(false) 59{ 60 _status = Active; 61 exeStatus = Running; 62 wbStatus = Idle; 63 64 // Setup wire to read instructions coming from issue. 65 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 66 67 // Instruction queue needs the queue between issue and execute. 68 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 69 70 instQueue.setIEW(this); 71 ldstQueue.setIEW(this); 72 73 for (int i=0; i < numThreads; i++) { 74 dispatchStatus[i] = Running; 75 stalls[i].commit = false; 76 fetchRedirect[i] = false; 77 } 78
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| 79 wbMax = wbWidth * params->wbDepth; 80
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77 updateLSQNextCycle = false; 78
| 81 updateLSQNextCycle = false; 82
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| 83 ableToIssue = true; 84
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79 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 80} 81 82template <class Impl> 83std::string 84DefaultIEW<Impl>::name() const 85{ 86 return cpu->name() + ".iew"; 87} 88 89template <class Impl> 90void 91DefaultIEW<Impl>::regStats() 92{ 93 using namespace Stats; 94 95 instQueue.regStats(); 96 ldstQueue.regStats(); 97 98 iewIdleCycles 99 .name(name() + ".iewIdleCycles") 100 .desc("Number of cycles IEW is idle"); 101 102 iewSquashCycles 103 .name(name() + ".iewSquashCycles") 104 .desc("Number of cycles IEW is squashing"); 105 106 iewBlockCycles 107 .name(name() + ".iewBlockCycles") 108 .desc("Number of cycles IEW is blocking"); 109 110 iewUnblockCycles 111 .name(name() + ".iewUnblockCycles") 112 .desc("Number of cycles IEW is unblocking"); 113 114 iewDispatchedInsts 115 .name(name() + ".iewDispatchedInsts") 116 .desc("Number of instructions dispatched to IQ"); 117 118 iewDispSquashedInsts 119 .name(name() + ".iewDispSquashedInsts") 120 .desc("Number of squashed instructions skipped by dispatch"); 121 122 iewDispLoadInsts 123 .name(name() + ".iewDispLoadInsts") 124 .desc("Number of dispatched load instructions"); 125 126 iewDispStoreInsts 127 .name(name() + ".iewDispStoreInsts") 128 .desc("Number of dispatched store instructions"); 129 130 iewDispNonSpecInsts 131 .name(name() + ".iewDispNonSpecInsts") 132 .desc("Number of dispatched non-speculative instructions"); 133 134 iewIQFullEvents 135 .name(name() + ".iewIQFullEvents") 136 .desc("Number of times the IQ has become full, causing a stall"); 137 138 iewLSQFullEvents 139 .name(name() + ".iewLSQFullEvents") 140 .desc("Number of times the LSQ has become full, causing a stall"); 141 142 memOrderViolationEvents 143 .name(name() + ".memOrderViolationEvents") 144 .desc("Number of memory order violations"); 145 146 predictedTakenIncorrect 147 .name(name() + ".predictedTakenIncorrect") 148 .desc("Number of branches that were predicted taken incorrectly"); 149 150 predictedNotTakenIncorrect 151 .name(name() + ".predictedNotTakenIncorrect") 152 .desc("Number of branches that were predicted not taken incorrectly"); 153 154 branchMispredicts 155 .name(name() + ".branchMispredicts") 156 .desc("Number of branch mispredicts detected at execute"); 157 158 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 159 160 iewExecutedInsts 161 .name(name() + ".EXEC:insts") 162 .desc("Number of executed instructions"); 163 164 iewExecLoadInsts 165 .init(cpu->number_of_threads) 166 .name(name() + ".EXEC:loads") 167 .desc("Number of load instructions executed") 168 .flags(total); 169 170 iewExecSquashedInsts 171 .name(name() + ".EXEC:squashedInsts") 172 .desc("Number of squashed instructions skipped in execute"); 173 174 iewExecutedSwp 175 .init(cpu->number_of_threads) 176 .name(name() + ".EXEC:swp") 177 .desc("number of swp insts executed") 178 .flags(total); 179 180 iewExecutedNop 181 .init(cpu->number_of_threads) 182 .name(name() + ".EXEC:nop") 183 .desc("number of nop insts executed") 184 .flags(total); 185 186 iewExecutedRefs 187 .init(cpu->number_of_threads) 188 .name(name() + ".EXEC:refs") 189 .desc("number of memory reference insts executed") 190 .flags(total); 191 192 iewExecutedBranches 193 .init(cpu->number_of_threads) 194 .name(name() + ".EXEC:branches") 195 .desc("Number of branches executed") 196 .flags(total); 197 198 iewExecStoreInsts 199 .name(name() + ".EXEC:stores") 200 .desc("Number of stores executed") 201 .flags(total); 202 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 203 204 iewExecRate 205 .name(name() + ".EXEC:rate") 206 .desc("Inst execution rate") 207 .flags(total); 208 209 iewExecRate = iewExecutedInsts / cpu->numCycles; 210 211 iewInstsToCommit 212 .init(cpu->number_of_threads) 213 .name(name() + ".WB:sent") 214 .desc("cumulative count of insts sent to commit") 215 .flags(total); 216 217 writebackCount 218 .init(cpu->number_of_threads) 219 .name(name() + ".WB:count") 220 .desc("cumulative count of insts written-back") 221 .flags(total); 222 223 producerInst 224 .init(cpu->number_of_threads) 225 .name(name() + ".WB:producers") 226 .desc("num instructions producing a value") 227 .flags(total); 228 229 consumerInst 230 .init(cpu->number_of_threads) 231 .name(name() + ".WB:consumers") 232 .desc("num instructions consuming a value") 233 .flags(total); 234 235 wbPenalized 236 .init(cpu->number_of_threads) 237 .name(name() + ".WB:penalized") 238 .desc("number of instrctions required to write to 'other' IQ") 239 .flags(total); 240 241 wbPenalizedRate 242 .name(name() + ".WB:penalized_rate") 243 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 244 .flags(total); 245 246 wbPenalizedRate = wbPenalized / writebackCount; 247 248 wbFanout 249 .name(name() + ".WB:fanout") 250 .desc("average fanout of values written-back") 251 .flags(total); 252 253 wbFanout = producerInst / consumerInst; 254 255 wbRate 256 .name(name() + ".WB:rate") 257 .desc("insts written-back per cycle") 258 .flags(total); 259 wbRate = writebackCount / cpu->numCycles; 260} 261 262template<class Impl> 263void 264DefaultIEW<Impl>::initStage() 265{ 266 for (int tid=0; tid < numThreads; tid++) { 267 toRename->iewInfo[tid].usedIQ = true; 268 toRename->iewInfo[tid].freeIQEntries = 269 instQueue.numFreeEntries(tid); 270 271 toRename->iewInfo[tid].usedLSQ = true; 272 toRename->iewInfo[tid].freeLSQEntries = 273 ldstQueue.numFreeEntries(tid); 274 } 275} 276 277template<class Impl> 278void 279DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 280{ 281 DPRINTF(IEW, "Setting CPU pointer.\n"); 282 cpu = cpu_ptr; 283 284 instQueue.setCPU(cpu_ptr); 285 ldstQueue.setCPU(cpu_ptr); 286 287 cpu->activateStage(O3CPU::IEWIdx); 288} 289 290template<class Impl> 291void 292DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 293{ 294 DPRINTF(IEW, "Setting time buffer pointer.\n"); 295 timeBuffer = tb_ptr; 296 297 // Setup wire to read information from time buffer, from commit. 298 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 299 300 // Setup wire to write information back to previous stages. 301 toRename = timeBuffer->getWire(0); 302 303 toFetch = timeBuffer->getWire(0); 304 305 // Instruction queue also needs main time buffer. 306 instQueue.setTimeBuffer(tb_ptr); 307} 308 309template<class Impl> 310void 311DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 312{ 313 DPRINTF(IEW, "Setting rename queue pointer.\n"); 314 renameQueue = rq_ptr; 315 316 // Setup wire to read information from rename queue. 317 fromRename = renameQueue->getWire(-renameToIEWDelay); 318} 319 320template<class Impl> 321void 322DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 323{ 324 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 325 iewQueue = iq_ptr; 326 327 // Setup wire to write instructions to commit. 328 toCommit = iewQueue->getWire(0); 329} 330 331template<class Impl> 332void 333DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 334{ 335 DPRINTF(IEW, "Setting active threads list pointer.\n"); 336 activeThreads = at_ptr; 337 338 ldstQueue.setActiveThreads(at_ptr); 339 instQueue.setActiveThreads(at_ptr); 340} 341 342template<class Impl> 343void 344DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 345{ 346 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 347 scoreboard = sb_ptr; 348} 349 350template <class Impl> 351void 352DefaultIEW<Impl>::switchOut() 353{ 354 // IEW is ready to switch out at any time. 355 cpu->signalSwitched(); 356} 357 358template <class Impl> 359void 360DefaultIEW<Impl>::doSwitchOut() 361{ 362 // Clear any state. 363 switchedOut = true; 364 365 instQueue.switchOut(); 366 ldstQueue.switchOut(); 367 fuPool->switchOut(); 368 369 for (int i = 0; i < numThreads; i++) { 370 while (!insts[i].empty()) 371 insts[i].pop(); 372 while (!skidBuffer[i].empty()) 373 skidBuffer[i].pop(); 374 } 375} 376 377template <class Impl> 378void 379DefaultIEW<Impl>::takeOverFrom() 380{ 381 // Reset all state. 382 _status = Active; 383 exeStatus = Running; 384 wbStatus = Idle; 385 switchedOut = false; 386 387 instQueue.takeOverFrom(); 388 ldstQueue.takeOverFrom(); 389 fuPool->takeOverFrom(); 390 391 initStage(); 392 cpu->activityThisCycle(); 393 394 for (int i=0; i < numThreads; i++) { 395 dispatchStatus[i] = Running; 396 stalls[i].commit = false; 397 fetchRedirect[i] = false; 398 } 399 400 updateLSQNextCycle = false; 401 402 // @todo: Fix hardcoded number 403 for (int i = 0; i < 6; ++i) { 404 issueToExecQueue.advance(); 405 } 406} 407 408template<class Impl> 409void 410DefaultIEW<Impl>::squash(unsigned tid) 411{ 412 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 413 tid); 414 415 // Tell the IQ to start squashing. 416 instQueue.squash(tid); 417 418 // Tell the LDSTQ to start squashing. 419 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 420 421 updatedQueues = true; 422 423 // Clear the skid buffer in case it has any data in it. 424 while (!skidBuffer[tid].empty()) { 425 426 if (skidBuffer[tid].front()->isLoad() || 427 skidBuffer[tid].front()->isStore() ) { 428 toRename->iewInfo[tid].dispatchedToLSQ++; 429 } 430 431 toRename->iewInfo[tid].dispatched++; 432 433 skidBuffer[tid].pop(); 434 } 435 436 emptyRenameInsts(tid); 437} 438 439template<class Impl> 440void 441DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 442{ 443 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 444 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 445 446 toCommit->squash[tid] = true; 447 toCommit->squashedSeqNum[tid] = inst->seqNum; 448 toCommit->mispredPC[tid] = inst->readPC(); 449 toCommit->nextPC[tid] = inst->readNextPC(); 450 toCommit->branchMispredict[tid] = true; 451 toCommit->branchTaken[tid] = inst->readNextPC() != 452 (inst->readPC() + sizeof(TheISA::MachInst)); 453 454 toCommit->includeSquashInst[tid] = false; 455 456 wroteToTimeBuffer = true; 457} 458 459template<class Impl> 460void 461DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 462{ 463 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 464 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 465 466 toCommit->squash[tid] = true; 467 toCommit->squashedSeqNum[tid] = inst->seqNum; 468 toCommit->nextPC[tid] = inst->readNextPC(); 469 470 toCommit->includeSquashInst[tid] = false; 471 472 wroteToTimeBuffer = true; 473} 474 475template<class Impl> 476void 477DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 478{ 479 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 480 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 481 482 toCommit->squash[tid] = true; 483 toCommit->squashedSeqNum[tid] = inst->seqNum; 484 toCommit->nextPC[tid] = inst->readPC(); 485 486 // Must include the broadcasted SN in the squash. 487 toCommit->includeSquashInst[tid] = true; 488 489 ldstQueue.setLoadBlockedHandled(tid); 490 491 wroteToTimeBuffer = true; 492} 493 494template<class Impl> 495void 496DefaultIEW<Impl>::block(unsigned tid) 497{ 498 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 499 500 if (dispatchStatus[tid] != Blocked && 501 dispatchStatus[tid] != Unblocking) { 502 toRename->iewBlock[tid] = true; 503 wroteToTimeBuffer = true; 504 } 505 506 // Add the current inputs to the skid buffer so they can be 507 // reprocessed when this stage unblocks. 508 skidInsert(tid); 509 510 dispatchStatus[tid] = Blocked; 511} 512 513template<class Impl> 514void 515DefaultIEW<Impl>::unblock(unsigned tid) 516{ 517 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 518 "buffer %u.\n",tid, tid); 519 520 // If the skid bufffer is empty, signal back to previous stages to unblock. 521 // Also switch status to running. 522 if (skidBuffer[tid].empty()) { 523 toRename->iewUnblock[tid] = true; 524 wroteToTimeBuffer = true; 525 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 526 dispatchStatus[tid] = Running; 527 } 528} 529 530template<class Impl> 531void 532DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 533{ 534 instQueue.wakeDependents(inst); 535} 536 537template<class Impl> 538void 539DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 540{ 541 instQueue.rescheduleMemInst(inst); 542} 543 544template<class Impl> 545void 546DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 547{ 548 instQueue.replayMemInst(inst); 549} 550 551template<class Impl> 552void 553DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 554{ 555 // First check the time slot that this instruction will write 556 // to. If there are free write ports at the time, then go ahead 557 // and write the instruction to that time. If there are not, 558 // keep looking back to see where's the first time there's a 559 // free slot. 560 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 561 ++wbNumInst;
| 85 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 86} 87 88template <class Impl> 89std::string 90DefaultIEW<Impl>::name() const 91{ 92 return cpu->name() + ".iew"; 93} 94 95template <class Impl> 96void 97DefaultIEW<Impl>::regStats() 98{ 99 using namespace Stats; 100 101 instQueue.regStats(); 102 ldstQueue.regStats(); 103 104 iewIdleCycles 105 .name(name() + ".iewIdleCycles") 106 .desc("Number of cycles IEW is idle"); 107 108 iewSquashCycles 109 .name(name() + ".iewSquashCycles") 110 .desc("Number of cycles IEW is squashing"); 111 112 iewBlockCycles 113 .name(name() + ".iewBlockCycles") 114 .desc("Number of cycles IEW is blocking"); 115 116 iewUnblockCycles 117 .name(name() + ".iewUnblockCycles") 118 .desc("Number of cycles IEW is unblocking"); 119 120 iewDispatchedInsts 121 .name(name() + ".iewDispatchedInsts") 122 .desc("Number of instructions dispatched to IQ"); 123 124 iewDispSquashedInsts 125 .name(name() + ".iewDispSquashedInsts") 126 .desc("Number of squashed instructions skipped by dispatch"); 127 128 iewDispLoadInsts 129 .name(name() + ".iewDispLoadInsts") 130 .desc("Number of dispatched load instructions"); 131 132 iewDispStoreInsts 133 .name(name() + ".iewDispStoreInsts") 134 .desc("Number of dispatched store instructions"); 135 136 iewDispNonSpecInsts 137 .name(name() + ".iewDispNonSpecInsts") 138 .desc("Number of dispatched non-speculative instructions"); 139 140 iewIQFullEvents 141 .name(name() + ".iewIQFullEvents") 142 .desc("Number of times the IQ has become full, causing a stall"); 143 144 iewLSQFullEvents 145 .name(name() + ".iewLSQFullEvents") 146 .desc("Number of times the LSQ has become full, causing a stall"); 147 148 memOrderViolationEvents 149 .name(name() + ".memOrderViolationEvents") 150 .desc("Number of memory order violations"); 151 152 predictedTakenIncorrect 153 .name(name() + ".predictedTakenIncorrect") 154 .desc("Number of branches that were predicted taken incorrectly"); 155 156 predictedNotTakenIncorrect 157 .name(name() + ".predictedNotTakenIncorrect") 158 .desc("Number of branches that were predicted not taken incorrectly"); 159 160 branchMispredicts 161 .name(name() + ".branchMispredicts") 162 .desc("Number of branch mispredicts detected at execute"); 163 164 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 165 166 iewExecutedInsts 167 .name(name() + ".EXEC:insts") 168 .desc("Number of executed instructions"); 169 170 iewExecLoadInsts 171 .init(cpu->number_of_threads) 172 .name(name() + ".EXEC:loads") 173 .desc("Number of load instructions executed") 174 .flags(total); 175 176 iewExecSquashedInsts 177 .name(name() + ".EXEC:squashedInsts") 178 .desc("Number of squashed instructions skipped in execute"); 179 180 iewExecutedSwp 181 .init(cpu->number_of_threads) 182 .name(name() + ".EXEC:swp") 183 .desc("number of swp insts executed") 184 .flags(total); 185 186 iewExecutedNop 187 .init(cpu->number_of_threads) 188 .name(name() + ".EXEC:nop") 189 .desc("number of nop insts executed") 190 .flags(total); 191 192 iewExecutedRefs 193 .init(cpu->number_of_threads) 194 .name(name() + ".EXEC:refs") 195 .desc("number of memory reference insts executed") 196 .flags(total); 197 198 iewExecutedBranches 199 .init(cpu->number_of_threads) 200 .name(name() + ".EXEC:branches") 201 .desc("Number of branches executed") 202 .flags(total); 203 204 iewExecStoreInsts 205 .name(name() + ".EXEC:stores") 206 .desc("Number of stores executed") 207 .flags(total); 208 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 209 210 iewExecRate 211 .name(name() + ".EXEC:rate") 212 .desc("Inst execution rate") 213 .flags(total); 214 215 iewExecRate = iewExecutedInsts / cpu->numCycles; 216 217 iewInstsToCommit 218 .init(cpu->number_of_threads) 219 .name(name() + ".WB:sent") 220 .desc("cumulative count of insts sent to commit") 221 .flags(total); 222 223 writebackCount 224 .init(cpu->number_of_threads) 225 .name(name() + ".WB:count") 226 .desc("cumulative count of insts written-back") 227 .flags(total); 228 229 producerInst 230 .init(cpu->number_of_threads) 231 .name(name() + ".WB:producers") 232 .desc("num instructions producing a value") 233 .flags(total); 234 235 consumerInst 236 .init(cpu->number_of_threads) 237 .name(name() + ".WB:consumers") 238 .desc("num instructions consuming a value") 239 .flags(total); 240 241 wbPenalized 242 .init(cpu->number_of_threads) 243 .name(name() + ".WB:penalized") 244 .desc("number of instrctions required to write to 'other' IQ") 245 .flags(total); 246 247 wbPenalizedRate 248 .name(name() + ".WB:penalized_rate") 249 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 250 .flags(total); 251 252 wbPenalizedRate = wbPenalized / writebackCount; 253 254 wbFanout 255 .name(name() + ".WB:fanout") 256 .desc("average fanout of values written-back") 257 .flags(total); 258 259 wbFanout = producerInst / consumerInst; 260 261 wbRate 262 .name(name() + ".WB:rate") 263 .desc("insts written-back per cycle") 264 .flags(total); 265 wbRate = writebackCount / cpu->numCycles; 266} 267 268template<class Impl> 269void 270DefaultIEW<Impl>::initStage() 271{ 272 for (int tid=0; tid < numThreads; tid++) { 273 toRename->iewInfo[tid].usedIQ = true; 274 toRename->iewInfo[tid].freeIQEntries = 275 instQueue.numFreeEntries(tid); 276 277 toRename->iewInfo[tid].usedLSQ = true; 278 toRename->iewInfo[tid].freeLSQEntries = 279 ldstQueue.numFreeEntries(tid); 280 } 281} 282 283template<class Impl> 284void 285DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 286{ 287 DPRINTF(IEW, "Setting CPU pointer.\n"); 288 cpu = cpu_ptr; 289 290 instQueue.setCPU(cpu_ptr); 291 ldstQueue.setCPU(cpu_ptr); 292 293 cpu->activateStage(O3CPU::IEWIdx); 294} 295 296template<class Impl> 297void 298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 299{ 300 DPRINTF(IEW, "Setting time buffer pointer.\n"); 301 timeBuffer = tb_ptr; 302 303 // Setup wire to read information from time buffer, from commit. 304 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 305 306 // Setup wire to write information back to previous stages. 307 toRename = timeBuffer->getWire(0); 308 309 toFetch = timeBuffer->getWire(0); 310 311 // Instruction queue also needs main time buffer. 312 instQueue.setTimeBuffer(tb_ptr); 313} 314 315template<class Impl> 316void 317DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 318{ 319 DPRINTF(IEW, "Setting rename queue pointer.\n"); 320 renameQueue = rq_ptr; 321 322 // Setup wire to read information from rename queue. 323 fromRename = renameQueue->getWire(-renameToIEWDelay); 324} 325 326template<class Impl> 327void 328DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 329{ 330 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 331 iewQueue = iq_ptr; 332 333 // Setup wire to write instructions to commit. 334 toCommit = iewQueue->getWire(0); 335} 336 337template<class Impl> 338void 339DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 340{ 341 DPRINTF(IEW, "Setting active threads list pointer.\n"); 342 activeThreads = at_ptr; 343 344 ldstQueue.setActiveThreads(at_ptr); 345 instQueue.setActiveThreads(at_ptr); 346} 347 348template<class Impl> 349void 350DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 351{ 352 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 353 scoreboard = sb_ptr; 354} 355 356template <class Impl> 357void 358DefaultIEW<Impl>::switchOut() 359{ 360 // IEW is ready to switch out at any time. 361 cpu->signalSwitched(); 362} 363 364template <class Impl> 365void 366DefaultIEW<Impl>::doSwitchOut() 367{ 368 // Clear any state. 369 switchedOut = true; 370 371 instQueue.switchOut(); 372 ldstQueue.switchOut(); 373 fuPool->switchOut(); 374 375 for (int i = 0; i < numThreads; i++) { 376 while (!insts[i].empty()) 377 insts[i].pop(); 378 while (!skidBuffer[i].empty()) 379 skidBuffer[i].pop(); 380 } 381} 382 383template <class Impl> 384void 385DefaultIEW<Impl>::takeOverFrom() 386{ 387 // Reset all state. 388 _status = Active; 389 exeStatus = Running; 390 wbStatus = Idle; 391 switchedOut = false; 392 393 instQueue.takeOverFrom(); 394 ldstQueue.takeOverFrom(); 395 fuPool->takeOverFrom(); 396 397 initStage(); 398 cpu->activityThisCycle(); 399 400 for (int i=0; i < numThreads; i++) { 401 dispatchStatus[i] = Running; 402 stalls[i].commit = false; 403 fetchRedirect[i] = false; 404 } 405 406 updateLSQNextCycle = false; 407 408 // @todo: Fix hardcoded number 409 for (int i = 0; i < 6; ++i) { 410 issueToExecQueue.advance(); 411 } 412} 413 414template<class Impl> 415void 416DefaultIEW<Impl>::squash(unsigned tid) 417{ 418 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 419 tid); 420 421 // Tell the IQ to start squashing. 422 instQueue.squash(tid); 423 424 // Tell the LDSTQ to start squashing. 425 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 426 427 updatedQueues = true; 428 429 // Clear the skid buffer in case it has any data in it. 430 while (!skidBuffer[tid].empty()) { 431 432 if (skidBuffer[tid].front()->isLoad() || 433 skidBuffer[tid].front()->isStore() ) { 434 toRename->iewInfo[tid].dispatchedToLSQ++; 435 } 436 437 toRename->iewInfo[tid].dispatched++; 438 439 skidBuffer[tid].pop(); 440 } 441 442 emptyRenameInsts(tid); 443} 444 445template<class Impl> 446void 447DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 448{ 449 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 450 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 451 452 toCommit->squash[tid] = true; 453 toCommit->squashedSeqNum[tid] = inst->seqNum; 454 toCommit->mispredPC[tid] = inst->readPC(); 455 toCommit->nextPC[tid] = inst->readNextPC(); 456 toCommit->branchMispredict[tid] = true; 457 toCommit->branchTaken[tid] = inst->readNextPC() != 458 (inst->readPC() + sizeof(TheISA::MachInst)); 459 460 toCommit->includeSquashInst[tid] = false; 461 462 wroteToTimeBuffer = true; 463} 464 465template<class Impl> 466void 467DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 468{ 469 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 470 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 471 472 toCommit->squash[tid] = true; 473 toCommit->squashedSeqNum[tid] = inst->seqNum; 474 toCommit->nextPC[tid] = inst->readNextPC(); 475 476 toCommit->includeSquashInst[tid] = false; 477 478 wroteToTimeBuffer = true; 479} 480 481template<class Impl> 482void 483DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 484{ 485 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 486 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 487 488 toCommit->squash[tid] = true; 489 toCommit->squashedSeqNum[tid] = inst->seqNum; 490 toCommit->nextPC[tid] = inst->readPC(); 491 492 // Must include the broadcasted SN in the squash. 493 toCommit->includeSquashInst[tid] = true; 494 495 ldstQueue.setLoadBlockedHandled(tid); 496 497 wroteToTimeBuffer = true; 498} 499 500template<class Impl> 501void 502DefaultIEW<Impl>::block(unsigned tid) 503{ 504 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 505 506 if (dispatchStatus[tid] != Blocked && 507 dispatchStatus[tid] != Unblocking) { 508 toRename->iewBlock[tid] = true; 509 wroteToTimeBuffer = true; 510 } 511 512 // Add the current inputs to the skid buffer so they can be 513 // reprocessed when this stage unblocks. 514 skidInsert(tid); 515 516 dispatchStatus[tid] = Blocked; 517} 518 519template<class Impl> 520void 521DefaultIEW<Impl>::unblock(unsigned tid) 522{ 523 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 524 "buffer %u.\n",tid, tid); 525 526 // If the skid bufffer is empty, signal back to previous stages to unblock. 527 // Also switch status to running. 528 if (skidBuffer[tid].empty()) { 529 toRename->iewUnblock[tid] = true; 530 wroteToTimeBuffer = true; 531 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 532 dispatchStatus[tid] = Running; 533 } 534} 535 536template<class Impl> 537void 538DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 539{ 540 instQueue.wakeDependents(inst); 541} 542 543template<class Impl> 544void 545DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 546{ 547 instQueue.rescheduleMemInst(inst); 548} 549 550template<class Impl> 551void 552DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 553{ 554 instQueue.replayMemInst(inst); 555} 556 557template<class Impl> 558void 559DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 560{ 561 // First check the time slot that this instruction will write 562 // to. If there are free write ports at the time, then go ahead 563 // and write the instruction to that time. If there are not, 564 // keep looking back to see where's the first time there's a 565 // free slot. 566 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 567 ++wbNumInst;
|
562 if (wbNumInst == issueWidth) {
| 568 if (wbNumInst == wbWidth) {
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563 ++wbCycle; 564 wbNumInst = 0; 565 } 566
| 569 ++wbCycle; 570 wbNumInst = 0; 571 } 572
|
567 assert(wbCycle < 5);
| 573 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
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568 } 569 570 // Add finished instruction to queue to commit. 571 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 572 (*iewQueue)[wbCycle].size++; 573} 574 575template <class Impl> 576unsigned 577DefaultIEW<Impl>::validInstsFromRename() 578{ 579 unsigned inst_count = 0; 580 581 for (int i=0; i<fromRename->size; i++) { 582 if (!fromRename->insts[i]->isSquashed()) 583 inst_count++; 584 } 585 586 return inst_count; 587} 588 589template<class Impl> 590void 591DefaultIEW<Impl>::skidInsert(unsigned tid) 592{ 593 DynInstPtr inst = NULL; 594 595 while (!insts[tid].empty()) { 596 inst = insts[tid].front(); 597 598 insts[tid].pop(); 599 600 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 601 "dispatch skidBuffer %i\n",tid, inst->seqNum, 602 inst->readPC(),tid); 603 604 skidBuffer[tid].push(inst); 605 } 606 607 assert(skidBuffer[tid].size() <= skidBufferMax && 608 "Skidbuffer Exceeded Max Size"); 609} 610 611template<class Impl> 612int 613DefaultIEW<Impl>::skidCount() 614{ 615 int max=0; 616 617 list<unsigned>::iterator threads = (*activeThreads).begin(); 618 619 while (threads != (*activeThreads).end()) { 620 unsigned thread_count = skidBuffer[*threads++].size(); 621 if (max < thread_count) 622 max = thread_count; 623 } 624 625 return max; 626} 627 628template<class Impl> 629bool 630DefaultIEW<Impl>::skidsEmpty() 631{ 632 list<unsigned>::iterator threads = (*activeThreads).begin(); 633 634 while (threads != (*activeThreads).end()) { 635 if (!skidBuffer[*threads++].empty()) 636 return false; 637 } 638 639 return true; 640} 641 642template <class Impl> 643void 644DefaultIEW<Impl>::updateStatus() 645{ 646 bool any_unblocking = false; 647 648 list<unsigned>::iterator threads = (*activeThreads).begin(); 649 650 threads = (*activeThreads).begin(); 651 652 while (threads != (*activeThreads).end()) { 653 unsigned tid = *threads++; 654 655 if (dispatchStatus[tid] == Unblocking) { 656 any_unblocking = true; 657 break; 658 } 659 } 660 661 // If there are no ready instructions waiting to be scheduled by the IQ, 662 // and there's no stores waiting to write back, and dispatch is not 663 // unblocking, then there is no internal activity for the IEW stage. 664 if (_status == Active && !instQueue.hasReadyInsts() && 665 !ldstQueue.willWB() && !any_unblocking) { 666 DPRINTF(IEW, "IEW switching to idle\n"); 667 668 deactivateStage(); 669 670 _status = Inactive; 671 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 672 ldstQueue.willWB() || 673 any_unblocking)) { 674 // Otherwise there is internal activity. Set to active. 675 DPRINTF(IEW, "IEW switching to active\n"); 676 677 activateStage(); 678 679 _status = Active; 680 } 681} 682 683template <class Impl> 684void 685DefaultIEW<Impl>::resetEntries() 686{ 687 instQueue.resetEntries(); 688 ldstQueue.resetEntries(); 689} 690 691template <class Impl> 692void 693DefaultIEW<Impl>::readStallSignals(unsigned tid) 694{ 695 if (fromCommit->commitBlock[tid]) { 696 stalls[tid].commit = true; 697 } 698 699 if (fromCommit->commitUnblock[tid]) { 700 assert(stalls[tid].commit); 701 stalls[tid].commit = false; 702 } 703} 704 705template <class Impl> 706bool 707DefaultIEW<Impl>::checkStall(unsigned tid) 708{ 709 bool ret_val(false); 710 711 if (stalls[tid].commit) { 712 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 713 ret_val = true; 714 } else if (instQueue.isFull(tid)) { 715 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 716 ret_val = true; 717 } else if (ldstQueue.isFull(tid)) { 718 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 719 720 if (ldstQueue.numLoads(tid) > 0 ) { 721 722 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 723 tid,ldstQueue.getLoadHeadSeqNum(tid)); 724 } 725 726 if (ldstQueue.numStores(tid) > 0) { 727 728 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 729 tid,ldstQueue.getStoreHeadSeqNum(tid)); 730 } 731 732 ret_val = true; 733 } else if (ldstQueue.isStalled(tid)) { 734 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 735 ret_val = true; 736 } 737 738 return ret_val; 739} 740 741template <class Impl> 742void 743DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 744{ 745 // Check if there's a squash signal, squash if there is 746 // Check stall signals, block if there is. 747 // If status was Blocked 748 // if so then go to unblocking 749 // If status was Squashing 750 // check if squashing is not high. Switch to running this cycle. 751 752 readStallSignals(tid); 753 754 if (fromCommit->commitInfo[tid].squash) { 755 squash(tid); 756 757 if (dispatchStatus[tid] == Blocked || 758 dispatchStatus[tid] == Unblocking) { 759 toRename->iewUnblock[tid] = true; 760 wroteToTimeBuffer = true; 761 } 762 763 dispatchStatus[tid] = Squashing; 764 765 fetchRedirect[tid] = false; 766 return; 767 } 768 769 if (fromCommit->commitInfo[tid].robSquashing) { 770 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 771 772 dispatchStatus[tid] = Squashing; 773 774 emptyRenameInsts(tid); 775 wroteToTimeBuffer = true; 776 return; 777 } 778 779 if (checkStall(tid)) { 780 block(tid); 781 dispatchStatus[tid] = Blocked; 782 return; 783 } 784 785 if (dispatchStatus[tid] == Blocked) { 786 // Status from previous cycle was blocked, but there are no more stall 787 // conditions. Switch over to unblocking. 788 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 789 tid); 790 791 dispatchStatus[tid] = Unblocking; 792 793 unblock(tid); 794 795 return; 796 } 797 798 if (dispatchStatus[tid] == Squashing) { 799 // Switch status to running if rename isn't being told to block or 800 // squash this cycle. 801 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 802 tid); 803 804 dispatchStatus[tid] = Running; 805 806 return; 807 } 808} 809 810template <class Impl> 811void 812DefaultIEW<Impl>::sortInsts() 813{ 814 int insts_from_rename = fromRename->size; 815#ifdef DEBUG 816 for (int i = 0; i < numThreads; i++) 817 assert(insts[i].empty()); 818#endif 819 for (int i = 0; i < insts_from_rename; ++i) { 820 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 821 } 822} 823 824template <class Impl> 825void 826DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 827{ 828 while (!insts[tid].empty()) { 829 if (insts[tid].front()->isLoad() || 830 insts[tid].front()->isStore() ) { 831 toRename->iewInfo[tid].dispatchedToLSQ++; 832 } 833 834 toRename->iewInfo[tid].dispatched++; 835 836 insts[tid].pop(); 837 } 838} 839 840template <class Impl> 841void 842DefaultIEW<Impl>::wakeCPU() 843{ 844 cpu->wakeCPU(); 845} 846 847template <class Impl> 848void 849DefaultIEW<Impl>::activityThisCycle() 850{ 851 DPRINTF(Activity, "Activity this cycle.\n"); 852 cpu->activityThisCycle(); 853} 854 855template <class Impl> 856inline void 857DefaultIEW<Impl>::activateStage() 858{ 859 DPRINTF(Activity, "Activating stage.\n"); 860 cpu->activateStage(O3CPU::IEWIdx); 861} 862 863template <class Impl> 864inline void 865DefaultIEW<Impl>::deactivateStage() 866{ 867 DPRINTF(Activity, "Deactivating stage.\n"); 868 cpu->deactivateStage(O3CPU::IEWIdx); 869} 870 871template<class Impl> 872void 873DefaultIEW<Impl>::dispatch(unsigned tid) 874{ 875 // If status is Running or idle, 876 // call dispatchInsts() 877 // If status is Unblocking, 878 // buffer any instructions coming from rename 879 // continue trying to empty skid buffer 880 // check if stall conditions have passed 881 882 if (dispatchStatus[tid] == Blocked) { 883 ++iewBlockCycles; 884 885 } else if (dispatchStatus[tid] == Squashing) { 886 ++iewSquashCycles; 887 } 888 889 // Dispatch should try to dispatch as many instructions as its bandwidth 890 // will allow, as long as it is not currently blocked. 891 if (dispatchStatus[tid] == Running || 892 dispatchStatus[tid] == Idle) { 893 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 894 "dispatch.\n", tid); 895 896 dispatchInsts(tid); 897 } else if (dispatchStatus[tid] == Unblocking) { 898 // Make sure that the skid buffer has something in it if the 899 // status is unblocking. 900 assert(!skidsEmpty()); 901 902 // If the status was unblocking, then instructions from the skid 903 // buffer were used. Remove those instructions and handle 904 // the rest of unblocking. 905 dispatchInsts(tid); 906 907 ++iewUnblockCycles; 908 909 if (validInstsFromRename() && dispatchedAllInsts) { 910 // Add the current inputs to the skid buffer so they can be 911 // reprocessed when this stage unblocks. 912 skidInsert(tid); 913 } 914 915 unblock(tid); 916 } 917} 918 919template <class Impl> 920void 921DefaultIEW<Impl>::dispatchInsts(unsigned tid) 922{ 923 dispatchedAllInsts = true; 924 925 // Obtain instructions from skid buffer if unblocking, or queue from rename 926 // otherwise. 927 std::queue<DynInstPtr> &insts_to_dispatch = 928 dispatchStatus[tid] == Unblocking ? 929 skidBuffer[tid] : insts[tid]; 930 931 int insts_to_add = insts_to_dispatch.size(); 932 933 DynInstPtr inst; 934 bool add_to_iq = false; 935 int dis_num_inst = 0; 936 937 // Loop through the instructions, putting them in the instruction 938 // queue. 939 for ( ; dis_num_inst < insts_to_add &&
| 574 } 575 576 // Add finished instruction to queue to commit. 577 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 578 (*iewQueue)[wbCycle].size++; 579} 580 581template <class Impl> 582unsigned 583DefaultIEW<Impl>::validInstsFromRename() 584{ 585 unsigned inst_count = 0; 586 587 for (int i=0; i<fromRename->size; i++) { 588 if (!fromRename->insts[i]->isSquashed()) 589 inst_count++; 590 } 591 592 return inst_count; 593} 594 595template<class Impl> 596void 597DefaultIEW<Impl>::skidInsert(unsigned tid) 598{ 599 DynInstPtr inst = NULL; 600 601 while (!insts[tid].empty()) { 602 inst = insts[tid].front(); 603 604 insts[tid].pop(); 605 606 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 607 "dispatch skidBuffer %i\n",tid, inst->seqNum, 608 inst->readPC(),tid); 609 610 skidBuffer[tid].push(inst); 611 } 612 613 assert(skidBuffer[tid].size() <= skidBufferMax && 614 "Skidbuffer Exceeded Max Size"); 615} 616 617template<class Impl> 618int 619DefaultIEW<Impl>::skidCount() 620{ 621 int max=0; 622 623 list<unsigned>::iterator threads = (*activeThreads).begin(); 624 625 while (threads != (*activeThreads).end()) { 626 unsigned thread_count = skidBuffer[*threads++].size(); 627 if (max < thread_count) 628 max = thread_count; 629 } 630 631 return max; 632} 633 634template<class Impl> 635bool 636DefaultIEW<Impl>::skidsEmpty() 637{ 638 list<unsigned>::iterator threads = (*activeThreads).begin(); 639 640 while (threads != (*activeThreads).end()) { 641 if (!skidBuffer[*threads++].empty()) 642 return false; 643 } 644 645 return true; 646} 647 648template <class Impl> 649void 650DefaultIEW<Impl>::updateStatus() 651{ 652 bool any_unblocking = false; 653 654 list<unsigned>::iterator threads = (*activeThreads).begin(); 655 656 threads = (*activeThreads).begin(); 657 658 while (threads != (*activeThreads).end()) { 659 unsigned tid = *threads++; 660 661 if (dispatchStatus[tid] == Unblocking) { 662 any_unblocking = true; 663 break; 664 } 665 } 666 667 // If there are no ready instructions waiting to be scheduled by the IQ, 668 // and there's no stores waiting to write back, and dispatch is not 669 // unblocking, then there is no internal activity for the IEW stage. 670 if (_status == Active && !instQueue.hasReadyInsts() && 671 !ldstQueue.willWB() && !any_unblocking) { 672 DPRINTF(IEW, "IEW switching to idle\n"); 673 674 deactivateStage(); 675 676 _status = Inactive; 677 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 678 ldstQueue.willWB() || 679 any_unblocking)) { 680 // Otherwise there is internal activity. Set to active. 681 DPRINTF(IEW, "IEW switching to active\n"); 682 683 activateStage(); 684 685 _status = Active; 686 } 687} 688 689template <class Impl> 690void 691DefaultIEW<Impl>::resetEntries() 692{ 693 instQueue.resetEntries(); 694 ldstQueue.resetEntries(); 695} 696 697template <class Impl> 698void 699DefaultIEW<Impl>::readStallSignals(unsigned tid) 700{ 701 if (fromCommit->commitBlock[tid]) { 702 stalls[tid].commit = true; 703 } 704 705 if (fromCommit->commitUnblock[tid]) { 706 assert(stalls[tid].commit); 707 stalls[tid].commit = false; 708 } 709} 710 711template <class Impl> 712bool 713DefaultIEW<Impl>::checkStall(unsigned tid) 714{ 715 bool ret_val(false); 716 717 if (stalls[tid].commit) { 718 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 719 ret_val = true; 720 } else if (instQueue.isFull(tid)) { 721 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 722 ret_val = true; 723 } else if (ldstQueue.isFull(tid)) { 724 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 725 726 if (ldstQueue.numLoads(tid) > 0 ) { 727 728 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 729 tid,ldstQueue.getLoadHeadSeqNum(tid)); 730 } 731 732 if (ldstQueue.numStores(tid) > 0) { 733 734 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 735 tid,ldstQueue.getStoreHeadSeqNum(tid)); 736 } 737 738 ret_val = true; 739 } else if (ldstQueue.isStalled(tid)) { 740 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 741 ret_val = true; 742 } 743 744 return ret_val; 745} 746 747template <class Impl> 748void 749DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 750{ 751 // Check if there's a squash signal, squash if there is 752 // Check stall signals, block if there is. 753 // If status was Blocked 754 // if so then go to unblocking 755 // If status was Squashing 756 // check if squashing is not high. Switch to running this cycle. 757 758 readStallSignals(tid); 759 760 if (fromCommit->commitInfo[tid].squash) { 761 squash(tid); 762 763 if (dispatchStatus[tid] == Blocked || 764 dispatchStatus[tid] == Unblocking) { 765 toRename->iewUnblock[tid] = true; 766 wroteToTimeBuffer = true; 767 } 768 769 dispatchStatus[tid] = Squashing; 770 771 fetchRedirect[tid] = false; 772 return; 773 } 774 775 if (fromCommit->commitInfo[tid].robSquashing) { 776 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 777 778 dispatchStatus[tid] = Squashing; 779 780 emptyRenameInsts(tid); 781 wroteToTimeBuffer = true; 782 return; 783 } 784 785 if (checkStall(tid)) { 786 block(tid); 787 dispatchStatus[tid] = Blocked; 788 return; 789 } 790 791 if (dispatchStatus[tid] == Blocked) { 792 // Status from previous cycle was blocked, but there are no more stall 793 // conditions. Switch over to unblocking. 794 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 795 tid); 796 797 dispatchStatus[tid] = Unblocking; 798 799 unblock(tid); 800 801 return; 802 } 803 804 if (dispatchStatus[tid] == Squashing) { 805 // Switch status to running if rename isn't being told to block or 806 // squash this cycle. 807 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 808 tid); 809 810 dispatchStatus[tid] = Running; 811 812 return; 813 } 814} 815 816template <class Impl> 817void 818DefaultIEW<Impl>::sortInsts() 819{ 820 int insts_from_rename = fromRename->size; 821#ifdef DEBUG 822 for (int i = 0; i < numThreads; i++) 823 assert(insts[i].empty()); 824#endif 825 for (int i = 0; i < insts_from_rename; ++i) { 826 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 827 } 828} 829 830template <class Impl> 831void 832DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 833{ 834 while (!insts[tid].empty()) { 835 if (insts[tid].front()->isLoad() || 836 insts[tid].front()->isStore() ) { 837 toRename->iewInfo[tid].dispatchedToLSQ++; 838 } 839 840 toRename->iewInfo[tid].dispatched++; 841 842 insts[tid].pop(); 843 } 844} 845 846template <class Impl> 847void 848DefaultIEW<Impl>::wakeCPU() 849{ 850 cpu->wakeCPU(); 851} 852 853template <class Impl> 854void 855DefaultIEW<Impl>::activityThisCycle() 856{ 857 DPRINTF(Activity, "Activity this cycle.\n"); 858 cpu->activityThisCycle(); 859} 860 861template <class Impl> 862inline void 863DefaultIEW<Impl>::activateStage() 864{ 865 DPRINTF(Activity, "Activating stage.\n"); 866 cpu->activateStage(O3CPU::IEWIdx); 867} 868 869template <class Impl> 870inline void 871DefaultIEW<Impl>::deactivateStage() 872{ 873 DPRINTF(Activity, "Deactivating stage.\n"); 874 cpu->deactivateStage(O3CPU::IEWIdx); 875} 876 877template<class Impl> 878void 879DefaultIEW<Impl>::dispatch(unsigned tid) 880{ 881 // If status is Running or idle, 882 // call dispatchInsts() 883 // If status is Unblocking, 884 // buffer any instructions coming from rename 885 // continue trying to empty skid buffer 886 // check if stall conditions have passed 887 888 if (dispatchStatus[tid] == Blocked) { 889 ++iewBlockCycles; 890 891 } else if (dispatchStatus[tid] == Squashing) { 892 ++iewSquashCycles; 893 } 894 895 // Dispatch should try to dispatch as many instructions as its bandwidth 896 // will allow, as long as it is not currently blocked. 897 if (dispatchStatus[tid] == Running || 898 dispatchStatus[tid] == Idle) { 899 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 900 "dispatch.\n", tid); 901 902 dispatchInsts(tid); 903 } else if (dispatchStatus[tid] == Unblocking) { 904 // Make sure that the skid buffer has something in it if the 905 // status is unblocking. 906 assert(!skidsEmpty()); 907 908 // If the status was unblocking, then instructions from the skid 909 // buffer were used. Remove those instructions and handle 910 // the rest of unblocking. 911 dispatchInsts(tid); 912 913 ++iewUnblockCycles; 914 915 if (validInstsFromRename() && dispatchedAllInsts) { 916 // Add the current inputs to the skid buffer so they can be 917 // reprocessed when this stage unblocks. 918 skidInsert(tid); 919 } 920 921 unblock(tid); 922 } 923} 924 925template <class Impl> 926void 927DefaultIEW<Impl>::dispatchInsts(unsigned tid) 928{ 929 dispatchedAllInsts = true; 930 931 // Obtain instructions from skid buffer if unblocking, or queue from rename 932 // otherwise. 933 std::queue<DynInstPtr> &insts_to_dispatch = 934 dispatchStatus[tid] == Unblocking ? 935 skidBuffer[tid] : insts[tid]; 936 937 int insts_to_add = insts_to_dispatch.size(); 938 939 DynInstPtr inst; 940 bool add_to_iq = false; 941 int dis_num_inst = 0; 942 943 // Loop through the instructions, putting them in the instruction 944 // queue. 945 for ( ; dis_num_inst < insts_to_add &&
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940 dis_num_inst < issueReadWidth;
| 946 dis_num_inst < dispatchWidth;
|
941 ++dis_num_inst) 942 { 943 inst = insts_to_dispatch.front(); 944 945 if (dispatchStatus[tid] == Unblocking) { 946 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 947 "buffer\n", tid); 948 } 949 950 // Make sure there's a valid instruction there. 951 assert(inst); 952 953 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 954 "IQ.\n", 955 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 956 957 // Be sure to mark these instructions as ready so that the 958 // commit stage can go ahead and execute them, and mark 959 // them as issued so the IQ doesn't reprocess them. 960 961 // Check for squashed instructions. 962 if (inst->isSquashed()) { 963 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 964 "not adding to IQ.\n", tid); 965 966 ++iewDispSquashedInsts; 967 968 insts_to_dispatch.pop(); 969 970 //Tell Rename That An Instruction has been processed 971 if (inst->isLoad() || inst->isStore()) { 972 toRename->iewInfo[tid].dispatchedToLSQ++; 973 } 974 toRename->iewInfo[tid].dispatched++; 975 976 continue; 977 } 978 979 // Check for full conditions. 980 if (instQueue.isFull(tid)) { 981 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 982 983 // Call function to start blocking. 984 block(tid); 985 986 // Set unblock to false. Special case where we are using 987 // skidbuffer (unblocking) instructions but then we still 988 // get full in the IQ. 989 toRename->iewUnblock[tid] = false; 990 991 dispatchedAllInsts = false; 992 993 ++iewIQFullEvents; 994 break; 995 } else if (ldstQueue.isFull(tid)) { 996 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 997 998 // Call function to start blocking. 999 block(tid); 1000 1001 // Set unblock to false. Special case where we are using 1002 // skidbuffer (unblocking) instructions but then we still 1003 // get full in the IQ. 1004 toRename->iewUnblock[tid] = false; 1005 1006 dispatchedAllInsts = false; 1007 1008 ++iewLSQFullEvents; 1009 break; 1010 } 1011 1012 // Otherwise issue the instruction just fine. 1013 if (inst->isLoad()) { 1014 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1015 "encountered, adding to LSQ.\n", tid); 1016 1017 // Reserve a spot in the load store queue for this 1018 // memory access. 1019 ldstQueue.insertLoad(inst); 1020 1021 ++iewDispLoadInsts; 1022 1023 add_to_iq = true; 1024 1025 toRename->iewInfo[tid].dispatchedToLSQ++; 1026 } else if (inst->isStore()) { 1027 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1028 "encountered, adding to LSQ.\n", tid); 1029 1030 ldstQueue.insertStore(inst); 1031 1032 ++iewDispStoreInsts; 1033 1034 if (inst->isStoreConditional()) { 1035 // Store conditionals need to be set as "canCommit()" 1036 // so that commit can process them when they reach the 1037 // head of commit. 1038 // @todo: This is somewhat specific to Alpha. 1039 inst->setCanCommit(); 1040 instQueue.insertNonSpec(inst); 1041 add_to_iq = false; 1042 1043 ++iewDispNonSpecInsts; 1044 } else { 1045 add_to_iq = true; 1046 } 1047 1048 toRename->iewInfo[tid].dispatchedToLSQ++; 1049#if FULL_SYSTEM 1050 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1051 // Same as non-speculative stores. 1052 inst->setCanCommit(); 1053 instQueue.insertBarrier(inst); 1054 add_to_iq = false; 1055#endif 1056 } else if (inst->isNonSpeculative()) { 1057 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1058 "encountered, skipping.\n", tid); 1059 1060 // Same as non-speculative stores. 1061 inst->setCanCommit(); 1062 1063 // Specifically insert it as nonspeculative. 1064 instQueue.insertNonSpec(inst); 1065 1066 ++iewDispNonSpecInsts; 1067 1068 add_to_iq = false; 1069 } else if (inst->isNop()) { 1070 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1071 "skipping.\n", tid); 1072 1073 inst->setIssued(); 1074 inst->setExecuted(); 1075 inst->setCanCommit(); 1076 1077 instQueue.recordProducer(inst); 1078 1079 iewExecutedNop[tid]++; 1080 1081 add_to_iq = false; 1082 } else if (inst->isExecuted()) { 1083 assert(0 && "Instruction shouldn't be executed.\n"); 1084 DPRINTF(IEW, "Issue: Executed branch encountered, " 1085 "skipping.\n"); 1086 1087 inst->setIssued(); 1088 inst->setCanCommit(); 1089 1090 instQueue.recordProducer(inst); 1091 1092 add_to_iq = false; 1093 } else { 1094 add_to_iq = true; 1095 } 1096 1097 // If the instruction queue is not full, then add the 1098 // instruction. 1099 if (add_to_iq) { 1100 instQueue.insert(inst); 1101 } 1102 1103 insts_to_dispatch.pop(); 1104 1105 toRename->iewInfo[tid].dispatched++; 1106 1107 ++iewDispatchedInsts; 1108 } 1109 1110 if (!insts_to_dispatch.empty()) { 1111 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 1112 block(tid); 1113 toRename->iewUnblock[tid] = false; 1114 } 1115 1116 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1117 dispatchStatus[tid] = Running; 1118 1119 updatedQueues = true; 1120 } 1121 1122 dis_num_inst = 0; 1123} 1124 1125template <class Impl> 1126void 1127DefaultIEW<Impl>::printAvailableInsts() 1128{ 1129 int inst = 0; 1130 1131 cout << "Available Instructions: "; 1132 1133 while (fromIssue->insts[inst]) { 1134 1135 if (inst%3==0) cout << "\n\t"; 1136 1137 cout << "PC: " << fromIssue->insts[inst]->readPC() 1138 << " TN: " << fromIssue->insts[inst]->threadNumber 1139 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1140 1141 inst++; 1142 1143 } 1144 1145 cout << "\n"; 1146} 1147 1148template <class Impl> 1149void 1150DefaultIEW<Impl>::executeInsts() 1151{ 1152 wbNumInst = 0; 1153 wbCycle = 0; 1154 1155 list<unsigned>::iterator threads = (*activeThreads).begin(); 1156 1157 while (threads != (*activeThreads).end()) { 1158 unsigned tid = *threads++; 1159 fetchRedirect[tid] = false; 1160 } 1161 1162 // Uncomment this if you want to see all available instructions. 1163// printAvailableInsts(); 1164 1165 // Execute/writeback any instructions that are available. 1166 int insts_to_execute = fromIssue->size; 1167 int inst_num = 0; 1168 for (; inst_num < insts_to_execute; 1169 ++inst_num) { 1170 1171 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1172 1173 DynInstPtr inst = instQueue.getInstToExecute(); 1174 1175 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1176 inst->readPC(), inst->threadNumber,inst->seqNum); 1177 1178 // Check if the instruction is squashed; if so then skip it 1179 if (inst->isSquashed()) { 1180 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1181 1182 // Consider this instruction executed so that commit can go 1183 // ahead and retire the instruction. 1184 inst->setExecuted(); 1185 1186 // Not sure if I should set this here or just let commit try to 1187 // commit any squashed instructions. I like the latter a bit more. 1188 inst->setCanCommit(); 1189 1190 ++iewExecSquashedInsts; 1191
| 947 ++dis_num_inst) 948 { 949 inst = insts_to_dispatch.front(); 950 951 if (dispatchStatus[tid] == Unblocking) { 952 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 953 "buffer\n", tid); 954 } 955 956 // Make sure there's a valid instruction there. 957 assert(inst); 958 959 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 960 "IQ.\n", 961 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 962 963 // Be sure to mark these instructions as ready so that the 964 // commit stage can go ahead and execute them, and mark 965 // them as issued so the IQ doesn't reprocess them. 966 967 // Check for squashed instructions. 968 if (inst->isSquashed()) { 969 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 970 "not adding to IQ.\n", tid); 971 972 ++iewDispSquashedInsts; 973 974 insts_to_dispatch.pop(); 975 976 //Tell Rename That An Instruction has been processed 977 if (inst->isLoad() || inst->isStore()) { 978 toRename->iewInfo[tid].dispatchedToLSQ++; 979 } 980 toRename->iewInfo[tid].dispatched++; 981 982 continue; 983 } 984 985 // Check for full conditions. 986 if (instQueue.isFull(tid)) { 987 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 988 989 // Call function to start blocking. 990 block(tid); 991 992 // Set unblock to false. Special case where we are using 993 // skidbuffer (unblocking) instructions but then we still 994 // get full in the IQ. 995 toRename->iewUnblock[tid] = false; 996 997 dispatchedAllInsts = false; 998 999 ++iewIQFullEvents; 1000 break; 1001 } else if (ldstQueue.isFull(tid)) { 1002 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1003 1004 // Call function to start blocking. 1005 block(tid); 1006 1007 // Set unblock to false. Special case where we are using 1008 // skidbuffer (unblocking) instructions but then we still 1009 // get full in the IQ. 1010 toRename->iewUnblock[tid] = false; 1011 1012 dispatchedAllInsts = false; 1013 1014 ++iewLSQFullEvents; 1015 break; 1016 } 1017 1018 // Otherwise issue the instruction just fine. 1019 if (inst->isLoad()) { 1020 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1021 "encountered, adding to LSQ.\n", tid); 1022 1023 // Reserve a spot in the load store queue for this 1024 // memory access. 1025 ldstQueue.insertLoad(inst); 1026 1027 ++iewDispLoadInsts; 1028 1029 add_to_iq = true; 1030 1031 toRename->iewInfo[tid].dispatchedToLSQ++; 1032 } else if (inst->isStore()) { 1033 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1034 "encountered, adding to LSQ.\n", tid); 1035 1036 ldstQueue.insertStore(inst); 1037 1038 ++iewDispStoreInsts; 1039 1040 if (inst->isStoreConditional()) { 1041 // Store conditionals need to be set as "canCommit()" 1042 // so that commit can process them when they reach the 1043 // head of commit. 1044 // @todo: This is somewhat specific to Alpha. 1045 inst->setCanCommit(); 1046 instQueue.insertNonSpec(inst); 1047 add_to_iq = false; 1048 1049 ++iewDispNonSpecInsts; 1050 } else { 1051 add_to_iq = true; 1052 } 1053 1054 toRename->iewInfo[tid].dispatchedToLSQ++; 1055#if FULL_SYSTEM 1056 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1057 // Same as non-speculative stores. 1058 inst->setCanCommit(); 1059 instQueue.insertBarrier(inst); 1060 add_to_iq = false; 1061#endif 1062 } else if (inst->isNonSpeculative()) { 1063 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1064 "encountered, skipping.\n", tid); 1065 1066 // Same as non-speculative stores. 1067 inst->setCanCommit(); 1068 1069 // Specifically insert it as nonspeculative. 1070 instQueue.insertNonSpec(inst); 1071 1072 ++iewDispNonSpecInsts; 1073 1074 add_to_iq = false; 1075 } else if (inst->isNop()) { 1076 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1077 "skipping.\n", tid); 1078 1079 inst->setIssued(); 1080 inst->setExecuted(); 1081 inst->setCanCommit(); 1082 1083 instQueue.recordProducer(inst); 1084 1085 iewExecutedNop[tid]++; 1086 1087 add_to_iq = false; 1088 } else if (inst->isExecuted()) { 1089 assert(0 && "Instruction shouldn't be executed.\n"); 1090 DPRINTF(IEW, "Issue: Executed branch encountered, " 1091 "skipping.\n"); 1092 1093 inst->setIssued(); 1094 inst->setCanCommit(); 1095 1096 instQueue.recordProducer(inst); 1097 1098 add_to_iq = false; 1099 } else { 1100 add_to_iq = true; 1101 } 1102 1103 // If the instruction queue is not full, then add the 1104 // instruction. 1105 if (add_to_iq) { 1106 instQueue.insert(inst); 1107 } 1108 1109 insts_to_dispatch.pop(); 1110 1111 toRename->iewInfo[tid].dispatched++; 1112 1113 ++iewDispatchedInsts; 1114 } 1115 1116 if (!insts_to_dispatch.empty()) { 1117 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 1118 block(tid); 1119 toRename->iewUnblock[tid] = false; 1120 } 1121 1122 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1123 dispatchStatus[tid] = Running; 1124 1125 updatedQueues = true; 1126 } 1127 1128 dis_num_inst = 0; 1129} 1130 1131template <class Impl> 1132void 1133DefaultIEW<Impl>::printAvailableInsts() 1134{ 1135 int inst = 0; 1136 1137 cout << "Available Instructions: "; 1138 1139 while (fromIssue->insts[inst]) { 1140 1141 if (inst%3==0) cout << "\n\t"; 1142 1143 cout << "PC: " << fromIssue->insts[inst]->readPC() 1144 << " TN: " << fromIssue->insts[inst]->threadNumber 1145 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1146 1147 inst++; 1148 1149 } 1150 1151 cout << "\n"; 1152} 1153 1154template <class Impl> 1155void 1156DefaultIEW<Impl>::executeInsts() 1157{ 1158 wbNumInst = 0; 1159 wbCycle = 0; 1160 1161 list<unsigned>::iterator threads = (*activeThreads).begin(); 1162 1163 while (threads != (*activeThreads).end()) { 1164 unsigned tid = *threads++; 1165 fetchRedirect[tid] = false; 1166 } 1167 1168 // Uncomment this if you want to see all available instructions. 1169// printAvailableInsts(); 1170 1171 // Execute/writeback any instructions that are available. 1172 int insts_to_execute = fromIssue->size; 1173 int inst_num = 0; 1174 for (; inst_num < insts_to_execute; 1175 ++inst_num) { 1176 1177 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1178 1179 DynInstPtr inst = instQueue.getInstToExecute(); 1180 1181 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1182 inst->readPC(), inst->threadNumber,inst->seqNum); 1183 1184 // Check if the instruction is squashed; if so then skip it 1185 if (inst->isSquashed()) { 1186 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1187 1188 // Consider this instruction executed so that commit can go 1189 // ahead and retire the instruction. 1190 inst->setExecuted(); 1191 1192 // Not sure if I should set this here or just let commit try to 1193 // commit any squashed instructions. I like the latter a bit more. 1194 inst->setCanCommit(); 1195 1196 ++iewExecSquashedInsts; 1197
|
| 1198 decrWb(inst->seqNum);
|
1192 continue; 1193 } 1194 1195 Fault fault = NoFault; 1196 1197 // Execute instruction. 1198 // Note that if the instruction faults, it will be handled 1199 // at the commit stage. 1200 if (inst->isMemRef() && 1201 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1202 DPRINTF(IEW, "Execute: Calculating address for memory " 1203 "reference.\n"); 1204 1205 // Tell the LDSTQ to execute this instruction (if it is a load). 1206 if (inst->isLoad()) { 1207 // Loads will mark themselves as executed, and their writeback 1208 // event adds the instruction to the queue to commit 1209 fault = ldstQueue.executeLoad(inst); 1210 } else if (inst->isStore()) { 1211 ldstQueue.executeStore(inst); 1212 1213 // If the store had a fault then it may not have a mem req 1214 if (inst->req && !(inst->req->getFlags() & LOCKED)) { 1215 inst->setExecuted(); 1216 1217 instToCommit(inst); 1218 } 1219 1220 // Store conditionals will mark themselves as 1221 // executed, and their writeback event will add the 1222 // instruction to the queue to commit. 1223 } else { 1224 panic("Unexpected memory type!\n"); 1225 } 1226 1227 } else { 1228 inst->execute(); 1229 1230 inst->setExecuted(); 1231 1232 instToCommit(inst); 1233 } 1234 1235 updateExeInstStats(inst); 1236 1237 // Check if branch prediction was correct, if not then we need 1238 // to tell commit to squash in flight instructions. Only 1239 // handle this if there hasn't already been something that 1240 // redirects fetch in this group of instructions. 1241 1242 // This probably needs to prioritize the redirects if a different 1243 // scheduler is used. Currently the scheduler schedules the oldest 1244 // instruction first, so the branch resolution order will be correct. 1245 unsigned tid = inst->threadNumber; 1246 1247 if (!fetchRedirect[tid]) { 1248 1249 if (inst->mispredicted()) { 1250 fetchRedirect[tid] = true; 1251 1252 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1253 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1254 inst->nextPC); 1255 1256 // If incorrect, then signal the ROB that it must be squashed. 1257 squashDueToBranch(inst, tid); 1258 1259 if (inst->predTaken()) { 1260 predictedTakenIncorrect++; 1261 } else { 1262 predictedNotTakenIncorrect++; 1263 } 1264 } else if (ldstQueue.violation(tid)) { 1265 fetchRedirect[tid] = true; 1266 1267 // If there was an ordering violation, then get the 1268 // DynInst that caused the violation. Note that this 1269 // clears the violation signal. 1270 DynInstPtr violator; 1271 violator = ldstQueue.getMemDepViolator(tid); 1272 1273 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1274 "%#x, inst PC: %#x. Addr is: %#x.\n", 1275 violator->readPC(), inst->readPC(), inst->physEffAddr); 1276 1277 // Tell the instruction queue that a violation has occured. 1278 instQueue.violation(inst, violator); 1279 1280 // Squash. 1281 squashDueToMemOrder(inst,tid); 1282 1283 ++memOrderViolationEvents; 1284 } else if (ldstQueue.loadBlocked(tid) && 1285 !ldstQueue.isLoadBlockedHandled(tid)) { 1286 fetchRedirect[tid] = true; 1287 1288 DPRINTF(IEW, "Load operation couldn't execute because the " 1289 "memory system is blocked. PC: %#x [sn:%lli]\n", 1290 inst->readPC(), inst->seqNum); 1291 1292 squashDueToMemBlocked(inst, tid); 1293 } 1294 } 1295 } 1296 1297 // Update and record activity if we processed any instructions. 1298 if (inst_num) { 1299 if (exeStatus == Idle) { 1300 exeStatus = Running; 1301 } 1302 1303 updatedQueues = true; 1304 1305 cpu->activityThisCycle(); 1306 } 1307 1308 // Need to reset this in case a writeback event needs to write into the 1309 // iew queue. That way the writeback event will write into the correct 1310 // spot in the queue. 1311 wbNumInst = 0; 1312} 1313 1314template <class Impl> 1315void 1316DefaultIEW<Impl>::writebackInsts() 1317{ 1318 // Loop through the head of the time buffer and wake any 1319 // dependents. These instructions are about to write back. Also 1320 // mark scoreboard that this instruction is finally complete. 1321 // Either have IEW have direct access to scoreboard, or have this 1322 // as part of backwards communication. 1323 for (int inst_num = 0; inst_num < issueWidth && 1324 toCommit->insts[inst_num]; inst_num++) { 1325 DynInstPtr inst = toCommit->insts[inst_num]; 1326 int tid = inst->threadNumber; 1327 1328 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1329 inst->seqNum, inst->readPC()); 1330 1331 iewInstsToCommit[tid]++; 1332 1333 // Some instructions will be sent to commit without having 1334 // executed because they need commit to handle them. 1335 // E.g. Uncached loads have not actually executed when they 1336 // are first sent to commit. Instead commit must tell the LSQ 1337 // when it's ready to execute the uncached load. 1338 if (!inst->isSquashed() && inst->isExecuted()) { 1339 int dependents = instQueue.wakeDependents(inst); 1340 1341 for (int i = 0; i < inst->numDestRegs(); i++) { 1342 //mark as Ready 1343 DPRINTF(IEW,"Setting Destination Register %i\n", 1344 inst->renamedDestRegIdx(i)); 1345 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1346 } 1347 1348 if (dependents) { 1349 producerInst[tid]++; 1350 consumerInst[tid]+= dependents; 1351 } 1352 writebackCount[tid]++; 1353 }
| 1199 continue; 1200 } 1201 1202 Fault fault = NoFault; 1203 1204 // Execute instruction. 1205 // Note that if the instruction faults, it will be handled 1206 // at the commit stage. 1207 if (inst->isMemRef() && 1208 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1209 DPRINTF(IEW, "Execute: Calculating address for memory " 1210 "reference.\n"); 1211 1212 // Tell the LDSTQ to execute this instruction (if it is a load). 1213 if (inst->isLoad()) { 1214 // Loads will mark themselves as executed, and their writeback 1215 // event adds the instruction to the queue to commit 1216 fault = ldstQueue.executeLoad(inst); 1217 } else if (inst->isStore()) { 1218 ldstQueue.executeStore(inst); 1219 1220 // If the store had a fault then it may not have a mem req 1221 if (inst->req && !(inst->req->getFlags() & LOCKED)) { 1222 inst->setExecuted(); 1223 1224 instToCommit(inst); 1225 } 1226 1227 // Store conditionals will mark themselves as 1228 // executed, and their writeback event will add the 1229 // instruction to the queue to commit. 1230 } else { 1231 panic("Unexpected memory type!\n"); 1232 } 1233 1234 } else { 1235 inst->execute(); 1236 1237 inst->setExecuted(); 1238 1239 instToCommit(inst); 1240 } 1241 1242 updateExeInstStats(inst); 1243 1244 // Check if branch prediction was correct, if not then we need 1245 // to tell commit to squash in flight instructions. Only 1246 // handle this if there hasn't already been something that 1247 // redirects fetch in this group of instructions. 1248 1249 // This probably needs to prioritize the redirects if a different 1250 // scheduler is used. Currently the scheduler schedules the oldest 1251 // instruction first, so the branch resolution order will be correct. 1252 unsigned tid = inst->threadNumber; 1253 1254 if (!fetchRedirect[tid]) { 1255 1256 if (inst->mispredicted()) { 1257 fetchRedirect[tid] = true; 1258 1259 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1260 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1261 inst->nextPC); 1262 1263 // If incorrect, then signal the ROB that it must be squashed. 1264 squashDueToBranch(inst, tid); 1265 1266 if (inst->predTaken()) { 1267 predictedTakenIncorrect++; 1268 } else { 1269 predictedNotTakenIncorrect++; 1270 } 1271 } else if (ldstQueue.violation(tid)) { 1272 fetchRedirect[tid] = true; 1273 1274 // If there was an ordering violation, then get the 1275 // DynInst that caused the violation. Note that this 1276 // clears the violation signal. 1277 DynInstPtr violator; 1278 violator = ldstQueue.getMemDepViolator(tid); 1279 1280 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1281 "%#x, inst PC: %#x. Addr is: %#x.\n", 1282 violator->readPC(), inst->readPC(), inst->physEffAddr); 1283 1284 // Tell the instruction queue that a violation has occured. 1285 instQueue.violation(inst, violator); 1286 1287 // Squash. 1288 squashDueToMemOrder(inst,tid); 1289 1290 ++memOrderViolationEvents; 1291 } else if (ldstQueue.loadBlocked(tid) && 1292 !ldstQueue.isLoadBlockedHandled(tid)) { 1293 fetchRedirect[tid] = true; 1294 1295 DPRINTF(IEW, "Load operation couldn't execute because the " 1296 "memory system is blocked. PC: %#x [sn:%lli]\n", 1297 inst->readPC(), inst->seqNum); 1298 1299 squashDueToMemBlocked(inst, tid); 1300 } 1301 } 1302 } 1303 1304 // Update and record activity if we processed any instructions. 1305 if (inst_num) { 1306 if (exeStatus == Idle) { 1307 exeStatus = Running; 1308 } 1309 1310 updatedQueues = true; 1311 1312 cpu->activityThisCycle(); 1313 } 1314 1315 // Need to reset this in case a writeback event needs to write into the 1316 // iew queue. That way the writeback event will write into the correct 1317 // spot in the queue. 1318 wbNumInst = 0; 1319} 1320 1321template <class Impl> 1322void 1323DefaultIEW<Impl>::writebackInsts() 1324{ 1325 // Loop through the head of the time buffer and wake any 1326 // dependents. These instructions are about to write back. Also 1327 // mark scoreboard that this instruction is finally complete. 1328 // Either have IEW have direct access to scoreboard, or have this 1329 // as part of backwards communication. 1330 for (int inst_num = 0; inst_num < issueWidth && 1331 toCommit->insts[inst_num]; inst_num++) { 1332 DynInstPtr inst = toCommit->insts[inst_num]; 1333 int tid = inst->threadNumber; 1334 1335 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1336 inst->seqNum, inst->readPC()); 1337 1338 iewInstsToCommit[tid]++; 1339 1340 // Some instructions will be sent to commit without having 1341 // executed because they need commit to handle them. 1342 // E.g. Uncached loads have not actually executed when they 1343 // are first sent to commit. Instead commit must tell the LSQ 1344 // when it's ready to execute the uncached load. 1345 if (!inst->isSquashed() && inst->isExecuted()) { 1346 int dependents = instQueue.wakeDependents(inst); 1347 1348 for (int i = 0; i < inst->numDestRegs(); i++) { 1349 //mark as Ready 1350 DPRINTF(IEW,"Setting Destination Register %i\n", 1351 inst->renamedDestRegIdx(i)); 1352 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1353 } 1354 1355 if (dependents) { 1356 producerInst[tid]++; 1357 consumerInst[tid]+= dependents; 1358 } 1359 writebackCount[tid]++; 1360 }
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| 1361 1362 decrWb(inst->seqNum);
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1354 } 1355} 1356 1357template<class Impl> 1358void 1359DefaultIEW<Impl>::tick() 1360{ 1361 wbNumInst = 0; 1362 wbCycle = 0; 1363 1364 wroteToTimeBuffer = false; 1365 updatedQueues = false; 1366 1367 sortInsts(); 1368 1369 // Free function units marked as being freed this cycle. 1370 fuPool->processFreeUnits(); 1371 1372 list<unsigned>::iterator threads = (*activeThreads).begin(); 1373 1374 // Check stall and squash signals, dispatch any instructions. 1375 while (threads != (*activeThreads).end()) { 1376 unsigned tid = *threads++; 1377 1378 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1379 1380 checkSignalsAndUpdate(tid); 1381 dispatch(tid); 1382 } 1383 1384 if (exeStatus != Squashing) { 1385 executeInsts(); 1386 1387 writebackInsts(); 1388 1389 // Have the instruction queue try to schedule any ready instructions. 1390 // (In actuality, this scheduling is for instructions that will 1391 // be executed next cycle.) 1392 instQueue.scheduleReadyInsts(); 1393 1394 // Also should advance its own time buffers if the stage ran. 1395 // Not the best place for it, but this works (hopefully). 1396 issueToExecQueue.advance(); 1397 } 1398 1399 bool broadcast_free_entries = false; 1400 1401 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1402 exeStatus = Idle; 1403 updateLSQNextCycle = false; 1404 1405 broadcast_free_entries = true; 1406 } 1407 1408 // Writeback any stores using any leftover bandwidth. 1409 ldstQueue.writebackStores(); 1410 1411 // Check the committed load/store signals to see if there's a load 1412 // or store to commit. Also check if it's being told to execute a 1413 // nonspeculative instruction. 1414 // This is pretty inefficient... 1415 1416 threads = (*activeThreads).begin(); 1417 while (threads != (*activeThreads).end()) { 1418 unsigned tid = (*threads++); 1419 1420 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1421 1422 // Update structures based on instructions committed. 1423 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1424 !fromCommit->commitInfo[tid].squash && 1425 !fromCommit->commitInfo[tid].robSquashing) { 1426 1427 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1428 1429 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1430 1431 updateLSQNextCycle = true; 1432 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1433 } 1434 1435 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1436 1437 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1438 if (fromCommit->commitInfo[tid].uncached) { 1439 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1440 } else { 1441 instQueue.scheduleNonSpec( 1442 fromCommit->commitInfo[tid].nonSpecSeqNum); 1443 } 1444 } 1445 1446 if (broadcast_free_entries) { 1447 toFetch->iewInfo[tid].iqCount = 1448 instQueue.getCount(tid); 1449 toFetch->iewInfo[tid].ldstqCount = 1450 ldstQueue.getCount(tid); 1451 1452 toRename->iewInfo[tid].usedIQ = true; 1453 toRename->iewInfo[tid].freeIQEntries = 1454 instQueue.numFreeEntries(); 1455 toRename->iewInfo[tid].usedLSQ = true; 1456 toRename->iewInfo[tid].freeLSQEntries = 1457 ldstQueue.numFreeEntries(tid); 1458 1459 wroteToTimeBuffer = true; 1460 } 1461 1462 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1463 tid, toRename->iewInfo[tid].dispatched); 1464 } 1465 1466 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1467 "LSQ has %i free entries.\n", 1468 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1469 ldstQueue.numFreeEntries()); 1470 1471 updateStatus(); 1472 1473 if (wroteToTimeBuffer) { 1474 DPRINTF(Activity, "Activity this cycle.\n"); 1475 cpu->activityThisCycle(); 1476 } 1477} 1478 1479template <class Impl> 1480void 1481DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1482{ 1483 int thread_number = inst->threadNumber; 1484 1485 // 1486 // Pick off the software prefetches 1487 // 1488#ifdef TARGET_ALPHA 1489 if (inst->isDataPrefetch()) 1490 iewExecutedSwp[thread_number]++; 1491 else 1492 iewIewExecutedcutedInsts++; 1493#else 1494 iewExecutedInsts++; 1495#endif 1496 1497 // 1498 // Control operations 1499 // 1500 if (inst->isControl()) 1501 iewExecutedBranches[thread_number]++; 1502 1503 // 1504 // Memory operations 1505 // 1506 if (inst->isMemRef()) { 1507 iewExecutedRefs[thread_number]++; 1508 1509 if (inst->isLoad()) { 1510 iewExecLoadInsts[thread_number]++; 1511 } 1512 } 1513}
| 1363 } 1364} 1365 1366template<class Impl> 1367void 1368DefaultIEW<Impl>::tick() 1369{ 1370 wbNumInst = 0; 1371 wbCycle = 0; 1372 1373 wroteToTimeBuffer = false; 1374 updatedQueues = false; 1375 1376 sortInsts(); 1377 1378 // Free function units marked as being freed this cycle. 1379 fuPool->processFreeUnits(); 1380 1381 list<unsigned>::iterator threads = (*activeThreads).begin(); 1382 1383 // Check stall and squash signals, dispatch any instructions. 1384 while (threads != (*activeThreads).end()) { 1385 unsigned tid = *threads++; 1386 1387 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1388 1389 checkSignalsAndUpdate(tid); 1390 dispatch(tid); 1391 } 1392 1393 if (exeStatus != Squashing) { 1394 executeInsts(); 1395 1396 writebackInsts(); 1397 1398 // Have the instruction queue try to schedule any ready instructions. 1399 // (In actuality, this scheduling is for instructions that will 1400 // be executed next cycle.) 1401 instQueue.scheduleReadyInsts(); 1402 1403 // Also should advance its own time buffers if the stage ran. 1404 // Not the best place for it, but this works (hopefully). 1405 issueToExecQueue.advance(); 1406 } 1407 1408 bool broadcast_free_entries = false; 1409 1410 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1411 exeStatus = Idle; 1412 updateLSQNextCycle = false; 1413 1414 broadcast_free_entries = true; 1415 } 1416 1417 // Writeback any stores using any leftover bandwidth. 1418 ldstQueue.writebackStores(); 1419 1420 // Check the committed load/store signals to see if there's a load 1421 // or store to commit. Also check if it's being told to execute a 1422 // nonspeculative instruction. 1423 // This is pretty inefficient... 1424 1425 threads = (*activeThreads).begin(); 1426 while (threads != (*activeThreads).end()) { 1427 unsigned tid = (*threads++); 1428 1429 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1430 1431 // Update structures based on instructions committed. 1432 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1433 !fromCommit->commitInfo[tid].squash && 1434 !fromCommit->commitInfo[tid].robSquashing) { 1435 1436 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1437 1438 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1439 1440 updateLSQNextCycle = true; 1441 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1442 } 1443 1444 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1445 1446 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1447 if (fromCommit->commitInfo[tid].uncached) { 1448 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1449 } else { 1450 instQueue.scheduleNonSpec( 1451 fromCommit->commitInfo[tid].nonSpecSeqNum); 1452 } 1453 } 1454 1455 if (broadcast_free_entries) { 1456 toFetch->iewInfo[tid].iqCount = 1457 instQueue.getCount(tid); 1458 toFetch->iewInfo[tid].ldstqCount = 1459 ldstQueue.getCount(tid); 1460 1461 toRename->iewInfo[tid].usedIQ = true; 1462 toRename->iewInfo[tid].freeIQEntries = 1463 instQueue.numFreeEntries(); 1464 toRename->iewInfo[tid].usedLSQ = true; 1465 toRename->iewInfo[tid].freeLSQEntries = 1466 ldstQueue.numFreeEntries(tid); 1467 1468 wroteToTimeBuffer = true; 1469 } 1470 1471 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1472 tid, toRename->iewInfo[tid].dispatched); 1473 } 1474 1475 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1476 "LSQ has %i free entries.\n", 1477 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1478 ldstQueue.numFreeEntries()); 1479 1480 updateStatus(); 1481 1482 if (wroteToTimeBuffer) { 1483 DPRINTF(Activity, "Activity this cycle.\n"); 1484 cpu->activityThisCycle(); 1485 } 1486} 1487 1488template <class Impl> 1489void 1490DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1491{ 1492 int thread_number = inst->threadNumber; 1493 1494 // 1495 // Pick off the software prefetches 1496 // 1497#ifdef TARGET_ALPHA 1498 if (inst->isDataPrefetch()) 1499 iewExecutedSwp[thread_number]++; 1500 else 1501 iewIewExecutedcutedInsts++; 1502#else 1503 iewExecutedInsts++; 1504#endif 1505 1506 // 1507 // Control operations 1508 // 1509 if (inst->isControl()) 1510 iewExecutedBranches[thread_number]++; 1511 1512 // 1513 // Memory operations 1514 // 1515 if (inst->isMemRef()) { 1516 iewExecutedRefs[thread_number]++; 1517 1518 if (inst->isLoad()) { 1519 iewExecLoadInsts[thread_number]++; 1520 } 1521 } 1522}
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