1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 issueReadWidth(params->issueWidth),
54 issueWidth(params->issueWidth),
55 executeWidth(params->executeWidth),
56 numThreads(params->numberOfThreads),
57 switchedOut(false)
58{
59 _status = Active;
60 exeStatus = Running;
61 wbStatus = Idle;
62
63 // Setup wire to read instructions coming from issue.
64 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66 // Instruction queue needs the queue between issue and execute.
67 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69 instQueue.setIEW(this);
70 ldstQueue.setIEW(this);
71
72 for (int i=0; i < numThreads; i++) {
73 dispatchStatus[i] = Running;
74 stalls[i].commit = false;
75 fetchRedirect[i] = false;
76 }
77
78 updateLSQNextCycle = false;
79
80 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
81}
82
83template <class Impl>
84std::string
85DefaultIEW<Impl>::name() const
86{
87 return cpu->name() + ".iew";
88}
89
90template <class Impl>
91void
92DefaultIEW<Impl>::regStats()
93{
94 using namespace Stats;
95
96 instQueue.regStats();
97
98 iewIdleCycles
99 .name(name() + ".iewIdleCycles")
100 .desc("Number of cycles IEW is idle");
101
102 iewSquashCycles
103 .name(name() + ".iewSquashCycles")
104 .desc("Number of cycles IEW is squashing");
105
106 iewBlockCycles
107 .name(name() + ".iewBlockCycles")
108 .desc("Number of cycles IEW is blocking");
109
110 iewUnblockCycles
111 .name(name() + ".iewUnblockCycles")
112 .desc("Number of cycles IEW is unblocking");
113
114 iewDispatchedInsts
115 .name(name() + ".iewDispatchedInsts")
116 .desc("Number of instructions dispatched to IQ");
117
118 iewDispSquashedInsts
119 .name(name() + ".iewDispSquashedInsts")
120 .desc("Number of squashed instructions skipped by dispatch");
121
122 iewDispLoadInsts
123 .name(name() + ".iewDispLoadInsts")
124 .desc("Number of dispatched load instructions");
125
126 iewDispStoreInsts
127 .name(name() + ".iewDispStoreInsts")
128 .desc("Number of dispatched store instructions");
129
130 iewDispNonSpecInsts
131 .name(name() + ".iewDispNonSpecInsts")
132 .desc("Number of dispatched non-speculative instructions");
133
134 iewIQFullEvents
135 .name(name() + ".iewIQFullEvents")
136 .desc("Number of times the IQ has become full, causing a stall");
137
138 iewLSQFullEvents
139 .name(name() + ".iewLSQFullEvents")
140 .desc("Number of times the LSQ has become full, causing a stall");
141
142 iewExecutedInsts
143 .name(name() + ".iewExecutedInsts")
144 .desc("Number of executed instructions");
145
146 iewExecLoadInsts
147 .init(cpu->number_of_threads)
148 .name(name() + ".iewExecLoadInsts")
149 .desc("Number of load instructions executed")
150 .flags(total);
151
152 iewExecSquashedInsts
153 .name(name() + ".iewExecSquashedInsts")
154 .desc("Number of squashed instructions skipped in execute");
155
156 memOrderViolationEvents
157 .name(name() + ".memOrderViolationEvents")
158 .desc("Number of memory order violations");
159
160 predictedTakenIncorrect
161 .name(name() + ".predictedTakenIncorrect")
162 .desc("Number of branches that were predicted taken incorrectly");
163
164 predictedNotTakenIncorrect
165 .name(name() + ".predictedNotTakenIncorrect")
166 .desc("Number of branches that were predicted not taken incorrectly");
167
168 branchMispredicts
169 .name(name() + ".branchMispredicts")
170 .desc("Number of branch mispredicts detected at execute");
171
172 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
173
174 exeSwp
175 .init(cpu->number_of_threads)
176 .name(name() + ".EXEC:swp")
177 .desc("number of swp insts executed")
178 .flags(total)
179 ;
180
181 exeNop
182 .init(cpu->number_of_threads)
183 .name(name() + ".EXEC:nop")
184 .desc("number of nop insts executed")
185 .flags(total)
186 ;
187
188 exeRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".EXEC:refs")
191 .desc("number of memory reference insts executed")
192 .flags(total)
193 ;
194
195 exeBranches
196 .init(cpu->number_of_threads)
197 .name(name() + ".EXEC:branches")
198 .desc("Number of branches executed")
199 .flags(total)
200 ;
201
202 issueRate
203 .name(name() + ".EXEC:rate")
204 .desc("Inst execution rate")
205 .flags(total)
206 ;
207 issueRate = iewExecutedInsts / cpu->numCycles;
208
209 iewExecStoreInsts
210 .name(name() + ".EXEC:stores")
211 .desc("Number of stores executed")
212 .flags(total)
213 ;
214 iewExecStoreInsts = exeRefs - iewExecLoadInsts;
215/*
216 for (int i=0; i<Num_OpClasses; ++i) {
217 stringstream subname;
218 subname << opClassStrings[i] << "_delay";
219 issue_delay_dist.subname(i, subname.str());
220 }
221*/
222 //
223 // Other stats
224 //
225
226 iewInstsToCommit
227 .init(cpu->number_of_threads)
228 .name(name() + ".WB:sent")
229 .desc("cumulative count of insts sent to commit")
230 .flags(total)
231 ;
232
233 writebackCount
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:count")
236 .desc("cumulative count of insts written-back")
237 .flags(total)
238 ;
239
240 producerInst
241 .init(cpu->number_of_threads)
242 .name(name() + ".WB:producers")
243 .desc("num instructions producing a value")
244 .flags(total)
245 ;
246
247 consumerInst
248 .init(cpu->number_of_threads)
249 .name(name() + ".WB:consumers")
250 .desc("num instructions consuming a value")
251 .flags(total)
252 ;
253
254 wbPenalized
255 .init(cpu->number_of_threads)
256 .name(name() + ".WB:penalized")
257 .desc("number of instrctions required to write to 'other' IQ")
258 .flags(total)
259 ;
260
261 wbPenalizedRate
262 .name(name() + ".WB:penalized_rate")
263 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
264 .flags(total)
265 ;
266
267 wbPenalizedRate = wbPenalized / writebackCount;
268
269 wbFanout
270 .name(name() + ".WB:fanout")
271 .desc("average fanout of values written-back")
272 .flags(total)
273 ;
274
275 wbFanout = producerInst / consumerInst;
276
277 wbRate
278 .name(name() + ".WB:rate")
279 .desc("insts written-back per cycle")
280 .flags(total)
281 ;
282 wbRate = writebackCount / cpu->numCycles;
283}
284
285template<class Impl>
286void
287DefaultIEW<Impl>::initStage()
288{
289 for (int tid=0; tid < numThreads; tid++) {
290 toRename->iewInfo[tid].usedIQ = true;
291 toRename->iewInfo[tid].freeIQEntries =
292 instQueue.numFreeEntries(tid);
293
294 toRename->iewInfo[tid].usedLSQ = true;
295 toRename->iewInfo[tid].freeLSQEntries =
296 ldstQueue.numFreeEntries(tid);
297 }
298}
299
300template<class Impl>
301void
302DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
303{
304 DPRINTF(IEW, "Setting CPU pointer.\n");
305 cpu = cpu_ptr;
306
307 instQueue.setCPU(cpu_ptr);
308 ldstQueue.setCPU(cpu_ptr);
309
310 cpu->activateStage(FullCPU::IEWIdx);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
316{
317 DPRINTF(IEW, "Setting time buffer pointer.\n");
318 timeBuffer = tb_ptr;
319
320 // Setup wire to read information from time buffer, from commit.
321 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
322
323 // Setup wire to write information back to previous stages.
324 toRename = timeBuffer->getWire(0);
325
326 toFetch = timeBuffer->getWire(0);
327
328 // Instruction queue also needs main time buffer.
329 instQueue.setTimeBuffer(tb_ptr);
330}
331
332template<class Impl>
333void
334DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
335{
336 DPRINTF(IEW, "Setting rename queue pointer.\n");
337 renameQueue = rq_ptr;
338
339 // Setup wire to read information from rename queue.
340 fromRename = renameQueue->getWire(-renameToIEWDelay);
341}
342
343template<class Impl>
344void
345DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
346{
347 DPRINTF(IEW, "Setting IEW queue pointer.\n");
348 iewQueue = iq_ptr;
349
350 // Setup wire to write instructions to commit.
351 toCommit = iewQueue->getWire(0);
352}
353
354template<class Impl>
355void
356DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
357{
358 DPRINTF(IEW, "Setting active threads list pointer.\n");
359 activeThreads = at_ptr;
360
361 ldstQueue.setActiveThreads(at_ptr);
362 instQueue.setActiveThreads(at_ptr);
363}
364
365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 DPRINTF(IEW, "Setting scoreboard pointer.\n");
370 scoreboard = sb_ptr;
371}
372
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew. There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
47 instQueue(params),
48 ldstQueue(params),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 issueReadWidth(params->issueWidth),
54 issueWidth(params->issueWidth),
55 executeWidth(params->executeWidth),
56 numThreads(params->numberOfThreads),
57 switchedOut(false)
58{
59 _status = Active;
60 exeStatus = Running;
61 wbStatus = Idle;
62
63 // Setup wire to read instructions coming from issue.
64 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66 // Instruction queue needs the queue between issue and execute.
67 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69 instQueue.setIEW(this);
70 ldstQueue.setIEW(this);
71
72 for (int i=0; i < numThreads; i++) {
73 dispatchStatus[i] = Running;
74 stalls[i].commit = false;
75 fetchRedirect[i] = false;
76 }
77
78 updateLSQNextCycle = false;
79
80 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
81}
82
83template <class Impl>
84std::string
85DefaultIEW<Impl>::name() const
86{
87 return cpu->name() + ".iew";
88}
89
90template <class Impl>
91void
92DefaultIEW<Impl>::regStats()
93{
94 using namespace Stats;
95
96 instQueue.regStats();
97
98 iewIdleCycles
99 .name(name() + ".iewIdleCycles")
100 .desc("Number of cycles IEW is idle");
101
102 iewSquashCycles
103 .name(name() + ".iewSquashCycles")
104 .desc("Number of cycles IEW is squashing");
105
106 iewBlockCycles
107 .name(name() + ".iewBlockCycles")
108 .desc("Number of cycles IEW is blocking");
109
110 iewUnblockCycles
111 .name(name() + ".iewUnblockCycles")
112 .desc("Number of cycles IEW is unblocking");
113
114 iewDispatchedInsts
115 .name(name() + ".iewDispatchedInsts")
116 .desc("Number of instructions dispatched to IQ");
117
118 iewDispSquashedInsts
119 .name(name() + ".iewDispSquashedInsts")
120 .desc("Number of squashed instructions skipped by dispatch");
121
122 iewDispLoadInsts
123 .name(name() + ".iewDispLoadInsts")
124 .desc("Number of dispatched load instructions");
125
126 iewDispStoreInsts
127 .name(name() + ".iewDispStoreInsts")
128 .desc("Number of dispatched store instructions");
129
130 iewDispNonSpecInsts
131 .name(name() + ".iewDispNonSpecInsts")
132 .desc("Number of dispatched non-speculative instructions");
133
134 iewIQFullEvents
135 .name(name() + ".iewIQFullEvents")
136 .desc("Number of times the IQ has become full, causing a stall");
137
138 iewLSQFullEvents
139 .name(name() + ".iewLSQFullEvents")
140 .desc("Number of times the LSQ has become full, causing a stall");
141
142 iewExecutedInsts
143 .name(name() + ".iewExecutedInsts")
144 .desc("Number of executed instructions");
145
146 iewExecLoadInsts
147 .init(cpu->number_of_threads)
148 .name(name() + ".iewExecLoadInsts")
149 .desc("Number of load instructions executed")
150 .flags(total);
151
152 iewExecSquashedInsts
153 .name(name() + ".iewExecSquashedInsts")
154 .desc("Number of squashed instructions skipped in execute");
155
156 memOrderViolationEvents
157 .name(name() + ".memOrderViolationEvents")
158 .desc("Number of memory order violations");
159
160 predictedTakenIncorrect
161 .name(name() + ".predictedTakenIncorrect")
162 .desc("Number of branches that were predicted taken incorrectly");
163
164 predictedNotTakenIncorrect
165 .name(name() + ".predictedNotTakenIncorrect")
166 .desc("Number of branches that were predicted not taken incorrectly");
167
168 branchMispredicts
169 .name(name() + ".branchMispredicts")
170 .desc("Number of branch mispredicts detected at execute");
171
172 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
173
174 exeSwp
175 .init(cpu->number_of_threads)
176 .name(name() + ".EXEC:swp")
177 .desc("number of swp insts executed")
178 .flags(total)
179 ;
180
181 exeNop
182 .init(cpu->number_of_threads)
183 .name(name() + ".EXEC:nop")
184 .desc("number of nop insts executed")
185 .flags(total)
186 ;
187
188 exeRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".EXEC:refs")
191 .desc("number of memory reference insts executed")
192 .flags(total)
193 ;
194
195 exeBranches
196 .init(cpu->number_of_threads)
197 .name(name() + ".EXEC:branches")
198 .desc("Number of branches executed")
199 .flags(total)
200 ;
201
202 issueRate
203 .name(name() + ".EXEC:rate")
204 .desc("Inst execution rate")
205 .flags(total)
206 ;
207 issueRate = iewExecutedInsts / cpu->numCycles;
208
209 iewExecStoreInsts
210 .name(name() + ".EXEC:stores")
211 .desc("Number of stores executed")
212 .flags(total)
213 ;
214 iewExecStoreInsts = exeRefs - iewExecLoadInsts;
215/*
216 for (int i=0; i<Num_OpClasses; ++i) {
217 stringstream subname;
218 subname << opClassStrings[i] << "_delay";
219 issue_delay_dist.subname(i, subname.str());
220 }
221*/
222 //
223 // Other stats
224 //
225
226 iewInstsToCommit
227 .init(cpu->number_of_threads)
228 .name(name() + ".WB:sent")
229 .desc("cumulative count of insts sent to commit")
230 .flags(total)
231 ;
232
233 writebackCount
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:count")
236 .desc("cumulative count of insts written-back")
237 .flags(total)
238 ;
239
240 producerInst
241 .init(cpu->number_of_threads)
242 .name(name() + ".WB:producers")
243 .desc("num instructions producing a value")
244 .flags(total)
245 ;
246
247 consumerInst
248 .init(cpu->number_of_threads)
249 .name(name() + ".WB:consumers")
250 .desc("num instructions consuming a value")
251 .flags(total)
252 ;
253
254 wbPenalized
255 .init(cpu->number_of_threads)
256 .name(name() + ".WB:penalized")
257 .desc("number of instrctions required to write to 'other' IQ")
258 .flags(total)
259 ;
260
261 wbPenalizedRate
262 .name(name() + ".WB:penalized_rate")
263 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
264 .flags(total)
265 ;
266
267 wbPenalizedRate = wbPenalized / writebackCount;
268
269 wbFanout
270 .name(name() + ".WB:fanout")
271 .desc("average fanout of values written-back")
272 .flags(total)
273 ;
274
275 wbFanout = producerInst / consumerInst;
276
277 wbRate
278 .name(name() + ".WB:rate")
279 .desc("insts written-back per cycle")
280 .flags(total)
281 ;
282 wbRate = writebackCount / cpu->numCycles;
283}
284
285template<class Impl>
286void
287DefaultIEW<Impl>::initStage()
288{
289 for (int tid=0; tid < numThreads; tid++) {
290 toRename->iewInfo[tid].usedIQ = true;
291 toRename->iewInfo[tid].freeIQEntries =
292 instQueue.numFreeEntries(tid);
293
294 toRename->iewInfo[tid].usedLSQ = true;
295 toRename->iewInfo[tid].freeLSQEntries =
296 ldstQueue.numFreeEntries(tid);
297 }
298}
299
300template<class Impl>
301void
302DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
303{
304 DPRINTF(IEW, "Setting CPU pointer.\n");
305 cpu = cpu_ptr;
306
307 instQueue.setCPU(cpu_ptr);
308 ldstQueue.setCPU(cpu_ptr);
309
310 cpu->activateStage(FullCPU::IEWIdx);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
316{
317 DPRINTF(IEW, "Setting time buffer pointer.\n");
318 timeBuffer = tb_ptr;
319
320 // Setup wire to read information from time buffer, from commit.
321 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
322
323 // Setup wire to write information back to previous stages.
324 toRename = timeBuffer->getWire(0);
325
326 toFetch = timeBuffer->getWire(0);
327
328 // Instruction queue also needs main time buffer.
329 instQueue.setTimeBuffer(tb_ptr);
330}
331
332template<class Impl>
333void
334DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
335{
336 DPRINTF(IEW, "Setting rename queue pointer.\n");
337 renameQueue = rq_ptr;
338
339 // Setup wire to read information from rename queue.
340 fromRename = renameQueue->getWire(-renameToIEWDelay);
341}
342
343template<class Impl>
344void
345DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
346{
347 DPRINTF(IEW, "Setting IEW queue pointer.\n");
348 iewQueue = iq_ptr;
349
350 // Setup wire to write instructions to commit.
351 toCommit = iewQueue->getWire(0);
352}
353
354template<class Impl>
355void
356DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
357{
358 DPRINTF(IEW, "Setting active threads list pointer.\n");
359 activeThreads = at_ptr;
360
361 ldstQueue.setActiveThreads(at_ptr);
362 instQueue.setActiveThreads(at_ptr);
363}
364
365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 DPRINTF(IEW, "Setting scoreboard pointer.\n");
370 scoreboard = sb_ptr;
371}
372
|
373#if 0
374template<class Impl>
375void
376DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
377{
378 ldstQueue.setPageTable(pt_ptr);
379}
380#endif
381
| |
382template <class Impl>
383void
384DefaultIEW<Impl>::switchOut()
385{
386 // IEW is ready to switch out at any time.
387 cpu->signalSwitched();
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::doSwitchOut()
393{
394 // Clear any state.
395 switchedOut = true;
396
397 instQueue.switchOut();
398 ldstQueue.switchOut();
399 fuPool->switchOut();
400
401 for (int i = 0; i < numThreads; i++) {
402 while (!insts[i].empty())
403 insts[i].pop();
404 while (!skidBuffer[i].empty())
405 skidBuffer[i].pop();
406 }
407}
408
409template <class Impl>
410void
411DefaultIEW<Impl>::takeOverFrom()
412{
413 // Reset all state.
414 _status = Active;
415 exeStatus = Running;
416 wbStatus = Idle;
417 switchedOut = false;
418
419 instQueue.takeOverFrom();
420 ldstQueue.takeOverFrom();
421 fuPool->takeOverFrom();
422
423 initStage();
424 cpu->activityThisCycle();
425
426 for (int i=0; i < numThreads; i++) {
427 dispatchStatus[i] = Running;
428 stalls[i].commit = false;
429 fetchRedirect[i] = false;
430 }
431
432 updateLSQNextCycle = false;
433
434 // @todo: Fix hardcoded number
435 for (int i = 0; i < 6; ++i) {
436 issueToExecQueue.advance();
437 }
438}
439
440template<class Impl>
441void
442DefaultIEW<Impl>::squash(unsigned tid)
443{
444 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
445 tid);
446
447 // Tell the IQ to start squashing.
448 instQueue.squash(tid);
449
450 // Tell the LDSTQ to start squashing.
451 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
452
453 updatedQueues = true;
454
455 // Clear the skid buffer in case it has any data in it.
456 while (!skidBuffer[tid].empty()) {
457
458 if (skidBuffer[tid].front()->isLoad() ||
459 skidBuffer[tid].front()->isStore() ) {
460 toRename->iewInfo[tid].dispatchedToLSQ++;
461 }
462
463 toRename->iewInfo[tid].dispatched++;
464
465 skidBuffer[tid].pop();
466 }
467
468 while (!insts[tid].empty()) {
469 if (insts[tid].front()->isLoad() ||
470 insts[tid].front()->isStore() ) {
471 toRename->iewInfo[tid].dispatchedToLSQ++;
472 }
473
474 toRename->iewInfo[tid].dispatched++;
475
476 insts[tid].pop();
477 }
478}
479
480template<class Impl>
481void
482DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
483{
484 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
485 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
486
487 toCommit->squash[tid] = true;
488 toCommit->squashedSeqNum[tid] = inst->seqNum;
489 toCommit->mispredPC[tid] = inst->readPC();
490 toCommit->nextPC[tid] = inst->readNextPC();
491 toCommit->branchMispredict[tid] = true;
492 toCommit->branchTaken[tid] = inst->readNextPC() !=
493 (inst->readPC() + sizeof(TheISA::MachInst));
494
495 toCommit->includeSquashInst[tid] = false;
496
497 wroteToTimeBuffer = true;
498}
499
500template<class Impl>
501void
502DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
503{
504 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
505 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
506
507 toCommit->squash[tid] = true;
508 toCommit->squashedSeqNum[tid] = inst->seqNum;
509 toCommit->nextPC[tid] = inst->readNextPC();
510
511 toCommit->includeSquashInst[tid] = false;
512
513 wroteToTimeBuffer = true;
514}
515
516template<class Impl>
517void
518DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
519{
520 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
521 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
522
523 toCommit->squash[tid] = true;
524 toCommit->squashedSeqNum[tid] = inst->seqNum;
525 toCommit->nextPC[tid] = inst->readPC();
526
527 // Must include the broadcasted SN in the squash.
528 toCommit->includeSquashInst[tid] = true;
529
530 ldstQueue.setLoadBlockedHandled(tid);
531
532 wroteToTimeBuffer = true;
533}
534
535template<class Impl>
536void
537DefaultIEW<Impl>::block(unsigned tid)
538{
539 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
540
541 if (dispatchStatus[tid] != Blocked &&
542 dispatchStatus[tid] != Unblocking) {
543 toRename->iewBlock[tid] = true;
544 wroteToTimeBuffer = true;
545 }
546
547 // Add the current inputs to the skid buffer so they can be
548 // reprocessed when this stage unblocks.
549 skidInsert(tid);
550
551 dispatchStatus[tid] = Blocked;
552}
553
554template<class Impl>
555void
556DefaultIEW<Impl>::unblock(unsigned tid)
557{
558 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
559 "buffer %u.\n",tid, tid);
560
561 // If the skid bufffer is empty, signal back to previous stages to unblock.
562 // Also switch status to running.
563 if (skidBuffer[tid].empty()) {
564 toRename->iewUnblock[tid] = true;
565 wroteToTimeBuffer = true;
566 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
567 dispatchStatus[tid] = Running;
568 }
569}
570
571template<class Impl>
572void
573DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
574{
575 instQueue.wakeDependents(inst);
576}
577
578template<class Impl>
579void
580DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
581{
582 instQueue.rescheduleMemInst(inst);
583}
584
585template<class Impl>
586void
587DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
588{
589 instQueue.replayMemInst(inst);
590}
591
592template<class Impl>
593void
594DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
595{
596 // First check the time slot that this instruction will write
597 // to. If there are free write ports at the time, then go ahead
598 // and write the instruction to that time. If there are not,
599 // keep looking back to see where's the first time there's a
600 // free slot.
601 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
602 ++wbNumInst;
603 if (wbNumInst == issueWidth) {
604 ++wbCycle;
605 wbNumInst = 0;
606 }
607
608 assert(wbCycle < 5);
609 }
610
611 // Add finished instruction to queue to commit.
612 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
613 (*iewQueue)[wbCycle].size++;
614}
615
616template <class Impl>
617unsigned
618DefaultIEW<Impl>::validInstsFromRename()
619{
620 unsigned inst_count = 0;
621
622 for (int i=0; i<fromRename->size; i++) {
623 if (!fromRename->insts[i]->squashed)
624 inst_count++;
625 }
626
627 return inst_count;
628}
629
630template<class Impl>
631void
632DefaultIEW<Impl>::skidInsert(unsigned tid)
633{
634 DynInstPtr inst = NULL;
635
636 while (!insts[tid].empty()) {
637 inst = insts[tid].front();
638
639 insts[tid].pop();
640
641 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
642 "dispatch skidBuffer %i\n",tid, inst->seqNum,
643 inst->readPC(),tid);
644
645 skidBuffer[tid].push(inst);
646 }
647
648 assert(skidBuffer[tid].size() <= skidBufferMax &&
649 "Skidbuffer Exceeded Max Size");
650}
651
652template<class Impl>
653int
654DefaultIEW<Impl>::skidCount()
655{
656 int max=0;
657
658 list<unsigned>::iterator threads = (*activeThreads).begin();
659
660 while (threads != (*activeThreads).end()) {
661 unsigned thread_count = skidBuffer[*threads++].size();
662 if (max < thread_count)
663 max = thread_count;
664 }
665
666 return max;
667}
668
669template<class Impl>
670bool
671DefaultIEW<Impl>::skidsEmpty()
672{
673 list<unsigned>::iterator threads = (*activeThreads).begin();
674
675 while (threads != (*activeThreads).end()) {
676 if (!skidBuffer[*threads++].empty())
677 return false;
678 }
679
680 return true;
681}
682
683template <class Impl>
684void
685DefaultIEW<Impl>::updateStatus()
686{
687 bool any_unblocking = false;
688
689 list<unsigned>::iterator threads = (*activeThreads).begin();
690
691 threads = (*activeThreads).begin();
692
693 while (threads != (*activeThreads).end()) {
694 unsigned tid = *threads++;
695
696 if (dispatchStatus[tid] == Unblocking) {
697 any_unblocking = true;
698 break;
699 }
700 }
701
702 // If there are no ready instructions waiting to be scheduled by the IQ,
703 // and there's no stores waiting to write back, and dispatch is not
704 // unblocking, then there is no internal activity for the IEW stage.
705 if (_status == Active && !instQueue.hasReadyInsts() &&
706 !ldstQueue.willWB() && !any_unblocking) {
707 DPRINTF(IEW, "IEW switching to idle\n");
708
709 deactivateStage();
710
711 _status = Inactive;
712 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
713 ldstQueue.willWB() ||
714 any_unblocking)) {
715 // Otherwise there is internal activity. Set to active.
716 DPRINTF(IEW, "IEW switching to active\n");
717
718 activateStage();
719
720 _status = Active;
721 }
722}
723
724template <class Impl>
725void
726DefaultIEW<Impl>::resetEntries()
727{
728 instQueue.resetEntries();
729 ldstQueue.resetEntries();
730}
731
732template <class Impl>
733void
734DefaultIEW<Impl>::readStallSignals(unsigned tid)
735{
736 if (fromCommit->commitBlock[tid]) {
737 stalls[tid].commit = true;
738 }
739
740 if (fromCommit->commitUnblock[tid]) {
741 assert(stalls[tid].commit);
742 stalls[tid].commit = false;
743 }
744}
745
746template <class Impl>
747bool
748DefaultIEW<Impl>::checkStall(unsigned tid)
749{
750 bool ret_val(false);
751
752 if (stalls[tid].commit) {
753 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
754 ret_val = true;
755 } else if (instQueue.isFull(tid)) {
756 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
757 ret_val = true;
758 } else if (ldstQueue.isFull(tid)) {
759 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
760
761 if (ldstQueue.numLoads(tid) > 0 ) {
762
763 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
764 tid,ldstQueue.getLoadHeadSeqNum(tid));
765 }
766
767 if (ldstQueue.numStores(tid) > 0) {
768
769 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
770 tid,ldstQueue.getStoreHeadSeqNum(tid));
771 }
772
773 ret_val = true;
774 } else if (ldstQueue.isStalled(tid)) {
775 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
776 ret_val = true;
777 }
778
779 return ret_val;
780}
781
782template <class Impl>
783void
784DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
785{
786 // Check if there's a squash signal, squash if there is
787 // Check stall signals, block if there is.
788 // If status was Blocked
789 // if so then go to unblocking
790 // If status was Squashing
791 // check if squashing is not high. Switch to running this cycle.
792
793 readStallSignals(tid);
794
795 if (fromCommit->commitInfo[tid].squash) {
796 squash(tid);
797
798 if (dispatchStatus[tid] == Blocked ||
799 dispatchStatus[tid] == Unblocking) {
800 toRename->iewUnblock[tid] = true;
801 wroteToTimeBuffer = true;
802 }
803
804 dispatchStatus[tid] = Squashing;
805
806 fetchRedirect[tid] = false;
807 return;
808 }
809
810 if (fromCommit->commitInfo[tid].robSquashing) {
811 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
812
813 dispatchStatus[tid] = Squashing;
814
815 return;
816 }
817
818 if (checkStall(tid)) {
819 block(tid);
820 dispatchStatus[tid] = Blocked;
821 return;
822 }
823
824 if (dispatchStatus[tid] == Blocked) {
825 // Status from previous cycle was blocked, but there are no more stall
826 // conditions. Switch over to unblocking.
827 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
828 tid);
829
830 dispatchStatus[tid] = Unblocking;
831
832 unblock(tid);
833
834 return;
835 }
836
837 if (dispatchStatus[tid] == Squashing) {
838 // Switch status to running if rename isn't being told to block or
839 // squash this cycle.
840 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
841 tid);
842
843 dispatchStatus[tid] = Running;
844
845 return;
846 }
847}
848
849template <class Impl>
850void
851DefaultIEW<Impl>::sortInsts()
852{
853 int insts_from_rename = fromRename->size;
854#ifdef DEBUG
855 for (int i = 0; i < numThreads; i++)
856 assert(insts[i].empty());
857#endif
858 for (int i = 0; i < insts_from_rename; ++i) {
859 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
860 }
861}
862
863template <class Impl>
864void
865DefaultIEW<Impl>::wakeCPU()
866{
867 cpu->wakeCPU();
868}
869
870template <class Impl>
871void
872DefaultIEW<Impl>::activityThisCycle()
873{
874 DPRINTF(Activity, "Activity this cycle.\n");
875 cpu->activityThisCycle();
876}
877
878template <class Impl>
879inline void
880DefaultIEW<Impl>::activateStage()
881{
882 DPRINTF(Activity, "Activating stage.\n");
883 cpu->activateStage(FullCPU::IEWIdx);
884}
885
886template <class Impl>
887inline void
888DefaultIEW<Impl>::deactivateStage()
889{
890 DPRINTF(Activity, "Deactivating stage.\n");
891 cpu->deactivateStage(FullCPU::IEWIdx);
892}
893
894template<class Impl>
895void
896DefaultIEW<Impl>::dispatch(unsigned tid)
897{
898 // If status is Running or idle,
899 // call dispatchInsts()
900 // If status is Unblocking,
901 // buffer any instructions coming from rename
902 // continue trying to empty skid buffer
903 // check if stall conditions have passed
904
905 if (dispatchStatus[tid] == Blocked) {
906 ++iewBlockCycles;
907
908 } else if (dispatchStatus[tid] == Squashing) {
909 ++iewSquashCycles;
910 }
911
912 // Dispatch should try to dispatch as many instructions as its bandwidth
913 // will allow, as long as it is not currently blocked.
914 if (dispatchStatus[tid] == Running ||
915 dispatchStatus[tid] == Idle) {
916 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
917 "dispatch.\n", tid);
918
919 dispatchInsts(tid);
920 } else if (dispatchStatus[tid] == Unblocking) {
921 // Make sure that the skid buffer has something in it if the
922 // status is unblocking.
923 assert(!skidsEmpty());
924
925 // If the status was unblocking, then instructions from the skid
926 // buffer were used. Remove those instructions and handle
927 // the rest of unblocking.
928 dispatchInsts(tid);
929
930 ++iewUnblockCycles;
931
932 if (validInstsFromRename() && dispatchedAllInsts) {
933 // Add the current inputs to the skid buffer so they can be
934 // reprocessed when this stage unblocks.
935 skidInsert(tid);
936 }
937
938 unblock(tid);
939 }
940}
941
942template <class Impl>
943void
944DefaultIEW<Impl>::dispatchInsts(unsigned tid)
945{
946 dispatchedAllInsts = true;
947
948 // Obtain instructions from skid buffer if unblocking, or queue from rename
949 // otherwise.
950 std::queue<DynInstPtr> &insts_to_dispatch =
951 dispatchStatus[tid] == Unblocking ?
952 skidBuffer[tid] : insts[tid];
953
954 int insts_to_add = insts_to_dispatch.size();
955
956 DynInstPtr inst;
957 bool add_to_iq = false;
958 int dis_num_inst = 0;
959
960 // Loop through the instructions, putting them in the instruction
961 // queue.
962 for ( ; dis_num_inst < insts_to_add &&
963 dis_num_inst < issueReadWidth;
964 ++dis_num_inst)
965 {
966 inst = insts_to_dispatch.front();
967
968 if (dispatchStatus[tid] == Unblocking) {
969 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
970 "buffer\n", tid);
971 }
972
973 // Make sure there's a valid instruction there.
974 assert(inst);
975
976 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
977 "IQ.\n",
978 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
979
980 // Be sure to mark these instructions as ready so that the
981 // commit stage can go ahead and execute them, and mark
982 // them as issued so the IQ doesn't reprocess them.
983
984 // Check for squashed instructions.
985 if (inst->isSquashed()) {
986 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
987 "not adding to IQ.\n", tid);
988
989 ++iewDispSquashedInsts;
990
991 insts_to_dispatch.pop();
992
993 //Tell Rename That An Instruction has been processed
994 if (inst->isLoad() || inst->isStore()) {
995 toRename->iewInfo[tid].dispatchedToLSQ++;
996 }
997 toRename->iewInfo[tid].dispatched++;
998
999 continue;
1000 }
1001
1002 // Check for full conditions.
1003 if (instQueue.isFull(tid)) {
1004 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1005
1006 // Call function to start blocking.
1007 block(tid);
1008
1009 // Set unblock to false. Special case where we are using
1010 // skidbuffer (unblocking) instructions but then we still
1011 // get full in the IQ.
1012 toRename->iewUnblock[tid] = false;
1013
1014 dispatchedAllInsts = false;
1015
1016 ++iewIQFullEvents;
1017 break;
1018 } else if (ldstQueue.isFull(tid)) {
1019 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1020
1021 // Call function to start blocking.
1022 block(tid);
1023
1024 // Set unblock to false. Special case where we are using
1025 // skidbuffer (unblocking) instructions but then we still
1026 // get full in the IQ.
1027 toRename->iewUnblock[tid] = false;
1028
1029 dispatchedAllInsts = false;
1030
1031 ++iewLSQFullEvents;
1032 break;
1033 }
1034
1035 // Otherwise issue the instruction just fine.
1036 if (inst->isLoad()) {
1037 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1038 "encountered, adding to LSQ.\n", tid);
1039
1040 // Reserve a spot in the load store queue for this
1041 // memory access.
1042 ldstQueue.insertLoad(inst);
1043
1044 ++iewDispLoadInsts;
1045
1046 add_to_iq = true;
1047
1048 toRename->iewInfo[tid].dispatchedToLSQ++;
1049 } else if (inst->isStore()) {
1050 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1051 "encountered, adding to LSQ.\n", tid);
1052
1053 ldstQueue.insertStore(inst);
1054
1055 ++iewDispStoreInsts;
1056
1057 if (inst->isStoreConditional()) {
1058 // Store conditionals need to be set as "canCommit()"
1059 // so that commit can process them when they reach the
1060 // head of commit.
1061 // @todo: This is somewhat specific to Alpha.
1062 inst->setCanCommit();
1063 instQueue.insertNonSpec(inst);
1064 add_to_iq = false;
1065
1066 ++iewDispNonSpecInsts;
1067 } else {
1068 add_to_iq = true;
1069 }
1070
1071 toRename->iewInfo[tid].dispatchedToLSQ++;
1072#if FULL_SYSTEM
1073 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1074 // Same as non-speculative stores.
1075 inst->setCanCommit();
1076 instQueue.insertBarrier(inst);
1077 add_to_iq = false;
1078#endif
1079 } else if (inst->isNonSpeculative()) {
1080 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1081 "encountered, skipping.\n", tid);
1082
1083 // Same as non-speculative stores.
1084 inst->setCanCommit();
1085
1086 // Specifically insert it as nonspeculative.
1087 instQueue.insertNonSpec(inst);
1088
1089 ++iewDispNonSpecInsts;
1090
1091 add_to_iq = false;
1092 } else if (inst->isNop()) {
1093 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1094 "skipping.\n", tid);
1095
1096 inst->setIssued();
1097 inst->setExecuted();
1098 inst->setCanCommit();
1099
1100 instQueue.recordProducer(inst);
1101
1102 exeNop[tid]++;
1103
1104 add_to_iq = false;
1105 } else if (inst->isExecuted()) {
1106 assert(0 && "Instruction shouldn't be executed.\n");
1107 DPRINTF(IEW, "Issue: Executed branch encountered, "
1108 "skipping.\n");
1109
1110 inst->setIssued();
1111 inst->setCanCommit();
1112
1113 instQueue.recordProducer(inst);
1114
1115 add_to_iq = false;
1116 } else {
1117 add_to_iq = true;
1118 }
1119
1120 // If the instruction queue is not full, then add the
1121 // instruction.
1122 if (add_to_iq) {
1123 instQueue.insert(inst);
1124 }
1125
1126 insts_to_dispatch.pop();
1127
1128 toRename->iewInfo[tid].dispatched++;
1129
1130 ++iewDispatchedInsts;
1131 }
1132
1133 if (!insts_to_dispatch.empty()) {
1134 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1135 block(tid);
1136 toRename->iewUnblock[tid] = false;
1137 }
1138
1139 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1140 dispatchStatus[tid] = Running;
1141
1142 updatedQueues = true;
1143 }
1144
1145 dis_num_inst = 0;
1146}
1147
1148template <class Impl>
1149void
1150DefaultIEW<Impl>::printAvailableInsts()
1151{
1152 int inst = 0;
1153
1154 cout << "Available Instructions: ";
1155
1156 while (fromIssue->insts[inst]) {
1157
1158 if (inst%3==0) cout << "\n\t";
1159
1160 cout << "PC: " << fromIssue->insts[inst]->readPC()
1161 << " TN: " << fromIssue->insts[inst]->threadNumber
1162 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1163
1164 inst++;
1165
1166 }
1167
1168 cout << "\n";
1169}
1170
1171template <class Impl>
1172void
1173DefaultIEW<Impl>::executeInsts()
1174{
1175 wbNumInst = 0;
1176 wbCycle = 0;
1177
1178 list<unsigned>::iterator threads = (*activeThreads).begin();
1179
1180 while (threads != (*activeThreads).end()) {
1181 unsigned tid = *threads++;
1182 fetchRedirect[tid] = false;
1183 }
1184
| 373template <class Impl>
374void
375DefaultIEW<Impl>::switchOut()
376{
377 // IEW is ready to switch out at any time.
378 cpu->signalSwitched();
379}
380
381template <class Impl>
382void
383DefaultIEW<Impl>::doSwitchOut()
384{
385 // Clear any state.
386 switchedOut = true;
387
388 instQueue.switchOut();
389 ldstQueue.switchOut();
390 fuPool->switchOut();
391
392 for (int i = 0; i < numThreads; i++) {
393 while (!insts[i].empty())
394 insts[i].pop();
395 while (!skidBuffer[i].empty())
396 skidBuffer[i].pop();
397 }
398}
399
400template <class Impl>
401void
402DefaultIEW<Impl>::takeOverFrom()
403{
404 // Reset all state.
405 _status = Active;
406 exeStatus = Running;
407 wbStatus = Idle;
408 switchedOut = false;
409
410 instQueue.takeOverFrom();
411 ldstQueue.takeOverFrom();
412 fuPool->takeOverFrom();
413
414 initStage();
415 cpu->activityThisCycle();
416
417 for (int i=0; i < numThreads; i++) {
418 dispatchStatus[i] = Running;
419 stalls[i].commit = false;
420 fetchRedirect[i] = false;
421 }
422
423 updateLSQNextCycle = false;
424
425 // @todo: Fix hardcoded number
426 for (int i = 0; i < 6; ++i) {
427 issueToExecQueue.advance();
428 }
429}
430
431template<class Impl>
432void
433DefaultIEW<Impl>::squash(unsigned tid)
434{
435 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
436 tid);
437
438 // Tell the IQ to start squashing.
439 instQueue.squash(tid);
440
441 // Tell the LDSTQ to start squashing.
442 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
443
444 updatedQueues = true;
445
446 // Clear the skid buffer in case it has any data in it.
447 while (!skidBuffer[tid].empty()) {
448
449 if (skidBuffer[tid].front()->isLoad() ||
450 skidBuffer[tid].front()->isStore() ) {
451 toRename->iewInfo[tid].dispatchedToLSQ++;
452 }
453
454 toRename->iewInfo[tid].dispatched++;
455
456 skidBuffer[tid].pop();
457 }
458
459 while (!insts[tid].empty()) {
460 if (insts[tid].front()->isLoad() ||
461 insts[tid].front()->isStore() ) {
462 toRename->iewInfo[tid].dispatchedToLSQ++;
463 }
464
465 toRename->iewInfo[tid].dispatched++;
466
467 insts[tid].pop();
468 }
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->nextPC[tid] = inst->readNextPC();
482 toCommit->branchMispredict[tid] = true;
483 toCommit->branchTaken[tid] = inst->readNextPC() !=
484 (inst->readPC() + sizeof(TheISA::MachInst));
485
486 toCommit->includeSquashInst[tid] = false;
487
488 wroteToTimeBuffer = true;
489}
490
491template<class Impl>
492void
493DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
494{
495 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
496 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
497
498 toCommit->squash[tid] = true;
499 toCommit->squashedSeqNum[tid] = inst->seqNum;
500 toCommit->nextPC[tid] = inst->readNextPC();
501
502 toCommit->includeSquashInst[tid] = false;
503
504 wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readPC();
517
518 // Must include the broadcasted SN in the squash.
519 toCommit->includeSquashInst[tid] = true;
520
521 ldstQueue.setLoadBlockedHandled(tid);
522
523 wroteToTimeBuffer = true;
524}
525
526template<class Impl>
527void
528DefaultIEW<Impl>::block(unsigned tid)
529{
530 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
531
532 if (dispatchStatus[tid] != Blocked &&
533 dispatchStatus[tid] != Unblocking) {
534 toRename->iewBlock[tid] = true;
535 wroteToTimeBuffer = true;
536 }
537
538 // Add the current inputs to the skid buffer so they can be
539 // reprocessed when this stage unblocks.
540 skidInsert(tid);
541
542 dispatchStatus[tid] = Blocked;
543}
544
545template<class Impl>
546void
547DefaultIEW<Impl>::unblock(unsigned tid)
548{
549 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
550 "buffer %u.\n",tid, tid);
551
552 // If the skid bufffer is empty, signal back to previous stages to unblock.
553 // Also switch status to running.
554 if (skidBuffer[tid].empty()) {
555 toRename->iewUnblock[tid] = true;
556 wroteToTimeBuffer = true;
557 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
558 dispatchStatus[tid] = Running;
559 }
560}
561
562template<class Impl>
563void
564DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
565{
566 instQueue.wakeDependents(inst);
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
572{
573 instQueue.rescheduleMemInst(inst);
574}
575
576template<class Impl>
577void
578DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
579{
580 instQueue.replayMemInst(inst);
581}
582
583template<class Impl>
584void
585DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
586{
587 // First check the time slot that this instruction will write
588 // to. If there are free write ports at the time, then go ahead
589 // and write the instruction to that time. If there are not,
590 // keep looking back to see where's the first time there's a
591 // free slot.
592 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
593 ++wbNumInst;
594 if (wbNumInst == issueWidth) {
595 ++wbCycle;
596 wbNumInst = 0;
597 }
598
599 assert(wbCycle < 5);
600 }
601
602 // Add finished instruction to queue to commit.
603 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
604 (*iewQueue)[wbCycle].size++;
605}
606
607template <class Impl>
608unsigned
609DefaultIEW<Impl>::validInstsFromRename()
610{
611 unsigned inst_count = 0;
612
613 for (int i=0; i<fromRename->size; i++) {
614 if (!fromRename->insts[i]->squashed)
615 inst_count++;
616 }
617
618 return inst_count;
619}
620
621template<class Impl>
622void
623DefaultIEW<Impl>::skidInsert(unsigned tid)
624{
625 DynInstPtr inst = NULL;
626
627 while (!insts[tid].empty()) {
628 inst = insts[tid].front();
629
630 insts[tid].pop();
631
632 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
633 "dispatch skidBuffer %i\n",tid, inst->seqNum,
634 inst->readPC(),tid);
635
636 skidBuffer[tid].push(inst);
637 }
638
639 assert(skidBuffer[tid].size() <= skidBufferMax &&
640 "Skidbuffer Exceeded Max Size");
641}
642
643template<class Impl>
644int
645DefaultIEW<Impl>::skidCount()
646{
647 int max=0;
648
649 list<unsigned>::iterator threads = (*activeThreads).begin();
650
651 while (threads != (*activeThreads).end()) {
652 unsigned thread_count = skidBuffer[*threads++].size();
653 if (max < thread_count)
654 max = thread_count;
655 }
656
657 return max;
658}
659
660template<class Impl>
661bool
662DefaultIEW<Impl>::skidsEmpty()
663{
664 list<unsigned>::iterator threads = (*activeThreads).begin();
665
666 while (threads != (*activeThreads).end()) {
667 if (!skidBuffer[*threads++].empty())
668 return false;
669 }
670
671 return true;
672}
673
674template <class Impl>
675void
676DefaultIEW<Impl>::updateStatus()
677{
678 bool any_unblocking = false;
679
680 list<unsigned>::iterator threads = (*activeThreads).begin();
681
682 threads = (*activeThreads).begin();
683
684 while (threads != (*activeThreads).end()) {
685 unsigned tid = *threads++;
686
687 if (dispatchStatus[tid] == Unblocking) {
688 any_unblocking = true;
689 break;
690 }
691 }
692
693 // If there are no ready instructions waiting to be scheduled by the IQ,
694 // and there's no stores waiting to write back, and dispatch is not
695 // unblocking, then there is no internal activity for the IEW stage.
696 if (_status == Active && !instQueue.hasReadyInsts() &&
697 !ldstQueue.willWB() && !any_unblocking) {
698 DPRINTF(IEW, "IEW switching to idle\n");
699
700 deactivateStage();
701
702 _status = Inactive;
703 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
704 ldstQueue.willWB() ||
705 any_unblocking)) {
706 // Otherwise there is internal activity. Set to active.
707 DPRINTF(IEW, "IEW switching to active\n");
708
709 activateStage();
710
711 _status = Active;
712 }
713}
714
715template <class Impl>
716void
717DefaultIEW<Impl>::resetEntries()
718{
719 instQueue.resetEntries();
720 ldstQueue.resetEntries();
721}
722
723template <class Impl>
724void
725DefaultIEW<Impl>::readStallSignals(unsigned tid)
726{
727 if (fromCommit->commitBlock[tid]) {
728 stalls[tid].commit = true;
729 }
730
731 if (fromCommit->commitUnblock[tid]) {
732 assert(stalls[tid].commit);
733 stalls[tid].commit = false;
734 }
735}
736
737template <class Impl>
738bool
739DefaultIEW<Impl>::checkStall(unsigned tid)
740{
741 bool ret_val(false);
742
743 if (stalls[tid].commit) {
744 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
745 ret_val = true;
746 } else if (instQueue.isFull(tid)) {
747 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
748 ret_val = true;
749 } else if (ldstQueue.isFull(tid)) {
750 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
751
752 if (ldstQueue.numLoads(tid) > 0 ) {
753
754 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
755 tid,ldstQueue.getLoadHeadSeqNum(tid));
756 }
757
758 if (ldstQueue.numStores(tid) > 0) {
759
760 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
761 tid,ldstQueue.getStoreHeadSeqNum(tid));
762 }
763
764 ret_val = true;
765 } else if (ldstQueue.isStalled(tid)) {
766 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
767 ret_val = true;
768 }
769
770 return ret_val;
771}
772
773template <class Impl>
774void
775DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
776{
777 // Check if there's a squash signal, squash if there is
778 // Check stall signals, block if there is.
779 // If status was Blocked
780 // if so then go to unblocking
781 // If status was Squashing
782 // check if squashing is not high. Switch to running this cycle.
783
784 readStallSignals(tid);
785
786 if (fromCommit->commitInfo[tid].squash) {
787 squash(tid);
788
789 if (dispatchStatus[tid] == Blocked ||
790 dispatchStatus[tid] == Unblocking) {
791 toRename->iewUnblock[tid] = true;
792 wroteToTimeBuffer = true;
793 }
794
795 dispatchStatus[tid] = Squashing;
796
797 fetchRedirect[tid] = false;
798 return;
799 }
800
801 if (fromCommit->commitInfo[tid].robSquashing) {
802 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
803
804 dispatchStatus[tid] = Squashing;
805
806 return;
807 }
808
809 if (checkStall(tid)) {
810 block(tid);
811 dispatchStatus[tid] = Blocked;
812 return;
813 }
814
815 if (dispatchStatus[tid] == Blocked) {
816 // Status from previous cycle was blocked, but there are no more stall
817 // conditions. Switch over to unblocking.
818 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
819 tid);
820
821 dispatchStatus[tid] = Unblocking;
822
823 unblock(tid);
824
825 return;
826 }
827
828 if (dispatchStatus[tid] == Squashing) {
829 // Switch status to running if rename isn't being told to block or
830 // squash this cycle.
831 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
832 tid);
833
834 dispatchStatus[tid] = Running;
835
836 return;
837 }
838}
839
840template <class Impl>
841void
842DefaultIEW<Impl>::sortInsts()
843{
844 int insts_from_rename = fromRename->size;
845#ifdef DEBUG
846 for (int i = 0; i < numThreads; i++)
847 assert(insts[i].empty());
848#endif
849 for (int i = 0; i < insts_from_rename; ++i) {
850 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
851 }
852}
853
854template <class Impl>
855void
856DefaultIEW<Impl>::wakeCPU()
857{
858 cpu->wakeCPU();
859}
860
861template <class Impl>
862void
863DefaultIEW<Impl>::activityThisCycle()
864{
865 DPRINTF(Activity, "Activity this cycle.\n");
866 cpu->activityThisCycle();
867}
868
869template <class Impl>
870inline void
871DefaultIEW<Impl>::activateStage()
872{
873 DPRINTF(Activity, "Activating stage.\n");
874 cpu->activateStage(FullCPU::IEWIdx);
875}
876
877template <class Impl>
878inline void
879DefaultIEW<Impl>::deactivateStage()
880{
881 DPRINTF(Activity, "Deactivating stage.\n");
882 cpu->deactivateStage(FullCPU::IEWIdx);
883}
884
885template<class Impl>
886void
887DefaultIEW<Impl>::dispatch(unsigned tid)
888{
889 // If status is Running or idle,
890 // call dispatchInsts()
891 // If status is Unblocking,
892 // buffer any instructions coming from rename
893 // continue trying to empty skid buffer
894 // check if stall conditions have passed
895
896 if (dispatchStatus[tid] == Blocked) {
897 ++iewBlockCycles;
898
899 } else if (dispatchStatus[tid] == Squashing) {
900 ++iewSquashCycles;
901 }
902
903 // Dispatch should try to dispatch as many instructions as its bandwidth
904 // will allow, as long as it is not currently blocked.
905 if (dispatchStatus[tid] == Running ||
906 dispatchStatus[tid] == Idle) {
907 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
908 "dispatch.\n", tid);
909
910 dispatchInsts(tid);
911 } else if (dispatchStatus[tid] == Unblocking) {
912 // Make sure that the skid buffer has something in it if the
913 // status is unblocking.
914 assert(!skidsEmpty());
915
916 // If the status was unblocking, then instructions from the skid
917 // buffer were used. Remove those instructions and handle
918 // the rest of unblocking.
919 dispatchInsts(tid);
920
921 ++iewUnblockCycles;
922
923 if (validInstsFromRename() && dispatchedAllInsts) {
924 // Add the current inputs to the skid buffer so they can be
925 // reprocessed when this stage unblocks.
926 skidInsert(tid);
927 }
928
929 unblock(tid);
930 }
931}
932
933template <class Impl>
934void
935DefaultIEW<Impl>::dispatchInsts(unsigned tid)
936{
937 dispatchedAllInsts = true;
938
939 // Obtain instructions from skid buffer if unblocking, or queue from rename
940 // otherwise.
941 std::queue<DynInstPtr> &insts_to_dispatch =
942 dispatchStatus[tid] == Unblocking ?
943 skidBuffer[tid] : insts[tid];
944
945 int insts_to_add = insts_to_dispatch.size();
946
947 DynInstPtr inst;
948 bool add_to_iq = false;
949 int dis_num_inst = 0;
950
951 // Loop through the instructions, putting them in the instruction
952 // queue.
953 for ( ; dis_num_inst < insts_to_add &&
954 dis_num_inst < issueReadWidth;
955 ++dis_num_inst)
956 {
957 inst = insts_to_dispatch.front();
958
959 if (dispatchStatus[tid] == Unblocking) {
960 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
961 "buffer\n", tid);
962 }
963
964 // Make sure there's a valid instruction there.
965 assert(inst);
966
967 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
968 "IQ.\n",
969 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
970
971 // Be sure to mark these instructions as ready so that the
972 // commit stage can go ahead and execute them, and mark
973 // them as issued so the IQ doesn't reprocess them.
974
975 // Check for squashed instructions.
976 if (inst->isSquashed()) {
977 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
978 "not adding to IQ.\n", tid);
979
980 ++iewDispSquashedInsts;
981
982 insts_to_dispatch.pop();
983
984 //Tell Rename That An Instruction has been processed
985 if (inst->isLoad() || inst->isStore()) {
986 toRename->iewInfo[tid].dispatchedToLSQ++;
987 }
988 toRename->iewInfo[tid].dispatched++;
989
990 continue;
991 }
992
993 // Check for full conditions.
994 if (instQueue.isFull(tid)) {
995 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
996
997 // Call function to start blocking.
998 block(tid);
999
1000 // Set unblock to false. Special case where we are using
1001 // skidbuffer (unblocking) instructions but then we still
1002 // get full in the IQ.
1003 toRename->iewUnblock[tid] = false;
1004
1005 dispatchedAllInsts = false;
1006
1007 ++iewIQFullEvents;
1008 break;
1009 } else if (ldstQueue.isFull(tid)) {
1010 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1011
1012 // Call function to start blocking.
1013 block(tid);
1014
1015 // Set unblock to false. Special case where we are using
1016 // skidbuffer (unblocking) instructions but then we still
1017 // get full in the IQ.
1018 toRename->iewUnblock[tid] = false;
1019
1020 dispatchedAllInsts = false;
1021
1022 ++iewLSQFullEvents;
1023 break;
1024 }
1025
1026 // Otherwise issue the instruction just fine.
1027 if (inst->isLoad()) {
1028 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1029 "encountered, adding to LSQ.\n", tid);
1030
1031 // Reserve a spot in the load store queue for this
1032 // memory access.
1033 ldstQueue.insertLoad(inst);
1034
1035 ++iewDispLoadInsts;
1036
1037 add_to_iq = true;
1038
1039 toRename->iewInfo[tid].dispatchedToLSQ++;
1040 } else if (inst->isStore()) {
1041 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1042 "encountered, adding to LSQ.\n", tid);
1043
1044 ldstQueue.insertStore(inst);
1045
1046 ++iewDispStoreInsts;
1047
1048 if (inst->isStoreConditional()) {
1049 // Store conditionals need to be set as "canCommit()"
1050 // so that commit can process them when they reach the
1051 // head of commit.
1052 // @todo: This is somewhat specific to Alpha.
1053 inst->setCanCommit();
1054 instQueue.insertNonSpec(inst);
1055 add_to_iq = false;
1056
1057 ++iewDispNonSpecInsts;
1058 } else {
1059 add_to_iq = true;
1060 }
1061
1062 toRename->iewInfo[tid].dispatchedToLSQ++;
1063#if FULL_SYSTEM
1064 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1065 // Same as non-speculative stores.
1066 inst->setCanCommit();
1067 instQueue.insertBarrier(inst);
1068 add_to_iq = false;
1069#endif
1070 } else if (inst->isNonSpeculative()) {
1071 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1072 "encountered, skipping.\n", tid);
1073
1074 // Same as non-speculative stores.
1075 inst->setCanCommit();
1076
1077 // Specifically insert it as nonspeculative.
1078 instQueue.insertNonSpec(inst);
1079
1080 ++iewDispNonSpecInsts;
1081
1082 add_to_iq = false;
1083 } else if (inst->isNop()) {
1084 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1085 "skipping.\n", tid);
1086
1087 inst->setIssued();
1088 inst->setExecuted();
1089 inst->setCanCommit();
1090
1091 instQueue.recordProducer(inst);
1092
1093 exeNop[tid]++;
1094
1095 add_to_iq = false;
1096 } else if (inst->isExecuted()) {
1097 assert(0 && "Instruction shouldn't be executed.\n");
1098 DPRINTF(IEW, "Issue: Executed branch encountered, "
1099 "skipping.\n");
1100
1101 inst->setIssued();
1102 inst->setCanCommit();
1103
1104 instQueue.recordProducer(inst);
1105
1106 add_to_iq = false;
1107 } else {
1108 add_to_iq = true;
1109 }
1110
1111 // If the instruction queue is not full, then add the
1112 // instruction.
1113 if (add_to_iq) {
1114 instQueue.insert(inst);
1115 }
1116
1117 insts_to_dispatch.pop();
1118
1119 toRename->iewInfo[tid].dispatched++;
1120
1121 ++iewDispatchedInsts;
1122 }
1123
1124 if (!insts_to_dispatch.empty()) {
1125 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1126 block(tid);
1127 toRename->iewUnblock[tid] = false;
1128 }
1129
1130 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1131 dispatchStatus[tid] = Running;
1132
1133 updatedQueues = true;
1134 }
1135
1136 dis_num_inst = 0;
1137}
1138
1139template <class Impl>
1140void
1141DefaultIEW<Impl>::printAvailableInsts()
1142{
1143 int inst = 0;
1144
1145 cout << "Available Instructions: ";
1146
1147 while (fromIssue->insts[inst]) {
1148
1149 if (inst%3==0) cout << "\n\t";
1150
1151 cout << "PC: " << fromIssue->insts[inst]->readPC()
1152 << " TN: " << fromIssue->insts[inst]->threadNumber
1153 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1154
1155 inst++;
1156
1157 }
1158
1159 cout << "\n";
1160}
1161
1162template <class Impl>
1163void
1164DefaultIEW<Impl>::executeInsts()
1165{
1166 wbNumInst = 0;
1167 wbCycle = 0;
1168
1169 list<unsigned>::iterator threads = (*activeThreads).begin();
1170
1171 while (threads != (*activeThreads).end()) {
1172 unsigned tid = *threads++;
1173 fetchRedirect[tid] = false;
1174 }
1175
|
1185#if 0
1186 printAvailableInsts();
1187#endif
| 1176 // Uncomment this if you want to see all available instructions.
1177// printAvailableInsts();
|
1188
1189 // Execute/writeback any instructions that are available.
1190 int insts_to_execute = fromIssue->size;
1191 int inst_num = 0;
1192 for (; inst_num < insts_to_execute;
1193 ++inst_num) {
1194
1195 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1196
1197 DynInstPtr inst = instQueue.getInstToExecute();
1198
1199 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1200 inst->readPC(), inst->threadNumber,inst->seqNum);
1201
1202 // Check if the instruction is squashed; if so then skip it
1203 if (inst->isSquashed()) {
1204 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1205
1206 // Consider this instruction executed so that commit can go
1207 // ahead and retire the instruction.
1208 inst->setExecuted();
1209
1210 // Not sure if I should set this here or just let commit try to
1211 // commit any squashed instructions. I like the latter a bit more.
1212 inst->setCanCommit();
1213
1214 ++iewExecSquashedInsts;
1215
1216 continue;
1217 }
1218
1219 Fault fault = NoFault;
1220
1221 // Execute instruction.
1222 // Note that if the instruction faults, it will be handled
1223 // at the commit stage.
1224 if (inst->isMemRef() &&
1225 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1226 DPRINTF(IEW, "Execute: Calculating address for memory "
1227 "reference.\n");
1228
1229 // Tell the LDSTQ to execute this instruction (if it is a load).
1230 if (inst->isLoad()) {
1231 // Loads will mark themselves as executed, and their writeback
1232 // event adds the instruction to the queue to commit
1233 fault = ldstQueue.executeLoad(inst);
1234 } else if (inst->isStore()) {
1235 ldstQueue.executeStore(inst);
1236
1237 // If the store had a fault then it may not have a mem req
1238 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1239 inst->setExecuted();
1240
1241 instToCommit(inst);
1242 }
1243
1244 // Store conditionals will mark themselves as
1245 // executed, and their writeback event will add the
1246 // instruction to the queue to commit.
1247 } else {
1248 panic("Unexpected memory type!\n");
1249 }
1250
1251 } else {
1252 inst->execute();
1253
1254 inst->setExecuted();
1255
1256 instToCommit(inst);
1257 }
1258
1259 updateExeInstStats(inst);
1260
1261 // Check if branch prediction was correct, if not then we need
1262 // to tell commit to squash in flight instructions. Only
1263 // handle this if there hasn't already been something that
1264 // redirects fetch in this group of instructions.
1265
1266 // This probably needs to prioritize the redirects if a different
1267 // scheduler is used. Currently the scheduler schedules the oldest
1268 // instruction first, so the branch resolution order will be correct.
1269 unsigned tid = inst->threadNumber;
1270
1271 if (!fetchRedirect[tid]) {
1272
1273 if (inst->mispredicted()) {
1274 fetchRedirect[tid] = true;
1275
1276 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1277 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1278 inst->nextPC);
1279
1280 // If incorrect, then signal the ROB that it must be squashed.
1281 squashDueToBranch(inst, tid);
1282
1283 if (inst->predTaken()) {
1284 predictedTakenIncorrect++;
1285 } else {
1286 predictedNotTakenIncorrect++;
1287 }
1288 } else if (ldstQueue.violation(tid)) {
1289 fetchRedirect[tid] = true;
1290
1291 // If there was an ordering violation, then get the
1292 // DynInst that caused the violation. Note that this
1293 // clears the violation signal.
1294 DynInstPtr violator;
1295 violator = ldstQueue.getMemDepViolator(tid);
1296
1297 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1298 "%#x, inst PC: %#x. Addr is: %#x.\n",
1299 violator->readPC(), inst->readPC(), inst->physEffAddr);
1300
1301 // Tell the instruction queue that a violation has occured.
1302 instQueue.violation(inst, violator);
1303
1304 // Squash.
1305 squashDueToMemOrder(inst,tid);
1306
1307 ++memOrderViolationEvents;
1308 } else if (ldstQueue.loadBlocked(tid) &&
1309 !ldstQueue.isLoadBlockedHandled(tid)) {
1310 fetchRedirect[tid] = true;
1311
1312 DPRINTF(IEW, "Load operation couldn't execute because the "
1313 "memory system is blocked. PC: %#x [sn:%lli]\n",
1314 inst->readPC(), inst->seqNum);
1315
1316 squashDueToMemBlocked(inst, tid);
1317 }
1318 }
1319 }
1320
1321 // Update and record activity if we processed any instructions.
1322 if (inst_num) {
1323 if (exeStatus == Idle) {
1324 exeStatus = Running;
1325 }
1326
1327 updatedQueues = true;
1328
1329 cpu->activityThisCycle();
1330 }
1331
1332 // Need to reset this in case a writeback event needs to write into the
1333 // iew queue. That way the writeback event will write into the correct
1334 // spot in the queue.
1335 wbNumInst = 0;
1336}
1337
1338template <class Impl>
1339void
1340DefaultIEW<Impl>::writebackInsts()
1341{
1342 // Loop through the head of the time buffer and wake any
1343 // dependents. These instructions are about to write back. Also
1344 // mark scoreboard that this instruction is finally complete.
1345 // Either have IEW have direct access to scoreboard, or have this
1346 // as part of backwards communication.
1347 for (int inst_num = 0; inst_num < issueWidth &&
1348 toCommit->insts[inst_num]; inst_num++) {
1349 DynInstPtr inst = toCommit->insts[inst_num];
1350 int tid = inst->threadNumber;
1351
| 1178
1179 // Execute/writeback any instructions that are available.
1180 int insts_to_execute = fromIssue->size;
1181 int inst_num = 0;
1182 for (; inst_num < insts_to_execute;
1183 ++inst_num) {
1184
1185 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1186
1187 DynInstPtr inst = instQueue.getInstToExecute();
1188
1189 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1190 inst->readPC(), inst->threadNumber,inst->seqNum);
1191
1192 // Check if the instruction is squashed; if so then skip it
1193 if (inst->isSquashed()) {
1194 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1195
1196 // Consider this instruction executed so that commit can go
1197 // ahead and retire the instruction.
1198 inst->setExecuted();
1199
1200 // Not sure if I should set this here or just let commit try to
1201 // commit any squashed instructions. I like the latter a bit more.
1202 inst->setCanCommit();
1203
1204 ++iewExecSquashedInsts;
1205
1206 continue;
1207 }
1208
1209 Fault fault = NoFault;
1210
1211 // Execute instruction.
1212 // Note that if the instruction faults, it will be handled
1213 // at the commit stage.
1214 if (inst->isMemRef() &&
1215 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1216 DPRINTF(IEW, "Execute: Calculating address for memory "
1217 "reference.\n");
1218
1219 // Tell the LDSTQ to execute this instruction (if it is a load).
1220 if (inst->isLoad()) {
1221 // Loads will mark themselves as executed, and their writeback
1222 // event adds the instruction to the queue to commit
1223 fault = ldstQueue.executeLoad(inst);
1224 } else if (inst->isStore()) {
1225 ldstQueue.executeStore(inst);
1226
1227 // If the store had a fault then it may not have a mem req
1228 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1229 inst->setExecuted();
1230
1231 instToCommit(inst);
1232 }
1233
1234 // Store conditionals will mark themselves as
1235 // executed, and their writeback event will add the
1236 // instruction to the queue to commit.
1237 } else {
1238 panic("Unexpected memory type!\n");
1239 }
1240
1241 } else {
1242 inst->execute();
1243
1244 inst->setExecuted();
1245
1246 instToCommit(inst);
1247 }
1248
1249 updateExeInstStats(inst);
1250
1251 // Check if branch prediction was correct, if not then we need
1252 // to tell commit to squash in flight instructions. Only
1253 // handle this if there hasn't already been something that
1254 // redirects fetch in this group of instructions.
1255
1256 // This probably needs to prioritize the redirects if a different
1257 // scheduler is used. Currently the scheduler schedules the oldest
1258 // instruction first, so the branch resolution order will be correct.
1259 unsigned tid = inst->threadNumber;
1260
1261 if (!fetchRedirect[tid]) {
1262
1263 if (inst->mispredicted()) {
1264 fetchRedirect[tid] = true;
1265
1266 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1267 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1268 inst->nextPC);
1269
1270 // If incorrect, then signal the ROB that it must be squashed.
1271 squashDueToBranch(inst, tid);
1272
1273 if (inst->predTaken()) {
1274 predictedTakenIncorrect++;
1275 } else {
1276 predictedNotTakenIncorrect++;
1277 }
1278 } else if (ldstQueue.violation(tid)) {
1279 fetchRedirect[tid] = true;
1280
1281 // If there was an ordering violation, then get the
1282 // DynInst that caused the violation. Note that this
1283 // clears the violation signal.
1284 DynInstPtr violator;
1285 violator = ldstQueue.getMemDepViolator(tid);
1286
1287 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1288 "%#x, inst PC: %#x. Addr is: %#x.\n",
1289 violator->readPC(), inst->readPC(), inst->physEffAddr);
1290
1291 // Tell the instruction queue that a violation has occured.
1292 instQueue.violation(inst, violator);
1293
1294 // Squash.
1295 squashDueToMemOrder(inst,tid);
1296
1297 ++memOrderViolationEvents;
1298 } else if (ldstQueue.loadBlocked(tid) &&
1299 !ldstQueue.isLoadBlockedHandled(tid)) {
1300 fetchRedirect[tid] = true;
1301
1302 DPRINTF(IEW, "Load operation couldn't execute because the "
1303 "memory system is blocked. PC: %#x [sn:%lli]\n",
1304 inst->readPC(), inst->seqNum);
1305
1306 squashDueToMemBlocked(inst, tid);
1307 }
1308 }
1309 }
1310
1311 // Update and record activity if we processed any instructions.
1312 if (inst_num) {
1313 if (exeStatus == Idle) {
1314 exeStatus = Running;
1315 }
1316
1317 updatedQueues = true;
1318
1319 cpu->activityThisCycle();
1320 }
1321
1322 // Need to reset this in case a writeback event needs to write into the
1323 // iew queue. That way the writeback event will write into the correct
1324 // spot in the queue.
1325 wbNumInst = 0;
1326}
1327
1328template <class Impl>
1329void
1330DefaultIEW<Impl>::writebackInsts()
1331{
1332 // Loop through the head of the time buffer and wake any
1333 // dependents. These instructions are about to write back. Also
1334 // mark scoreboard that this instruction is finally complete.
1335 // Either have IEW have direct access to scoreboard, or have this
1336 // as part of backwards communication.
1337 for (int inst_num = 0; inst_num < issueWidth &&
1338 toCommit->insts[inst_num]; inst_num++) {
1339 DynInstPtr inst = toCommit->insts[inst_num];
1340 int tid = inst->threadNumber;
1341
|
1352 DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
1353 inst->readPC());
| 1342 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1343 inst->seqNum, inst->readPC());
|
1354
1355 iewInstsToCommit[tid]++;
1356
1357 // Some instructions will be sent to commit without having
1358 // executed because they need commit to handle them.
1359 // E.g. Uncached loads have not actually executed when they
1360 // are first sent to commit. Instead commit must tell the LSQ
1361 // when it's ready to execute the uncached load.
1362 if (!inst->isSquashed() && inst->isExecuted()) {
1363 int dependents = instQueue.wakeDependents(inst);
1364
1365 for (int i = 0; i < inst->numDestRegs(); i++) {
1366 //mark as Ready
1367 DPRINTF(IEW,"Setting Destination Register %i\n",
1368 inst->renamedDestRegIdx(i));
1369 scoreboard->setReg(inst->renamedDestRegIdx(i));
1370 }
1371
1372 if (dependents) {
1373 producerInst[tid]++;
1374 consumerInst[tid]+= dependents;
1375 }
1376 writebackCount[tid]++;
1377 }
1378 }
1379}
1380
1381template<class Impl>
1382void
1383DefaultIEW<Impl>::tick()
1384{
1385 wbNumInst = 0;
1386 wbCycle = 0;
1387
1388 wroteToTimeBuffer = false;
1389 updatedQueues = false;
1390
1391 sortInsts();
1392
1393 // Free function units marked as being freed this cycle.
1394 fuPool->processFreeUnits();
1395
1396 list<unsigned>::iterator threads = (*activeThreads).begin();
1397
1398 // Check stall and squash signals, dispatch any instructions.
1399 while (threads != (*activeThreads).end()) {
1400 unsigned tid = *threads++;
1401
1402 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1403
1404 checkSignalsAndUpdate(tid);
1405 dispatch(tid);
1406 }
1407
1408 if (exeStatus != Squashing) {
1409 executeInsts();
1410
1411 writebackInsts();
1412
1413 // Have the instruction queue try to schedule any ready instructions.
1414 // (In actuality, this scheduling is for instructions that will
1415 // be executed next cycle.)
1416 instQueue.scheduleReadyInsts();
1417
1418 // Also should advance its own time buffers if the stage ran.
1419 // Not the best place for it, but this works (hopefully).
1420 issueToExecQueue.advance();
1421 }
1422
1423 bool broadcast_free_entries = false;
1424
1425 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1426 exeStatus = Idle;
1427 updateLSQNextCycle = false;
1428
1429 broadcast_free_entries = true;
1430 }
1431
1432 // Writeback any stores using any leftover bandwidth.
1433 ldstQueue.writebackStores();
1434
1435 // Check the committed load/store signals to see if there's a load
1436 // or store to commit. Also check if it's being told to execute a
1437 // nonspeculative instruction.
1438 // This is pretty inefficient...
1439
1440 threads = (*activeThreads).begin();
1441 while (threads != (*activeThreads).end()) {
1442 unsigned tid = (*threads++);
1443
1444 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1445
1446 // Update structures based on instructions committed.
1447 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1448 !fromCommit->commitInfo[tid].squash &&
1449 !fromCommit->commitInfo[tid].robSquashing) {
1450
1451 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1452
1453 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1454
1455 updateLSQNextCycle = true;
1456 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1457 }
1458
1459 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1460
1461 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1462 if (fromCommit->commitInfo[tid].uncached) {
1463 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1464 } else {
1465 instQueue.scheduleNonSpec(
1466 fromCommit->commitInfo[tid].nonSpecSeqNum);
1467 }
1468 }
1469
1470 if (broadcast_free_entries) {
1471 toFetch->iewInfo[tid].iqCount =
1472 instQueue.getCount(tid);
1473 toFetch->iewInfo[tid].ldstqCount =
1474 ldstQueue.getCount(tid);
1475
1476 toRename->iewInfo[tid].usedIQ = true;
1477 toRename->iewInfo[tid].freeIQEntries =
1478 instQueue.numFreeEntries();
1479 toRename->iewInfo[tid].usedLSQ = true;
1480 toRename->iewInfo[tid].freeLSQEntries =
1481 ldstQueue.numFreeEntries(tid);
1482
1483 wroteToTimeBuffer = true;
1484 }
1485
1486 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1487 tid, toRename->iewInfo[tid].dispatched);
1488 }
1489
1490 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1491 "LSQ has %i free entries.\n",
1492 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1493 ldstQueue.numFreeEntries());
1494
1495 updateStatus();
1496
1497 if (wroteToTimeBuffer) {
1498 DPRINTF(Activity, "Activity this cycle.\n");
1499 cpu->activityThisCycle();
1500 }
1501}
1502
1503template <class Impl>
1504void
1505DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1506{
1507 int thread_number = inst->threadNumber;
1508
1509 //
1510 // Pick off the software prefetches
1511 //
1512#ifdef TARGET_ALPHA
1513 if (inst->isDataPrefetch())
1514 exeSwp[thread_number]++;
1515 else
1516 iewExecutedInsts++;
1517#else
1518 iewExecutedInsts++;
1519#endif
1520
1521 //
1522 // Control operations
1523 //
1524 if (inst->isControl())
1525 exeBranches[thread_number]++;
1526
1527 //
1528 // Memory operations
1529 //
1530 if (inst->isMemRef()) {
1531 exeRefs[thread_number]++;
1532
1533 if (inst->isLoad()) {
1534 iewExecLoadInsts[thread_number]++;
1535 }
1536 }
1537}
| 1344
1345 iewInstsToCommit[tid]++;
1346
1347 // Some instructions will be sent to commit without having
1348 // executed because they need commit to handle them.
1349 // E.g. Uncached loads have not actually executed when they
1350 // are first sent to commit. Instead commit must tell the LSQ
1351 // when it's ready to execute the uncached load.
1352 if (!inst->isSquashed() && inst->isExecuted()) {
1353 int dependents = instQueue.wakeDependents(inst);
1354
1355 for (int i = 0; i < inst->numDestRegs(); i++) {
1356 //mark as Ready
1357 DPRINTF(IEW,"Setting Destination Register %i\n",
1358 inst->renamedDestRegIdx(i));
1359 scoreboard->setReg(inst->renamedDestRegIdx(i));
1360 }
1361
1362 if (dependents) {
1363 producerInst[tid]++;
1364 consumerInst[tid]+= dependents;
1365 }
1366 writebackCount[tid]++;
1367 }
1368 }
1369}
1370
1371template<class Impl>
1372void
1373DefaultIEW<Impl>::tick()
1374{
1375 wbNumInst = 0;
1376 wbCycle = 0;
1377
1378 wroteToTimeBuffer = false;
1379 updatedQueues = false;
1380
1381 sortInsts();
1382
1383 // Free function units marked as being freed this cycle.
1384 fuPool->processFreeUnits();
1385
1386 list<unsigned>::iterator threads = (*activeThreads).begin();
1387
1388 // Check stall and squash signals, dispatch any instructions.
1389 while (threads != (*activeThreads).end()) {
1390 unsigned tid = *threads++;
1391
1392 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1393
1394 checkSignalsAndUpdate(tid);
1395 dispatch(tid);
1396 }
1397
1398 if (exeStatus != Squashing) {
1399 executeInsts();
1400
1401 writebackInsts();
1402
1403 // Have the instruction queue try to schedule any ready instructions.
1404 // (In actuality, this scheduling is for instructions that will
1405 // be executed next cycle.)
1406 instQueue.scheduleReadyInsts();
1407
1408 // Also should advance its own time buffers if the stage ran.
1409 // Not the best place for it, but this works (hopefully).
1410 issueToExecQueue.advance();
1411 }
1412
1413 bool broadcast_free_entries = false;
1414
1415 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1416 exeStatus = Idle;
1417 updateLSQNextCycle = false;
1418
1419 broadcast_free_entries = true;
1420 }
1421
1422 // Writeback any stores using any leftover bandwidth.
1423 ldstQueue.writebackStores();
1424
1425 // Check the committed load/store signals to see if there's a load
1426 // or store to commit. Also check if it's being told to execute a
1427 // nonspeculative instruction.
1428 // This is pretty inefficient...
1429
1430 threads = (*activeThreads).begin();
1431 while (threads != (*activeThreads).end()) {
1432 unsigned tid = (*threads++);
1433
1434 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1435
1436 // Update structures based on instructions committed.
1437 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1438 !fromCommit->commitInfo[tid].squash &&
1439 !fromCommit->commitInfo[tid].robSquashing) {
1440
1441 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1442
1443 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1444
1445 updateLSQNextCycle = true;
1446 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1447 }
1448
1449 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1450
1451 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1452 if (fromCommit->commitInfo[tid].uncached) {
1453 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1454 } else {
1455 instQueue.scheduleNonSpec(
1456 fromCommit->commitInfo[tid].nonSpecSeqNum);
1457 }
1458 }
1459
1460 if (broadcast_free_entries) {
1461 toFetch->iewInfo[tid].iqCount =
1462 instQueue.getCount(tid);
1463 toFetch->iewInfo[tid].ldstqCount =
1464 ldstQueue.getCount(tid);
1465
1466 toRename->iewInfo[tid].usedIQ = true;
1467 toRename->iewInfo[tid].freeIQEntries =
1468 instQueue.numFreeEntries();
1469 toRename->iewInfo[tid].usedLSQ = true;
1470 toRename->iewInfo[tid].freeLSQEntries =
1471 ldstQueue.numFreeEntries(tid);
1472
1473 wroteToTimeBuffer = true;
1474 }
1475
1476 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1477 tid, toRename->iewInfo[tid].dispatched);
1478 }
1479
1480 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1481 "LSQ has %i free entries.\n",
1482 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1483 ldstQueue.numFreeEntries());
1484
1485 updateStatus();
1486
1487 if (wroteToTimeBuffer) {
1488 DPRINTF(Activity, "Activity this cycle.\n");
1489 cpu->activityThisCycle();
1490 }
1491}
1492
1493template <class Impl>
1494void
1495DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1496{
1497 int thread_number = inst->threadNumber;
1498
1499 //
1500 // Pick off the software prefetches
1501 //
1502#ifdef TARGET_ALPHA
1503 if (inst->isDataPrefetch())
1504 exeSwp[thread_number]++;
1505 else
1506 iewExecutedInsts++;
1507#else
1508 iewExecutedInsts++;
1509#endif
1510
1511 //
1512 // Control operations
1513 //
1514 if (inst->isControl())
1515 exeBranches[thread_number]++;
1516
1517 //
1518 // Memory operations
1519 //
1520 if (inst->isMemRef()) {
1521 exeRefs[thread_number]++;
1522
1523 if (inst->isLoad()) {
1524 iewExecLoadInsts[thread_number]++;
1525 }
1526 }
1527}
|