1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 45#define __CPU_O3_IEW_IMPL_IMPL_HH__ 46 47// @todo: Fix the instantaneous communication among all the stages within 48// iew. There's a clear delay between issue and execute, yet backwards 49// communication happens simultaneously. 50 51#include <queue> 52 53#include "arch/utility.hh" 54#include "config/the_isa.hh" 55#include "cpu/checker/cpu.hh" 56#include "cpu/o3/fu_pool.hh" 57#include "cpu/o3/iew.hh" 58#include "cpu/timebuf.hh" 59#include "debug/Activity.hh" 60#include "debug/Drain.hh" 61#include "debug/IEW.hh" 62#include "debug/O3PipeView.hh" 63#include "params/DerivO3CPU.hh" 64 65using namespace std; 66 67template<class Impl> 68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 69 : issueToExecQueue(params->backComSize, params->forwardComSize), 70 cpu(_cpu), 71 instQueue(_cpu, this, params), 72 ldstQueue(_cpu, this, params), 73 fuPool(params->fuPool), 74 commitToIEWDelay(params->commitToIEWDelay), 75 renameToIEWDelay(params->renameToIEWDelay), 76 issueToExecuteDelay(params->issueToExecuteDelay), 77 dispatchWidth(params->dispatchWidth), 78 issueWidth(params->issueWidth), 79 wbWidth(params->wbWidth), 80 numThreads(params->numThreads) 81{ 82 if (dispatchWidth > Impl::MaxWidth) 83 fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 84 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 85 dispatchWidth, static_cast<int>(Impl::MaxWidth)); 86 if (issueWidth > Impl::MaxWidth) 87 fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 88 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 89 issueWidth, static_cast<int>(Impl::MaxWidth)); 90 if (wbWidth > Impl::MaxWidth) 91 fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 92 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 93 wbWidth, static_cast<int>(Impl::MaxWidth)); 94 95 _status = Active; 96 exeStatus = Running; 97 wbStatus = Idle; 98 99 // Setup wire to read instructions coming from issue. 100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 101 102 // Instruction queue needs the queue between issue and execute. 103 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 104 105 for (ThreadID tid = 0; tid < numThreads; tid++) { 106 dispatchStatus[tid] = Running; 107 fetchRedirect[tid] = false; 108 } 109 110 updateLSQNextCycle = false; 111 112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 113} 114 115template <class Impl> 116std::string 117DefaultIEW<Impl>::name() const 118{ 119 return cpu->name() + ".iew"; 120} 121 122template <class Impl> 123void 124DefaultIEW<Impl>::regProbePoints() 125{ 126 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 127 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 128 /** 129 * Probe point with dynamic instruction as the argument used to probe when 130 * an instruction starts to execute. 131 */ 132 ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 133 "Execute"); 134 /** 135 * Probe point with dynamic instruction as the argument used to probe when 136 * an instruction execution completes and it is marked ready to commit. 137 */ 138 ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 139 "ToCommit"); 140} 141 142template <class Impl> 143void 144DefaultIEW<Impl>::regStats() 145{ 146 using namespace Stats; 147 148 instQueue.regStats(); 149 ldstQueue.regStats(); 150 151 iewIdleCycles 152 .name(name() + ".iewIdleCycles") 153 .desc("Number of cycles IEW is idle"); 154 155 iewSquashCycles 156 .name(name() + ".iewSquashCycles") 157 .desc("Number of cycles IEW is squashing"); 158 159 iewBlockCycles 160 .name(name() + ".iewBlockCycles") 161 .desc("Number of cycles IEW is blocking"); 162 163 iewUnblockCycles 164 .name(name() + ".iewUnblockCycles") 165 .desc("Number of cycles IEW is unblocking"); 166 167 iewDispatchedInsts 168 .name(name() + ".iewDispatchedInsts") 169 .desc("Number of instructions dispatched to IQ"); 170 171 iewDispSquashedInsts 172 .name(name() + ".iewDispSquashedInsts") 173 .desc("Number of squashed instructions skipped by dispatch"); 174 175 iewDispLoadInsts 176 .name(name() + ".iewDispLoadInsts") 177 .desc("Number of dispatched load instructions"); 178 179 iewDispStoreInsts 180 .name(name() + ".iewDispStoreInsts") 181 .desc("Number of dispatched store instructions"); 182 183 iewDispNonSpecInsts 184 .name(name() + ".iewDispNonSpecInsts") 185 .desc("Number of dispatched non-speculative instructions"); 186 187 iewIQFullEvents 188 .name(name() + ".iewIQFullEvents") 189 .desc("Number of times the IQ has become full, causing a stall"); 190 191 iewLSQFullEvents 192 .name(name() + ".iewLSQFullEvents") 193 .desc("Number of times the LSQ has become full, causing a stall"); 194 195 memOrderViolationEvents 196 .name(name() + ".memOrderViolationEvents") 197 .desc("Number of memory order violations"); 198 199 predictedTakenIncorrect 200 .name(name() + ".predictedTakenIncorrect") 201 .desc("Number of branches that were predicted taken incorrectly"); 202 203 predictedNotTakenIncorrect 204 .name(name() + ".predictedNotTakenIncorrect") 205 .desc("Number of branches that were predicted not taken incorrectly"); 206 207 branchMispredicts 208 .name(name() + ".branchMispredicts") 209 .desc("Number of branch mispredicts detected at execute"); 210 211 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 212 213 iewExecutedInsts 214 .name(name() + ".iewExecutedInsts") 215 .desc("Number of executed instructions"); 216 217 iewExecLoadInsts 218 .init(cpu->numThreads) 219 .name(name() + ".iewExecLoadInsts") 220 .desc("Number of load instructions executed") 221 .flags(total); 222 223 iewExecSquashedInsts 224 .name(name() + ".iewExecSquashedInsts") 225 .desc("Number of squashed instructions skipped in execute"); 226 227 iewExecutedSwp 228 .init(cpu->numThreads) 229 .name(name() + ".exec_swp") 230 .desc("number of swp insts executed") 231 .flags(total); 232 233 iewExecutedNop 234 .init(cpu->numThreads) 235 .name(name() + ".exec_nop") 236 .desc("number of nop insts executed") 237 .flags(total); 238 239 iewExecutedRefs 240 .init(cpu->numThreads) 241 .name(name() + ".exec_refs") 242 .desc("number of memory reference insts executed") 243 .flags(total); 244 245 iewExecutedBranches 246 .init(cpu->numThreads) 247 .name(name() + ".exec_branches") 248 .desc("Number of branches executed") 249 .flags(total); 250 251 iewExecStoreInsts 252 .name(name() + ".exec_stores") 253 .desc("Number of stores executed") 254 .flags(total); 255 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 256 257 iewExecRate 258 .name(name() + ".exec_rate") 259 .desc("Inst execution rate") 260 .flags(total); 261 262 iewExecRate = iewExecutedInsts / cpu->numCycles; 263 264 iewInstsToCommit 265 .init(cpu->numThreads) 266 .name(name() + ".wb_sent") 267 .desc("cumulative count of insts sent to commit") 268 .flags(total); 269 270 writebackCount 271 .init(cpu->numThreads) 272 .name(name() + ".wb_count") 273 .desc("cumulative count of insts written-back") 274 .flags(total); 275 276 producerInst 277 .init(cpu->numThreads) 278 .name(name() + ".wb_producers") 279 .desc("num instructions producing a value") 280 .flags(total); 281 282 consumerInst 283 .init(cpu->numThreads) 284 .name(name() + ".wb_consumers") 285 .desc("num instructions consuming a value") 286 .flags(total); 287 288 wbFanout 289 .name(name() + ".wb_fanout") 290 .desc("average fanout of values written-back") 291 .flags(total); 292 293 wbFanout = producerInst / consumerInst; 294 295 wbRate 296 .name(name() + ".wb_rate") 297 .desc("insts written-back per cycle") 298 .flags(total); 299 wbRate = writebackCount / cpu->numCycles; 300} 301 302template<class Impl> 303void 304DefaultIEW<Impl>::startupStage() 305{ 306 for (ThreadID tid = 0; tid < numThreads; tid++) { 307 toRename->iewInfo[tid].usedIQ = true; 308 toRename->iewInfo[tid].freeIQEntries = 309 instQueue.numFreeEntries(tid); 310 311 toRename->iewInfo[tid].usedLSQ = true; 312 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 313 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 314 } 315 316 // Initialize the checker's dcache port here 317 if (cpu->checker) { 318 cpu->checker->setDcachePort(&cpu->getDataPort()); 319 } 320 321 cpu->activateStage(O3CPU::IEWIdx); 322} 323 324template<class Impl> 325void 326DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 327{ 328 timeBuffer = tb_ptr; 329 330 // Setup wire to read information from time buffer, from commit. 331 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 332 333 // Setup wire to write information back to previous stages. 334 toRename = timeBuffer->getWire(0); 335 336 toFetch = timeBuffer->getWire(0); 337 338 // Instruction queue also needs main time buffer. 339 instQueue.setTimeBuffer(tb_ptr); 340} 341 342template<class Impl> 343void 344DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 345{ 346 renameQueue = rq_ptr; 347 348 // Setup wire to read information from rename queue. 349 fromRename = renameQueue->getWire(-renameToIEWDelay); 350} 351 352template<class Impl> 353void 354DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 355{ 356 iewQueue = iq_ptr; 357 358 // Setup wire to write instructions to commit. 359 toCommit = iewQueue->getWire(0); 360} 361 362template<class Impl> 363void 364DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 365{ 366 activeThreads = at_ptr; 367 368 ldstQueue.setActiveThreads(at_ptr); 369 instQueue.setActiveThreads(at_ptr); 370} 371 372template<class Impl> 373void 374DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 375{ 376 scoreboard = sb_ptr; 377} 378 379template <class Impl> 380bool 381DefaultIEW<Impl>::isDrained() const 382{ 383 bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 384 385 for (ThreadID tid = 0; tid < numThreads; tid++) { 386 if (!insts[tid].empty()) { 387 DPRINTF(Drain, "%i: Insts not empty.\n", tid); 388 drained = false; 389 } 390 if (!skidBuffer[tid].empty()) { 391 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 392 drained = false; 393 }
| 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 45#define __CPU_O3_IEW_IMPL_IMPL_HH__ 46 47// @todo: Fix the instantaneous communication among all the stages within 48// iew. There's a clear delay between issue and execute, yet backwards 49// communication happens simultaneously. 50 51#include <queue> 52 53#include "arch/utility.hh" 54#include "config/the_isa.hh" 55#include "cpu/checker/cpu.hh" 56#include "cpu/o3/fu_pool.hh" 57#include "cpu/o3/iew.hh" 58#include "cpu/timebuf.hh" 59#include "debug/Activity.hh" 60#include "debug/Drain.hh" 61#include "debug/IEW.hh" 62#include "debug/O3PipeView.hh" 63#include "params/DerivO3CPU.hh" 64 65using namespace std; 66 67template<class Impl> 68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 69 : issueToExecQueue(params->backComSize, params->forwardComSize), 70 cpu(_cpu), 71 instQueue(_cpu, this, params), 72 ldstQueue(_cpu, this, params), 73 fuPool(params->fuPool), 74 commitToIEWDelay(params->commitToIEWDelay), 75 renameToIEWDelay(params->renameToIEWDelay), 76 issueToExecuteDelay(params->issueToExecuteDelay), 77 dispatchWidth(params->dispatchWidth), 78 issueWidth(params->issueWidth), 79 wbWidth(params->wbWidth), 80 numThreads(params->numThreads) 81{ 82 if (dispatchWidth > Impl::MaxWidth) 83 fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 84 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 85 dispatchWidth, static_cast<int>(Impl::MaxWidth)); 86 if (issueWidth > Impl::MaxWidth) 87 fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 88 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 89 issueWidth, static_cast<int>(Impl::MaxWidth)); 90 if (wbWidth > Impl::MaxWidth) 91 fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 92 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 93 wbWidth, static_cast<int>(Impl::MaxWidth)); 94 95 _status = Active; 96 exeStatus = Running; 97 wbStatus = Idle; 98 99 // Setup wire to read instructions coming from issue. 100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 101 102 // Instruction queue needs the queue between issue and execute. 103 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 104 105 for (ThreadID tid = 0; tid < numThreads; tid++) { 106 dispatchStatus[tid] = Running; 107 fetchRedirect[tid] = false; 108 } 109 110 updateLSQNextCycle = false; 111 112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 113} 114 115template <class Impl> 116std::string 117DefaultIEW<Impl>::name() const 118{ 119 return cpu->name() + ".iew"; 120} 121 122template <class Impl> 123void 124DefaultIEW<Impl>::regProbePoints() 125{ 126 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 127 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 128 /** 129 * Probe point with dynamic instruction as the argument used to probe when 130 * an instruction starts to execute. 131 */ 132 ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 133 "Execute"); 134 /** 135 * Probe point with dynamic instruction as the argument used to probe when 136 * an instruction execution completes and it is marked ready to commit. 137 */ 138 ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 139 "ToCommit"); 140} 141 142template <class Impl> 143void 144DefaultIEW<Impl>::regStats() 145{ 146 using namespace Stats; 147 148 instQueue.regStats(); 149 ldstQueue.regStats(); 150 151 iewIdleCycles 152 .name(name() + ".iewIdleCycles") 153 .desc("Number of cycles IEW is idle"); 154 155 iewSquashCycles 156 .name(name() + ".iewSquashCycles") 157 .desc("Number of cycles IEW is squashing"); 158 159 iewBlockCycles 160 .name(name() + ".iewBlockCycles") 161 .desc("Number of cycles IEW is blocking"); 162 163 iewUnblockCycles 164 .name(name() + ".iewUnblockCycles") 165 .desc("Number of cycles IEW is unblocking"); 166 167 iewDispatchedInsts 168 .name(name() + ".iewDispatchedInsts") 169 .desc("Number of instructions dispatched to IQ"); 170 171 iewDispSquashedInsts 172 .name(name() + ".iewDispSquashedInsts") 173 .desc("Number of squashed instructions skipped by dispatch"); 174 175 iewDispLoadInsts 176 .name(name() + ".iewDispLoadInsts") 177 .desc("Number of dispatched load instructions"); 178 179 iewDispStoreInsts 180 .name(name() + ".iewDispStoreInsts") 181 .desc("Number of dispatched store instructions"); 182 183 iewDispNonSpecInsts 184 .name(name() + ".iewDispNonSpecInsts") 185 .desc("Number of dispatched non-speculative instructions"); 186 187 iewIQFullEvents 188 .name(name() + ".iewIQFullEvents") 189 .desc("Number of times the IQ has become full, causing a stall"); 190 191 iewLSQFullEvents 192 .name(name() + ".iewLSQFullEvents") 193 .desc("Number of times the LSQ has become full, causing a stall"); 194 195 memOrderViolationEvents 196 .name(name() + ".memOrderViolationEvents") 197 .desc("Number of memory order violations"); 198 199 predictedTakenIncorrect 200 .name(name() + ".predictedTakenIncorrect") 201 .desc("Number of branches that were predicted taken incorrectly"); 202 203 predictedNotTakenIncorrect 204 .name(name() + ".predictedNotTakenIncorrect") 205 .desc("Number of branches that were predicted not taken incorrectly"); 206 207 branchMispredicts 208 .name(name() + ".branchMispredicts") 209 .desc("Number of branch mispredicts detected at execute"); 210 211 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 212 213 iewExecutedInsts 214 .name(name() + ".iewExecutedInsts") 215 .desc("Number of executed instructions"); 216 217 iewExecLoadInsts 218 .init(cpu->numThreads) 219 .name(name() + ".iewExecLoadInsts") 220 .desc("Number of load instructions executed") 221 .flags(total); 222 223 iewExecSquashedInsts 224 .name(name() + ".iewExecSquashedInsts") 225 .desc("Number of squashed instructions skipped in execute"); 226 227 iewExecutedSwp 228 .init(cpu->numThreads) 229 .name(name() + ".exec_swp") 230 .desc("number of swp insts executed") 231 .flags(total); 232 233 iewExecutedNop 234 .init(cpu->numThreads) 235 .name(name() + ".exec_nop") 236 .desc("number of nop insts executed") 237 .flags(total); 238 239 iewExecutedRefs 240 .init(cpu->numThreads) 241 .name(name() + ".exec_refs") 242 .desc("number of memory reference insts executed") 243 .flags(total); 244 245 iewExecutedBranches 246 .init(cpu->numThreads) 247 .name(name() + ".exec_branches") 248 .desc("Number of branches executed") 249 .flags(total); 250 251 iewExecStoreInsts 252 .name(name() + ".exec_stores") 253 .desc("Number of stores executed") 254 .flags(total); 255 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 256 257 iewExecRate 258 .name(name() + ".exec_rate") 259 .desc("Inst execution rate") 260 .flags(total); 261 262 iewExecRate = iewExecutedInsts / cpu->numCycles; 263 264 iewInstsToCommit 265 .init(cpu->numThreads) 266 .name(name() + ".wb_sent") 267 .desc("cumulative count of insts sent to commit") 268 .flags(total); 269 270 writebackCount 271 .init(cpu->numThreads) 272 .name(name() + ".wb_count") 273 .desc("cumulative count of insts written-back") 274 .flags(total); 275 276 producerInst 277 .init(cpu->numThreads) 278 .name(name() + ".wb_producers") 279 .desc("num instructions producing a value") 280 .flags(total); 281 282 consumerInst 283 .init(cpu->numThreads) 284 .name(name() + ".wb_consumers") 285 .desc("num instructions consuming a value") 286 .flags(total); 287 288 wbFanout 289 .name(name() + ".wb_fanout") 290 .desc("average fanout of values written-back") 291 .flags(total); 292 293 wbFanout = producerInst / consumerInst; 294 295 wbRate 296 .name(name() + ".wb_rate") 297 .desc("insts written-back per cycle") 298 .flags(total); 299 wbRate = writebackCount / cpu->numCycles; 300} 301 302template<class Impl> 303void 304DefaultIEW<Impl>::startupStage() 305{ 306 for (ThreadID tid = 0; tid < numThreads; tid++) { 307 toRename->iewInfo[tid].usedIQ = true; 308 toRename->iewInfo[tid].freeIQEntries = 309 instQueue.numFreeEntries(tid); 310 311 toRename->iewInfo[tid].usedLSQ = true; 312 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 313 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 314 } 315 316 // Initialize the checker's dcache port here 317 if (cpu->checker) { 318 cpu->checker->setDcachePort(&cpu->getDataPort()); 319 } 320 321 cpu->activateStage(O3CPU::IEWIdx); 322} 323 324template<class Impl> 325void 326DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 327{ 328 timeBuffer = tb_ptr; 329 330 // Setup wire to read information from time buffer, from commit. 331 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 332 333 // Setup wire to write information back to previous stages. 334 toRename = timeBuffer->getWire(0); 335 336 toFetch = timeBuffer->getWire(0); 337 338 // Instruction queue also needs main time buffer. 339 instQueue.setTimeBuffer(tb_ptr); 340} 341 342template<class Impl> 343void 344DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 345{ 346 renameQueue = rq_ptr; 347 348 // Setup wire to read information from rename queue. 349 fromRename = renameQueue->getWire(-renameToIEWDelay); 350} 351 352template<class Impl> 353void 354DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 355{ 356 iewQueue = iq_ptr; 357 358 // Setup wire to write instructions to commit. 359 toCommit = iewQueue->getWire(0); 360} 361 362template<class Impl> 363void 364DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 365{ 366 activeThreads = at_ptr; 367 368 ldstQueue.setActiveThreads(at_ptr); 369 instQueue.setActiveThreads(at_ptr); 370} 371 372template<class Impl> 373void 374DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 375{ 376 scoreboard = sb_ptr; 377} 378 379template <class Impl> 380bool 381DefaultIEW<Impl>::isDrained() const 382{ 383 bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 384 385 for (ThreadID tid = 0; tid < numThreads; tid++) { 386 if (!insts[tid].empty()) { 387 DPRINTF(Drain, "%i: Insts not empty.\n", tid); 388 drained = false; 389 } 390 if (!skidBuffer[tid].empty()) { 391 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 392 drained = false; 393 }
|
394 } 395 396 // Also check the FU pool as instructions are "stored" in FU 397 // completion events until they are done and not accounted for 398 // above 399 if (drained && !fuPool->isDrained()) { 400 DPRINTF(Drain, "FU pool still busy.\n"); 401 drained = false; 402 } 403 404 return drained; 405} 406 407template <class Impl> 408void 409DefaultIEW<Impl>::drainSanityCheck() const 410{ 411 assert(isDrained()); 412 413 instQueue.drainSanityCheck(); 414 ldstQueue.drainSanityCheck(); 415} 416 417template <class Impl> 418void 419DefaultIEW<Impl>::takeOverFrom() 420{ 421 // Reset all state. 422 _status = Active; 423 exeStatus = Running; 424 wbStatus = Idle; 425 426 instQueue.takeOverFrom(); 427 ldstQueue.takeOverFrom(); 428 fuPool->takeOverFrom(); 429 430 startupStage(); 431 cpu->activityThisCycle(); 432 433 for (ThreadID tid = 0; tid < numThreads; tid++) { 434 dispatchStatus[tid] = Running; 435 fetchRedirect[tid] = false; 436 } 437 438 updateLSQNextCycle = false; 439 440 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 441 issueToExecQueue.advance(); 442 } 443} 444 445template<class Impl> 446void 447DefaultIEW<Impl>::squash(ThreadID tid) 448{ 449 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 450 451 // Tell the IQ to start squashing. 452 instQueue.squash(tid); 453 454 // Tell the LDSTQ to start squashing. 455 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 456 updatedQueues = true; 457 458 // Clear the skid buffer in case it has any data in it. 459 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 460 tid, fromCommit->commitInfo[tid].doneSeqNum); 461 462 while (!skidBuffer[tid].empty()) { 463 if (skidBuffer[tid].front()->isLoad()) { 464 toRename->iewInfo[tid].dispatchedToLQ++; 465 } 466 if (skidBuffer[tid].front()->isStore()) { 467 toRename->iewInfo[tid].dispatchedToSQ++; 468 } 469 470 toRename->iewInfo[tid].dispatched++; 471 472 skidBuffer[tid].pop(); 473 } 474 475 emptyRenameInsts(tid); 476} 477 478template<class Impl> 479void 480DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 481{ 482 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 483 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 484 485 if (!toCommit->squash[tid] || 486 inst->seqNum < toCommit->squashedSeqNum[tid]) { 487 toCommit->squash[tid] = true; 488 toCommit->squashedSeqNum[tid] = inst->seqNum; 489 toCommit->branchTaken[tid] = inst->pcState().branching(); 490 491 TheISA::PCState pc = inst->pcState(); 492 TheISA::advancePC(pc, inst->staticInst); 493 494 toCommit->pc[tid] = pc; 495 toCommit->mispredictInst[tid] = inst; 496 toCommit->includeSquashInst[tid] = false; 497 498 wroteToTimeBuffer = true; 499 } 500 501} 502 503template<class Impl> 504void 505DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 506{ 507 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 508 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 509 // Need to include inst->seqNum in the following comparison to cover the 510 // corner case when a branch misprediction and a memory violation for the 511 // same instruction (e.g. load PC) are detected in the same cycle. In this 512 // case the memory violator should take precedence over the branch 513 // misprediction because it requires the violator itself to be included in 514 // the squash. 515 if (!toCommit->squash[tid] || 516 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 517 toCommit->squash[tid] = true; 518 519 toCommit->squashedSeqNum[tid] = inst->seqNum; 520 toCommit->pc[tid] = inst->pcState(); 521 toCommit->mispredictInst[tid] = NULL; 522 523 // Must include the memory violator in the squash. 524 toCommit->includeSquashInst[tid] = true; 525 526 wroteToTimeBuffer = true; 527 } 528} 529 530template<class Impl> 531void 532DefaultIEW<Impl>::block(ThreadID tid) 533{ 534 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 535 536 if (dispatchStatus[tid] != Blocked && 537 dispatchStatus[tid] != Unblocking) { 538 toRename->iewBlock[tid] = true; 539 wroteToTimeBuffer = true; 540 } 541 542 // Add the current inputs to the skid buffer so they can be 543 // reprocessed when this stage unblocks. 544 skidInsert(tid); 545 546 dispatchStatus[tid] = Blocked; 547} 548 549template<class Impl> 550void 551DefaultIEW<Impl>::unblock(ThreadID tid) 552{ 553 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 554 "buffer %u.\n",tid, tid); 555 556 // If the skid bufffer is empty, signal back to previous stages to unblock. 557 // Also switch status to running. 558 if (skidBuffer[tid].empty()) { 559 toRename->iewUnblock[tid] = true; 560 wroteToTimeBuffer = true; 561 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 562 dispatchStatus[tid] = Running; 563 } 564} 565 566template<class Impl> 567void 568DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 569{ 570 instQueue.wakeDependents(inst); 571} 572 573template<class Impl> 574void 575DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 576{ 577 instQueue.rescheduleMemInst(inst); 578} 579 580template<class Impl> 581void 582DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 583{ 584 instQueue.replayMemInst(inst); 585} 586 587template<class Impl> 588void 589DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst) 590{ 591 instQueue.blockMemInst(inst); 592} 593 594template<class Impl> 595void 596DefaultIEW<Impl>::cacheUnblocked() 597{ 598 instQueue.cacheUnblocked(); 599} 600 601template<class Impl> 602void 603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 604{ 605 // This function should not be called after writebackInsts in a 606 // single cycle. That will cause problems with an instruction 607 // being added to the queue to commit without being processed by 608 // writebackInsts prior to being sent to commit. 609 610 // First check the time slot that this instruction will write 611 // to. If there are free write ports at the time, then go ahead 612 // and write the instruction to that time. If there are not, 613 // keep looking back to see where's the first time there's a 614 // free slot. 615 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 616 ++wbNumInst; 617 if (wbNumInst == wbWidth) { 618 ++wbCycle; 619 wbNumInst = 0; 620 } 621 } 622 623 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 624 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 625 // Add finished instruction to queue to commit. 626 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 627 (*iewQueue)[wbCycle].size++; 628} 629 630template <class Impl> 631unsigned 632DefaultIEW<Impl>::validInstsFromRename() 633{ 634 unsigned inst_count = 0; 635 636 for (int i=0; i<fromRename->size; i++) { 637 if (!fromRename->insts[i]->isSquashed()) 638 inst_count++; 639 } 640 641 return inst_count; 642} 643 644template<class Impl> 645void 646DefaultIEW<Impl>::skidInsert(ThreadID tid) 647{ 648 DynInstPtr inst = NULL; 649 650 while (!insts[tid].empty()) { 651 inst = insts[tid].front(); 652 653 insts[tid].pop(); 654 655 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 656 "dispatch skidBuffer %i\n",tid, inst->seqNum, 657 inst->pcState(),tid); 658 659 skidBuffer[tid].push(inst); 660 } 661 662 assert(skidBuffer[tid].size() <= skidBufferMax && 663 "Skidbuffer Exceeded Max Size"); 664} 665 666template<class Impl> 667int 668DefaultIEW<Impl>::skidCount() 669{ 670 int max=0; 671 672 list<ThreadID>::iterator threads = activeThreads->begin(); 673 list<ThreadID>::iterator end = activeThreads->end(); 674 675 while (threads != end) { 676 ThreadID tid = *threads++; 677 unsigned thread_count = skidBuffer[tid].size(); 678 if (max < thread_count) 679 max = thread_count; 680 } 681 682 return max; 683} 684 685template<class Impl> 686bool 687DefaultIEW<Impl>::skidsEmpty() 688{ 689 list<ThreadID>::iterator threads = activeThreads->begin(); 690 list<ThreadID>::iterator end = activeThreads->end(); 691 692 while (threads != end) { 693 ThreadID tid = *threads++; 694 695 if (!skidBuffer[tid].empty()) 696 return false; 697 } 698 699 return true; 700} 701 702template <class Impl> 703void 704DefaultIEW<Impl>::updateStatus() 705{ 706 bool any_unblocking = false; 707 708 list<ThreadID>::iterator threads = activeThreads->begin(); 709 list<ThreadID>::iterator end = activeThreads->end(); 710 711 while (threads != end) { 712 ThreadID tid = *threads++; 713 714 if (dispatchStatus[tid] == Unblocking) { 715 any_unblocking = true; 716 break; 717 } 718 } 719 720 // If there are no ready instructions waiting to be scheduled by the IQ, 721 // and there's no stores waiting to write back, and dispatch is not 722 // unblocking, then there is no internal activity for the IEW stage. 723 instQueue.intInstQueueReads++; 724 if (_status == Active && !instQueue.hasReadyInsts() && 725 !ldstQueue.willWB() && !any_unblocking) { 726 DPRINTF(IEW, "IEW switching to idle\n"); 727 728 deactivateStage(); 729 730 _status = Inactive; 731 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 732 ldstQueue.willWB() || 733 any_unblocking)) { 734 // Otherwise there is internal activity. Set to active. 735 DPRINTF(IEW, "IEW switching to active\n"); 736 737 activateStage(); 738 739 _status = Active; 740 } 741} 742 743template <class Impl> 744void 745DefaultIEW<Impl>::resetEntries() 746{ 747 instQueue.resetEntries(); 748 ldstQueue.resetEntries(); 749} 750 751template <class Impl> 752bool 753DefaultIEW<Impl>::checkStall(ThreadID tid) 754{ 755 bool ret_val(false); 756 757 if (fromCommit->commitInfo[tid].robSquashing) { 758 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 759 ret_val = true; 760 } else if (instQueue.isFull(tid)) { 761 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 762 ret_val = true; 763 } 764 765 return ret_val; 766} 767 768template <class Impl> 769void 770DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 771{ 772 // Check if there's a squash signal, squash if there is 773 // Check stall signals, block if there is. 774 // If status was Blocked 775 // if so then go to unblocking 776 // If status was Squashing 777 // check if squashing is not high. Switch to running this cycle. 778 779 if (fromCommit->commitInfo[tid].squash) { 780 squash(tid); 781 782 if (dispatchStatus[tid] == Blocked || 783 dispatchStatus[tid] == Unblocking) { 784 toRename->iewUnblock[tid] = true; 785 wroteToTimeBuffer = true; 786 } 787 788 dispatchStatus[tid] = Squashing; 789 fetchRedirect[tid] = false; 790 return; 791 } 792 793 if (fromCommit->commitInfo[tid].robSquashing) { 794 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 795 796 dispatchStatus[tid] = Squashing; 797 emptyRenameInsts(tid); 798 wroteToTimeBuffer = true; 799 } 800 801 if (checkStall(tid)) { 802 block(tid); 803 dispatchStatus[tid] = Blocked; 804 return; 805 } 806 807 if (dispatchStatus[tid] == Blocked) { 808 // Status from previous cycle was blocked, but there are no more stall 809 // conditions. Switch over to unblocking. 810 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 811 tid); 812 813 dispatchStatus[tid] = Unblocking; 814 815 unblock(tid); 816 817 return; 818 } 819 820 if (dispatchStatus[tid] == Squashing) { 821 // Switch status to running if rename isn't being told to block or 822 // squash this cycle. 823 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 824 tid); 825 826 dispatchStatus[tid] = Running; 827 828 return; 829 } 830} 831 832template <class Impl> 833void 834DefaultIEW<Impl>::sortInsts() 835{ 836 int insts_from_rename = fromRename->size; 837#ifdef DEBUG 838 for (ThreadID tid = 0; tid < numThreads; tid++) 839 assert(insts[tid].empty()); 840#endif 841 for (int i = 0; i < insts_from_rename; ++i) { 842 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 843 } 844} 845 846template <class Impl> 847void 848DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 849{ 850 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 851 852 while (!insts[tid].empty()) { 853 854 if (insts[tid].front()->isLoad()) { 855 toRename->iewInfo[tid].dispatchedToLQ++; 856 } 857 if (insts[tid].front()->isStore()) { 858 toRename->iewInfo[tid].dispatchedToSQ++; 859 } 860 861 toRename->iewInfo[tid].dispatched++; 862 863 insts[tid].pop(); 864 } 865} 866 867template <class Impl> 868void 869DefaultIEW<Impl>::wakeCPU() 870{ 871 cpu->wakeCPU(); 872} 873 874template <class Impl> 875void 876DefaultIEW<Impl>::activityThisCycle() 877{ 878 DPRINTF(Activity, "Activity this cycle.\n"); 879 cpu->activityThisCycle(); 880} 881 882template <class Impl> 883inline void 884DefaultIEW<Impl>::activateStage() 885{ 886 DPRINTF(Activity, "Activating stage.\n"); 887 cpu->activateStage(O3CPU::IEWIdx); 888} 889 890template <class Impl> 891inline void 892DefaultIEW<Impl>::deactivateStage() 893{ 894 DPRINTF(Activity, "Deactivating stage.\n"); 895 cpu->deactivateStage(O3CPU::IEWIdx); 896} 897 898template<class Impl> 899void 900DefaultIEW<Impl>::dispatch(ThreadID tid) 901{ 902 // If status is Running or idle, 903 // call dispatchInsts() 904 // If status is Unblocking, 905 // buffer any instructions coming from rename 906 // continue trying to empty skid buffer 907 // check if stall conditions have passed 908 909 if (dispatchStatus[tid] == Blocked) { 910 ++iewBlockCycles; 911 912 } else if (dispatchStatus[tid] == Squashing) { 913 ++iewSquashCycles; 914 } 915 916 // Dispatch should try to dispatch as many instructions as its bandwidth 917 // will allow, as long as it is not currently blocked. 918 if (dispatchStatus[tid] == Running || 919 dispatchStatus[tid] == Idle) { 920 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 921 "dispatch.\n", tid); 922 923 dispatchInsts(tid); 924 } else if (dispatchStatus[tid] == Unblocking) { 925 // Make sure that the skid buffer has something in it if the 926 // status is unblocking. 927 assert(!skidsEmpty()); 928 929 // If the status was unblocking, then instructions from the skid 930 // buffer were used. Remove those instructions and handle 931 // the rest of unblocking. 932 dispatchInsts(tid); 933 934 ++iewUnblockCycles; 935 936 if (validInstsFromRename()) { 937 // Add the current inputs to the skid buffer so they can be 938 // reprocessed when this stage unblocks. 939 skidInsert(tid); 940 } 941 942 unblock(tid); 943 } 944} 945 946template <class Impl> 947void 948DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 949{ 950 // Obtain instructions from skid buffer if unblocking, or queue from rename 951 // otherwise. 952 std::queue<DynInstPtr> &insts_to_dispatch = 953 dispatchStatus[tid] == Unblocking ? 954 skidBuffer[tid] : insts[tid]; 955 956 int insts_to_add = insts_to_dispatch.size(); 957 958 DynInstPtr inst; 959 bool add_to_iq = false; 960 int dis_num_inst = 0; 961 962 // Loop through the instructions, putting them in the instruction 963 // queue. 964 for ( ; dis_num_inst < insts_to_add && 965 dis_num_inst < dispatchWidth; 966 ++dis_num_inst) 967 { 968 inst = insts_to_dispatch.front(); 969 970 if (dispatchStatus[tid] == Unblocking) { 971 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 972 "buffer\n", tid); 973 } 974 975 // Make sure there's a valid instruction there. 976 assert(inst); 977 978 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 979 "IQ.\n", 980 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 981 982 // Be sure to mark these instructions as ready so that the 983 // commit stage can go ahead and execute them, and mark 984 // them as issued so the IQ doesn't reprocess them. 985 986 // Check for squashed instructions. 987 if (inst->isSquashed()) { 988 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 989 "not adding to IQ.\n", tid); 990 991 ++iewDispSquashedInsts; 992 993 insts_to_dispatch.pop(); 994 995 //Tell Rename That An Instruction has been processed 996 if (inst->isLoad()) { 997 toRename->iewInfo[tid].dispatchedToLQ++; 998 } 999 if (inst->isStore()) { 1000 toRename->iewInfo[tid].dispatchedToSQ++; 1001 } 1002 1003 toRename->iewInfo[tid].dispatched++; 1004 1005 continue; 1006 } 1007 1008 // Check for full conditions. 1009 if (instQueue.isFull(tid)) { 1010 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1011 1012 // Call function to start blocking. 1013 block(tid); 1014 1015 // Set unblock to false. Special case where we are using 1016 // skidbuffer (unblocking) instructions but then we still 1017 // get full in the IQ. 1018 toRename->iewUnblock[tid] = false; 1019 1020 ++iewIQFullEvents; 1021 break; 1022 } 1023 1024 // Check LSQ if inst is LD/ST 1025 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1026 (inst->isStore() && ldstQueue.sqFull(tid))) { 1027 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1028 inst->isLoad() ? "LQ" : "SQ"); 1029 1030 // Call function to start blocking. 1031 block(tid); 1032 1033 // Set unblock to false. Special case where we are using 1034 // skidbuffer (unblocking) instructions but then we still 1035 // get full in the IQ. 1036 toRename->iewUnblock[tid] = false; 1037 1038 ++iewLSQFullEvents; 1039 break; 1040 } 1041 1042 // Otherwise issue the instruction just fine. 1043 if (inst->isLoad()) { 1044 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1045 "encountered, adding to LSQ.\n", tid); 1046 1047 // Reserve a spot in the load store queue for this 1048 // memory access. 1049 ldstQueue.insertLoad(inst); 1050 1051 ++iewDispLoadInsts; 1052 1053 add_to_iq = true; 1054 1055 toRename->iewInfo[tid].dispatchedToLQ++; 1056 } else if (inst->isStore()) { 1057 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1058 "encountered, adding to LSQ.\n", tid); 1059 1060 ldstQueue.insertStore(inst); 1061 1062 ++iewDispStoreInsts; 1063 1064 if (inst->isStoreConditional()) { 1065 // Store conditionals need to be set as "canCommit()" 1066 // so that commit can process them when they reach the 1067 // head of commit. 1068 // @todo: This is somewhat specific to Alpha. 1069 inst->setCanCommit(); 1070 instQueue.insertNonSpec(inst); 1071 add_to_iq = false; 1072 1073 ++iewDispNonSpecInsts; 1074 } else { 1075 add_to_iq = true; 1076 } 1077 1078 toRename->iewInfo[tid].dispatchedToSQ++; 1079 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1080 // Same as non-speculative stores. 1081 inst->setCanCommit(); 1082 instQueue.insertBarrier(inst); 1083 add_to_iq = false; 1084 } else if (inst->isNop()) { 1085 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1086 "skipping.\n", tid); 1087 1088 inst->setIssued(); 1089 inst->setExecuted(); 1090 inst->setCanCommit(); 1091 1092 instQueue.recordProducer(inst); 1093 1094 iewExecutedNop[tid]++; 1095 1096 add_to_iq = false; 1097 } else { 1098 assert(!inst->isExecuted()); 1099 add_to_iq = true; 1100 } 1101 1102 if (inst->isNonSpeculative()) { 1103 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1104 "encountered, skipping.\n", tid); 1105 1106 // Same as non-speculative stores. 1107 inst->setCanCommit(); 1108 1109 // Specifically insert it as nonspeculative. 1110 instQueue.insertNonSpec(inst); 1111 1112 ++iewDispNonSpecInsts; 1113 1114 add_to_iq = false; 1115 } 1116 1117 // If the instruction queue is not full, then add the 1118 // instruction. 1119 if (add_to_iq) { 1120 instQueue.insert(inst); 1121 } 1122 1123 insts_to_dispatch.pop(); 1124 1125 toRename->iewInfo[tid].dispatched++; 1126 1127 ++iewDispatchedInsts; 1128 1129#if TRACING_ON 1130 inst->dispatchTick = curTick() - inst->fetchTick; 1131#endif 1132 ppDispatch->notify(inst); 1133 } 1134 1135 if (!insts_to_dispatch.empty()) { 1136 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1137 block(tid); 1138 toRename->iewUnblock[tid] = false; 1139 } 1140 1141 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1142 dispatchStatus[tid] = Running; 1143 1144 updatedQueues = true; 1145 } 1146 1147 dis_num_inst = 0; 1148} 1149 1150template <class Impl> 1151void 1152DefaultIEW<Impl>::printAvailableInsts() 1153{ 1154 int inst = 0; 1155 1156 std::cout << "Available Instructions: "; 1157 1158 while (fromIssue->insts[inst]) { 1159 1160 if (inst%3==0) std::cout << "\n\t"; 1161 1162 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1163 << " TN: " << fromIssue->insts[inst]->threadNumber 1164 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1165 1166 inst++; 1167 1168 } 1169 1170 std::cout << "\n"; 1171} 1172 1173template <class Impl> 1174void 1175DefaultIEW<Impl>::executeInsts() 1176{ 1177 wbNumInst = 0; 1178 wbCycle = 0; 1179 1180 list<ThreadID>::iterator threads = activeThreads->begin(); 1181 list<ThreadID>::iterator end = activeThreads->end(); 1182 1183 while (threads != end) { 1184 ThreadID tid = *threads++; 1185 fetchRedirect[tid] = false; 1186 } 1187 1188 // Uncomment this if you want to see all available instructions. 1189 // @todo This doesn't actually work anymore, we should fix it. 1190// printAvailableInsts(); 1191 1192 // Execute/writeback any instructions that are available. 1193 int insts_to_execute = fromIssue->size; 1194 int inst_num = 0; 1195 for (; inst_num < insts_to_execute; 1196 ++inst_num) { 1197 1198 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1199 1200 DynInstPtr inst = instQueue.getInstToExecute(); 1201 1202 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1203 inst->pcState(), inst->threadNumber,inst->seqNum); 1204 1205 // Notify potential listeners that this instruction has started 1206 // executing 1207 ppExecute->notify(inst); 1208 1209 // Check if the instruction is squashed; if so then skip it 1210 if (inst->isSquashed()) { 1211 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1212 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1213 inst->seqNum); 1214 1215 // Consider this instruction executed so that commit can go 1216 // ahead and retire the instruction. 1217 inst->setExecuted(); 1218 1219 // Not sure if I should set this here or just let commit try to 1220 // commit any squashed instructions. I like the latter a bit more. 1221 inst->setCanCommit(); 1222 1223 ++iewExecSquashedInsts; 1224 1225 continue; 1226 } 1227 1228 Fault fault = NoFault; 1229 1230 // Execute instruction. 1231 // Note that if the instruction faults, it will be handled 1232 // at the commit stage. 1233 if (inst->isMemRef()) { 1234 DPRINTF(IEW, "Execute: Calculating address for memory " 1235 "reference.\n"); 1236 1237 // Tell the LDSTQ to execute this instruction (if it is a load). 1238 if (inst->isLoad()) { 1239 // Loads will mark themselves as executed, and their writeback 1240 // event adds the instruction to the queue to commit 1241 fault = ldstQueue.executeLoad(inst); 1242 1243 if (inst->isTranslationDelayed() && 1244 fault == NoFault) { 1245 // A hw page table walk is currently going on; the 1246 // instruction must be deferred. 1247 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1248 "load.\n"); 1249 instQueue.deferMemInst(inst); 1250 continue; 1251 } 1252 1253 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1254 inst->fault = NoFault; 1255 } 1256 } else if (inst->isStore()) { 1257 fault = ldstQueue.executeStore(inst); 1258 1259 if (inst->isTranslationDelayed() && 1260 fault == NoFault) { 1261 // A hw page table walk is currently going on; the 1262 // instruction must be deferred. 1263 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1264 "store.\n"); 1265 instQueue.deferMemInst(inst); 1266 continue; 1267 } 1268 1269 // If the store had a fault then it may not have a mem req 1270 if (fault != NoFault || !inst->readPredicate() || 1271 !inst->isStoreConditional()) { 1272 // If the instruction faulted, then we need to send it along 1273 // to commit without the instruction completing. 1274 // Send this instruction to commit, also make sure iew stage 1275 // realizes there is activity. 1276 inst->setExecuted(); 1277 instToCommit(inst); 1278 activityThisCycle(); 1279 } 1280 1281 // Store conditionals will mark themselves as 1282 // executed, and their writeback event will add the 1283 // instruction to the queue to commit. 1284 } else { 1285 panic("Unexpected memory type!\n"); 1286 } 1287 1288 } else { 1289 // If the instruction has already faulted, then skip executing it. 1290 // Such case can happen when it faulted during ITLB translation. 1291 // If we execute the instruction (even if it's a nop) the fault 1292 // will be replaced and we will lose it. 1293 if (inst->getFault() == NoFault) { 1294 inst->execute(); 1295 if (!inst->readPredicate()) 1296 inst->forwardOldRegs(); 1297 } 1298 1299 inst->setExecuted(); 1300 1301 instToCommit(inst); 1302 } 1303 1304 updateExeInstStats(inst); 1305 1306 // Check if branch prediction was correct, if not then we need 1307 // to tell commit to squash in flight instructions. Only 1308 // handle this if there hasn't already been something that 1309 // redirects fetch in this group of instructions. 1310 1311 // This probably needs to prioritize the redirects if a different 1312 // scheduler is used. Currently the scheduler schedules the oldest 1313 // instruction first, so the branch resolution order will be correct. 1314 ThreadID tid = inst->threadNumber; 1315 1316 if (!fetchRedirect[tid] || 1317 !toCommit->squash[tid] || 1318 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1319 1320 // Prevent testing for misprediction on load instructions, 1321 // that have not been executed. 1322 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1323 1324 if (inst->mispredicted() && !loadNotExecuted) { 1325 fetchRedirect[tid] = true; 1326 1327 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1328 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1329 inst->readPredTarg()); 1330 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1331 inst->pcState()); 1332 // If incorrect, then signal the ROB that it must be squashed. 1333 squashDueToBranch(inst, tid); 1334 1335 ppMispredict->notify(inst); 1336 1337 if (inst->readPredTaken()) { 1338 predictedTakenIncorrect++; 1339 } else { 1340 predictedNotTakenIncorrect++; 1341 } 1342 } else if (ldstQueue.violation(tid)) { 1343 assert(inst->isMemRef()); 1344 // If there was an ordering violation, then get the 1345 // DynInst that caused the violation. Note that this 1346 // clears the violation signal. 1347 DynInstPtr violator; 1348 violator = ldstQueue.getMemDepViolator(tid); 1349 1350 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1351 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1352 violator->pcState(), violator->seqNum, 1353 inst->pcState(), inst->seqNum, inst->physEffAddrLow); 1354 1355 fetchRedirect[tid] = true; 1356 1357 // Tell the instruction queue that a violation has occured. 1358 instQueue.violation(inst, violator); 1359 1360 // Squash. 1361 squashDueToMemOrder(violator, tid); 1362 1363 ++memOrderViolationEvents; 1364 } 1365 } else { 1366 // Reset any state associated with redirects that will not 1367 // be used. 1368 if (ldstQueue.violation(tid)) { 1369 assert(inst->isMemRef()); 1370 1371 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1372 1373 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1374 "%s, inst PC: %s. Addr is: %#x.\n", 1375 violator->pcState(), inst->pcState(), 1376 inst->physEffAddrLow); 1377 DPRINTF(IEW, "Violation will not be handled because " 1378 "already squashing\n"); 1379 1380 ++memOrderViolationEvents; 1381 } 1382 } 1383 } 1384 1385 // Update and record activity if we processed any instructions. 1386 if (inst_num) { 1387 if (exeStatus == Idle) { 1388 exeStatus = Running; 1389 } 1390 1391 updatedQueues = true; 1392 1393 cpu->activityThisCycle(); 1394 } 1395 1396 // Need to reset this in case a writeback event needs to write into the 1397 // iew queue. That way the writeback event will write into the correct 1398 // spot in the queue. 1399 wbNumInst = 0; 1400 1401} 1402 1403template <class Impl> 1404void 1405DefaultIEW<Impl>::writebackInsts() 1406{ 1407 // Loop through the head of the time buffer and wake any 1408 // dependents. These instructions are about to write back. Also 1409 // mark scoreboard that this instruction is finally complete. 1410 // Either have IEW have direct access to scoreboard, or have this 1411 // as part of backwards communication. 1412 for (int inst_num = 0; inst_num < wbWidth && 1413 toCommit->insts[inst_num]; inst_num++) { 1414 DynInstPtr inst = toCommit->insts[inst_num]; 1415 ThreadID tid = inst->threadNumber; 1416 1417 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1418 inst->seqNum, inst->pcState()); 1419 1420 iewInstsToCommit[tid]++; 1421 // Notify potential listeners that execution is complete for this 1422 // instruction. 1423 ppToCommit->notify(inst); 1424 1425 // Some instructions will be sent to commit without having 1426 // executed because they need commit to handle them. 1427 // E.g. Strictly ordered loads have not actually executed when they 1428 // are first sent to commit. Instead commit must tell the LSQ 1429 // when it's ready to execute the strictly ordered load. 1430 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1431 int dependents = instQueue.wakeDependents(inst); 1432 1433 for (int i = 0; i < inst->numDestRegs(); i++) { 1434 //mark as Ready 1435 DPRINTF(IEW,"Setting Destination Register %i\n", 1436 inst->renamedDestRegIdx(i)); 1437 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1438 } 1439 1440 if (dependents) { 1441 producerInst[tid]++; 1442 consumerInst[tid]+= dependents; 1443 } 1444 writebackCount[tid]++; 1445 } 1446 } 1447} 1448 1449template<class Impl> 1450void 1451DefaultIEW<Impl>::tick() 1452{ 1453 wbNumInst = 0; 1454 wbCycle = 0; 1455 1456 wroteToTimeBuffer = false; 1457 updatedQueues = false; 1458 1459 sortInsts(); 1460 1461 // Free function units marked as being freed this cycle. 1462 fuPool->processFreeUnits(); 1463 1464 list<ThreadID>::iterator threads = activeThreads->begin(); 1465 list<ThreadID>::iterator end = activeThreads->end(); 1466 1467 // Check stall and squash signals, dispatch any instructions. 1468 while (threads != end) { 1469 ThreadID tid = *threads++; 1470 1471 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1472 1473 checkSignalsAndUpdate(tid); 1474 dispatch(tid); 1475 } 1476 1477 if (exeStatus != Squashing) { 1478 executeInsts(); 1479 1480 writebackInsts(); 1481 1482 // Have the instruction queue try to schedule any ready instructions. 1483 // (In actuality, this scheduling is for instructions that will 1484 // be executed next cycle.) 1485 instQueue.scheduleReadyInsts(); 1486 1487 // Also should advance its own time buffers if the stage ran. 1488 // Not the best place for it, but this works (hopefully). 1489 issueToExecQueue.advance(); 1490 } 1491 1492 bool broadcast_free_entries = false; 1493 1494 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1495 exeStatus = Idle; 1496 updateLSQNextCycle = false; 1497 1498 broadcast_free_entries = true; 1499 } 1500 1501 // Writeback any stores using any leftover bandwidth. 1502 ldstQueue.writebackStores(); 1503 1504 // Check the committed load/store signals to see if there's a load 1505 // or store to commit. Also check if it's being told to execute a 1506 // nonspeculative instruction. 1507 // This is pretty inefficient... 1508 1509 threads = activeThreads->begin(); 1510 while (threads != end) { 1511 ThreadID tid = (*threads++); 1512 1513 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1514 1515 // Update structures based on instructions committed. 1516 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1517 !fromCommit->commitInfo[tid].squash && 1518 !fromCommit->commitInfo[tid].robSquashing) { 1519 1520 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1521 1522 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1523 1524 updateLSQNextCycle = true; 1525 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1526 } 1527 1528 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1529 1530 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1531 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1532 instQueue.replayMemInst( 1533 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1534 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1535 } else { 1536 instQueue.scheduleNonSpec( 1537 fromCommit->commitInfo[tid].nonSpecSeqNum); 1538 } 1539 } 1540 1541 if (broadcast_free_entries) { 1542 toFetch->iewInfo[tid].iqCount = 1543 instQueue.getCount(tid); 1544 toFetch->iewInfo[tid].ldstqCount = 1545 ldstQueue.getCount(tid); 1546 1547 toRename->iewInfo[tid].usedIQ = true; 1548 toRename->iewInfo[tid].freeIQEntries = 1549 instQueue.numFreeEntries(tid); 1550 toRename->iewInfo[tid].usedLSQ = true; 1551 1552 toRename->iewInfo[tid].freeLQEntries = 1553 ldstQueue.numFreeLoadEntries(tid); 1554 toRename->iewInfo[tid].freeSQEntries = 1555 ldstQueue.numFreeStoreEntries(tid); 1556 1557 wroteToTimeBuffer = true; 1558 } 1559 1560 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1561 tid, toRename->iewInfo[tid].dispatched); 1562 } 1563 1564 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1565 "LQ has %i free entries. SQ has %i free entries.\n", 1566 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1567 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1568 1569 updateStatus(); 1570 1571 if (wroteToTimeBuffer) { 1572 DPRINTF(Activity, "Activity this cycle.\n"); 1573 cpu->activityThisCycle(); 1574 } 1575} 1576 1577template <class Impl> 1578void 1579DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1580{ 1581 ThreadID tid = inst->threadNumber; 1582 1583 iewExecutedInsts++; 1584 1585#if TRACING_ON 1586 if (DTRACE(O3PipeView)) { 1587 inst->completeTick = curTick() - inst->fetchTick; 1588 } 1589#endif 1590 1591 // 1592 // Control operations 1593 // 1594 if (inst->isControl()) 1595 iewExecutedBranches[tid]++; 1596 1597 // 1598 // Memory operations 1599 // 1600 if (inst->isMemRef()) { 1601 iewExecutedRefs[tid]++; 1602 1603 if (inst->isLoad()) { 1604 iewExecLoadInsts[tid]++; 1605 } 1606 } 1607} 1608 1609template <class Impl> 1610void 1611DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1612{ 1613 ThreadID tid = inst->threadNumber; 1614 1615 if (!fetchRedirect[tid] || 1616 !toCommit->squash[tid] || 1617 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1618 1619 if (inst->mispredicted()) { 1620 fetchRedirect[tid] = true; 1621 1622 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1623 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1624 inst->predInstAddr(), inst->predNextInstAddr()); 1625 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1626 " NPC: %#x.\n", inst->nextInstAddr(), 1627 inst->nextInstAddr()); 1628 // If incorrect, then signal the ROB that it must be squashed. 1629 squashDueToBranch(inst, tid); 1630 1631 if (inst->readPredTaken()) { 1632 predictedTakenIncorrect++; 1633 } else { 1634 predictedNotTakenIncorrect++; 1635 } 1636 } 1637 } 1638} 1639 1640#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
| 395 } 396 397 // Also check the FU pool as instructions are "stored" in FU 398 // completion events until they are done and not accounted for 399 // above 400 if (drained && !fuPool->isDrained()) { 401 DPRINTF(Drain, "FU pool still busy.\n"); 402 drained = false; 403 } 404 405 return drained; 406} 407 408template <class Impl> 409void 410DefaultIEW<Impl>::drainSanityCheck() const 411{ 412 assert(isDrained()); 413 414 instQueue.drainSanityCheck(); 415 ldstQueue.drainSanityCheck(); 416} 417 418template <class Impl> 419void 420DefaultIEW<Impl>::takeOverFrom() 421{ 422 // Reset all state. 423 _status = Active; 424 exeStatus = Running; 425 wbStatus = Idle; 426 427 instQueue.takeOverFrom(); 428 ldstQueue.takeOverFrom(); 429 fuPool->takeOverFrom(); 430 431 startupStage(); 432 cpu->activityThisCycle(); 433 434 for (ThreadID tid = 0; tid < numThreads; tid++) { 435 dispatchStatus[tid] = Running; 436 fetchRedirect[tid] = false; 437 } 438 439 updateLSQNextCycle = false; 440 441 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 442 issueToExecQueue.advance(); 443 } 444} 445 446template<class Impl> 447void 448DefaultIEW<Impl>::squash(ThreadID tid) 449{ 450 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 451 452 // Tell the IQ to start squashing. 453 instQueue.squash(tid); 454 455 // Tell the LDSTQ to start squashing. 456 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 457 updatedQueues = true; 458 459 // Clear the skid buffer in case it has any data in it. 460 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 461 tid, fromCommit->commitInfo[tid].doneSeqNum); 462 463 while (!skidBuffer[tid].empty()) { 464 if (skidBuffer[tid].front()->isLoad()) { 465 toRename->iewInfo[tid].dispatchedToLQ++; 466 } 467 if (skidBuffer[tid].front()->isStore()) { 468 toRename->iewInfo[tid].dispatchedToSQ++; 469 } 470 471 toRename->iewInfo[tid].dispatched++; 472 473 skidBuffer[tid].pop(); 474 } 475 476 emptyRenameInsts(tid); 477} 478 479template<class Impl> 480void 481DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 482{ 483 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 484 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 485 486 if (!toCommit->squash[tid] || 487 inst->seqNum < toCommit->squashedSeqNum[tid]) { 488 toCommit->squash[tid] = true; 489 toCommit->squashedSeqNum[tid] = inst->seqNum; 490 toCommit->branchTaken[tid] = inst->pcState().branching(); 491 492 TheISA::PCState pc = inst->pcState(); 493 TheISA::advancePC(pc, inst->staticInst); 494 495 toCommit->pc[tid] = pc; 496 toCommit->mispredictInst[tid] = inst; 497 toCommit->includeSquashInst[tid] = false; 498 499 wroteToTimeBuffer = true; 500 } 501 502} 503 504template<class Impl> 505void 506DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 507{ 508 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 509 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 510 // Need to include inst->seqNum in the following comparison to cover the 511 // corner case when a branch misprediction and a memory violation for the 512 // same instruction (e.g. load PC) are detected in the same cycle. In this 513 // case the memory violator should take precedence over the branch 514 // misprediction because it requires the violator itself to be included in 515 // the squash. 516 if (!toCommit->squash[tid] || 517 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 518 toCommit->squash[tid] = true; 519 520 toCommit->squashedSeqNum[tid] = inst->seqNum; 521 toCommit->pc[tid] = inst->pcState(); 522 toCommit->mispredictInst[tid] = NULL; 523 524 // Must include the memory violator in the squash. 525 toCommit->includeSquashInst[tid] = true; 526 527 wroteToTimeBuffer = true; 528 } 529} 530 531template<class Impl> 532void 533DefaultIEW<Impl>::block(ThreadID tid) 534{ 535 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 536 537 if (dispatchStatus[tid] != Blocked && 538 dispatchStatus[tid] != Unblocking) { 539 toRename->iewBlock[tid] = true; 540 wroteToTimeBuffer = true; 541 } 542 543 // Add the current inputs to the skid buffer so they can be 544 // reprocessed when this stage unblocks. 545 skidInsert(tid); 546 547 dispatchStatus[tid] = Blocked; 548} 549 550template<class Impl> 551void 552DefaultIEW<Impl>::unblock(ThreadID tid) 553{ 554 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 555 "buffer %u.\n",tid, tid); 556 557 // If the skid bufffer is empty, signal back to previous stages to unblock. 558 // Also switch status to running. 559 if (skidBuffer[tid].empty()) { 560 toRename->iewUnblock[tid] = true; 561 wroteToTimeBuffer = true; 562 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 563 dispatchStatus[tid] = Running; 564 } 565} 566 567template<class Impl> 568void 569DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 570{ 571 instQueue.wakeDependents(inst); 572} 573 574template<class Impl> 575void 576DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 577{ 578 instQueue.rescheduleMemInst(inst); 579} 580 581template<class Impl> 582void 583DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 584{ 585 instQueue.replayMemInst(inst); 586} 587 588template<class Impl> 589void 590DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst) 591{ 592 instQueue.blockMemInst(inst); 593} 594 595template<class Impl> 596void 597DefaultIEW<Impl>::cacheUnblocked() 598{ 599 instQueue.cacheUnblocked(); 600} 601 602template<class Impl> 603void 604DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 605{ 606 // This function should not be called after writebackInsts in a 607 // single cycle. That will cause problems with an instruction 608 // being added to the queue to commit without being processed by 609 // writebackInsts prior to being sent to commit. 610 611 // First check the time slot that this instruction will write 612 // to. If there are free write ports at the time, then go ahead 613 // and write the instruction to that time. If there are not, 614 // keep looking back to see where's the first time there's a 615 // free slot. 616 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 617 ++wbNumInst; 618 if (wbNumInst == wbWidth) { 619 ++wbCycle; 620 wbNumInst = 0; 621 } 622 } 623 624 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 625 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 626 // Add finished instruction to queue to commit. 627 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 628 (*iewQueue)[wbCycle].size++; 629} 630 631template <class Impl> 632unsigned 633DefaultIEW<Impl>::validInstsFromRename() 634{ 635 unsigned inst_count = 0; 636 637 for (int i=0; i<fromRename->size; i++) { 638 if (!fromRename->insts[i]->isSquashed()) 639 inst_count++; 640 } 641 642 return inst_count; 643} 644 645template<class Impl> 646void 647DefaultIEW<Impl>::skidInsert(ThreadID tid) 648{ 649 DynInstPtr inst = NULL; 650 651 while (!insts[tid].empty()) { 652 inst = insts[tid].front(); 653 654 insts[tid].pop(); 655 656 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 657 "dispatch skidBuffer %i\n",tid, inst->seqNum, 658 inst->pcState(),tid); 659 660 skidBuffer[tid].push(inst); 661 } 662 663 assert(skidBuffer[tid].size() <= skidBufferMax && 664 "Skidbuffer Exceeded Max Size"); 665} 666 667template<class Impl> 668int 669DefaultIEW<Impl>::skidCount() 670{ 671 int max=0; 672 673 list<ThreadID>::iterator threads = activeThreads->begin(); 674 list<ThreadID>::iterator end = activeThreads->end(); 675 676 while (threads != end) { 677 ThreadID tid = *threads++; 678 unsigned thread_count = skidBuffer[tid].size(); 679 if (max < thread_count) 680 max = thread_count; 681 } 682 683 return max; 684} 685 686template<class Impl> 687bool 688DefaultIEW<Impl>::skidsEmpty() 689{ 690 list<ThreadID>::iterator threads = activeThreads->begin(); 691 list<ThreadID>::iterator end = activeThreads->end(); 692 693 while (threads != end) { 694 ThreadID tid = *threads++; 695 696 if (!skidBuffer[tid].empty()) 697 return false; 698 } 699 700 return true; 701} 702 703template <class Impl> 704void 705DefaultIEW<Impl>::updateStatus() 706{ 707 bool any_unblocking = false; 708 709 list<ThreadID>::iterator threads = activeThreads->begin(); 710 list<ThreadID>::iterator end = activeThreads->end(); 711 712 while (threads != end) { 713 ThreadID tid = *threads++; 714 715 if (dispatchStatus[tid] == Unblocking) { 716 any_unblocking = true; 717 break; 718 } 719 } 720 721 // If there are no ready instructions waiting to be scheduled by the IQ, 722 // and there's no stores waiting to write back, and dispatch is not 723 // unblocking, then there is no internal activity for the IEW stage. 724 instQueue.intInstQueueReads++; 725 if (_status == Active && !instQueue.hasReadyInsts() && 726 !ldstQueue.willWB() && !any_unblocking) { 727 DPRINTF(IEW, "IEW switching to idle\n"); 728 729 deactivateStage(); 730 731 _status = Inactive; 732 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 733 ldstQueue.willWB() || 734 any_unblocking)) { 735 // Otherwise there is internal activity. Set to active. 736 DPRINTF(IEW, "IEW switching to active\n"); 737 738 activateStage(); 739 740 _status = Active; 741 } 742} 743 744template <class Impl> 745void 746DefaultIEW<Impl>::resetEntries() 747{ 748 instQueue.resetEntries(); 749 ldstQueue.resetEntries(); 750} 751 752template <class Impl> 753bool 754DefaultIEW<Impl>::checkStall(ThreadID tid) 755{ 756 bool ret_val(false); 757 758 if (fromCommit->commitInfo[tid].robSquashing) { 759 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 760 ret_val = true; 761 } else if (instQueue.isFull(tid)) { 762 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 763 ret_val = true; 764 } 765 766 return ret_val; 767} 768 769template <class Impl> 770void 771DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 772{ 773 // Check if there's a squash signal, squash if there is 774 // Check stall signals, block if there is. 775 // If status was Blocked 776 // if so then go to unblocking 777 // If status was Squashing 778 // check if squashing is not high. Switch to running this cycle. 779 780 if (fromCommit->commitInfo[tid].squash) { 781 squash(tid); 782 783 if (dispatchStatus[tid] == Blocked || 784 dispatchStatus[tid] == Unblocking) { 785 toRename->iewUnblock[tid] = true; 786 wroteToTimeBuffer = true; 787 } 788 789 dispatchStatus[tid] = Squashing; 790 fetchRedirect[tid] = false; 791 return; 792 } 793 794 if (fromCommit->commitInfo[tid].robSquashing) { 795 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 796 797 dispatchStatus[tid] = Squashing; 798 emptyRenameInsts(tid); 799 wroteToTimeBuffer = true; 800 } 801 802 if (checkStall(tid)) { 803 block(tid); 804 dispatchStatus[tid] = Blocked; 805 return; 806 } 807 808 if (dispatchStatus[tid] == Blocked) { 809 // Status from previous cycle was blocked, but there are no more stall 810 // conditions. Switch over to unblocking. 811 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 812 tid); 813 814 dispatchStatus[tid] = Unblocking; 815 816 unblock(tid); 817 818 return; 819 } 820 821 if (dispatchStatus[tid] == Squashing) { 822 // Switch status to running if rename isn't being told to block or 823 // squash this cycle. 824 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 825 tid); 826 827 dispatchStatus[tid] = Running; 828 829 return; 830 } 831} 832 833template <class Impl> 834void 835DefaultIEW<Impl>::sortInsts() 836{ 837 int insts_from_rename = fromRename->size; 838#ifdef DEBUG 839 for (ThreadID tid = 0; tid < numThreads; tid++) 840 assert(insts[tid].empty()); 841#endif 842 for (int i = 0; i < insts_from_rename; ++i) { 843 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 844 } 845} 846 847template <class Impl> 848void 849DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 850{ 851 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 852 853 while (!insts[tid].empty()) { 854 855 if (insts[tid].front()->isLoad()) { 856 toRename->iewInfo[tid].dispatchedToLQ++; 857 } 858 if (insts[tid].front()->isStore()) { 859 toRename->iewInfo[tid].dispatchedToSQ++; 860 } 861 862 toRename->iewInfo[tid].dispatched++; 863 864 insts[tid].pop(); 865 } 866} 867 868template <class Impl> 869void 870DefaultIEW<Impl>::wakeCPU() 871{ 872 cpu->wakeCPU(); 873} 874 875template <class Impl> 876void 877DefaultIEW<Impl>::activityThisCycle() 878{ 879 DPRINTF(Activity, "Activity this cycle.\n"); 880 cpu->activityThisCycle(); 881} 882 883template <class Impl> 884inline void 885DefaultIEW<Impl>::activateStage() 886{ 887 DPRINTF(Activity, "Activating stage.\n"); 888 cpu->activateStage(O3CPU::IEWIdx); 889} 890 891template <class Impl> 892inline void 893DefaultIEW<Impl>::deactivateStage() 894{ 895 DPRINTF(Activity, "Deactivating stage.\n"); 896 cpu->deactivateStage(O3CPU::IEWIdx); 897} 898 899template<class Impl> 900void 901DefaultIEW<Impl>::dispatch(ThreadID tid) 902{ 903 // If status is Running or idle, 904 // call dispatchInsts() 905 // If status is Unblocking, 906 // buffer any instructions coming from rename 907 // continue trying to empty skid buffer 908 // check if stall conditions have passed 909 910 if (dispatchStatus[tid] == Blocked) { 911 ++iewBlockCycles; 912 913 } else if (dispatchStatus[tid] == Squashing) { 914 ++iewSquashCycles; 915 } 916 917 // Dispatch should try to dispatch as many instructions as its bandwidth 918 // will allow, as long as it is not currently blocked. 919 if (dispatchStatus[tid] == Running || 920 dispatchStatus[tid] == Idle) { 921 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 922 "dispatch.\n", tid); 923 924 dispatchInsts(tid); 925 } else if (dispatchStatus[tid] == Unblocking) { 926 // Make sure that the skid buffer has something in it if the 927 // status is unblocking. 928 assert(!skidsEmpty()); 929 930 // If the status was unblocking, then instructions from the skid 931 // buffer were used. Remove those instructions and handle 932 // the rest of unblocking. 933 dispatchInsts(tid); 934 935 ++iewUnblockCycles; 936 937 if (validInstsFromRename()) { 938 // Add the current inputs to the skid buffer so they can be 939 // reprocessed when this stage unblocks. 940 skidInsert(tid); 941 } 942 943 unblock(tid); 944 } 945} 946 947template <class Impl> 948void 949DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 950{ 951 // Obtain instructions from skid buffer if unblocking, or queue from rename 952 // otherwise. 953 std::queue<DynInstPtr> &insts_to_dispatch = 954 dispatchStatus[tid] == Unblocking ? 955 skidBuffer[tid] : insts[tid]; 956 957 int insts_to_add = insts_to_dispatch.size(); 958 959 DynInstPtr inst; 960 bool add_to_iq = false; 961 int dis_num_inst = 0; 962 963 // Loop through the instructions, putting them in the instruction 964 // queue. 965 for ( ; dis_num_inst < insts_to_add && 966 dis_num_inst < dispatchWidth; 967 ++dis_num_inst) 968 { 969 inst = insts_to_dispatch.front(); 970 971 if (dispatchStatus[tid] == Unblocking) { 972 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 973 "buffer\n", tid); 974 } 975 976 // Make sure there's a valid instruction there. 977 assert(inst); 978 979 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 980 "IQ.\n", 981 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 982 983 // Be sure to mark these instructions as ready so that the 984 // commit stage can go ahead and execute them, and mark 985 // them as issued so the IQ doesn't reprocess them. 986 987 // Check for squashed instructions. 988 if (inst->isSquashed()) { 989 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 990 "not adding to IQ.\n", tid); 991 992 ++iewDispSquashedInsts; 993 994 insts_to_dispatch.pop(); 995 996 //Tell Rename That An Instruction has been processed 997 if (inst->isLoad()) { 998 toRename->iewInfo[tid].dispatchedToLQ++; 999 } 1000 if (inst->isStore()) { 1001 toRename->iewInfo[tid].dispatchedToSQ++; 1002 } 1003 1004 toRename->iewInfo[tid].dispatched++; 1005 1006 continue; 1007 } 1008 1009 // Check for full conditions. 1010 if (instQueue.isFull(tid)) { 1011 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1012 1013 // Call function to start blocking. 1014 block(tid); 1015 1016 // Set unblock to false. Special case where we are using 1017 // skidbuffer (unblocking) instructions but then we still 1018 // get full in the IQ. 1019 toRename->iewUnblock[tid] = false; 1020 1021 ++iewIQFullEvents; 1022 break; 1023 } 1024 1025 // Check LSQ if inst is LD/ST 1026 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1027 (inst->isStore() && ldstQueue.sqFull(tid))) { 1028 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1029 inst->isLoad() ? "LQ" : "SQ"); 1030 1031 // Call function to start blocking. 1032 block(tid); 1033 1034 // Set unblock to false. Special case where we are using 1035 // skidbuffer (unblocking) instructions but then we still 1036 // get full in the IQ. 1037 toRename->iewUnblock[tid] = false; 1038 1039 ++iewLSQFullEvents; 1040 break; 1041 } 1042 1043 // Otherwise issue the instruction just fine. 1044 if (inst->isLoad()) { 1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1046 "encountered, adding to LSQ.\n", tid); 1047 1048 // Reserve a spot in the load store queue for this 1049 // memory access. 1050 ldstQueue.insertLoad(inst); 1051 1052 ++iewDispLoadInsts; 1053 1054 add_to_iq = true; 1055 1056 toRename->iewInfo[tid].dispatchedToLQ++; 1057 } else if (inst->isStore()) { 1058 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1059 "encountered, adding to LSQ.\n", tid); 1060 1061 ldstQueue.insertStore(inst); 1062 1063 ++iewDispStoreInsts; 1064 1065 if (inst->isStoreConditional()) { 1066 // Store conditionals need to be set as "canCommit()" 1067 // so that commit can process them when they reach the 1068 // head of commit. 1069 // @todo: This is somewhat specific to Alpha. 1070 inst->setCanCommit(); 1071 instQueue.insertNonSpec(inst); 1072 add_to_iq = false; 1073 1074 ++iewDispNonSpecInsts; 1075 } else { 1076 add_to_iq = true; 1077 } 1078 1079 toRename->iewInfo[tid].dispatchedToSQ++; 1080 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1081 // Same as non-speculative stores. 1082 inst->setCanCommit(); 1083 instQueue.insertBarrier(inst); 1084 add_to_iq = false; 1085 } else if (inst->isNop()) { 1086 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1087 "skipping.\n", tid); 1088 1089 inst->setIssued(); 1090 inst->setExecuted(); 1091 inst->setCanCommit(); 1092 1093 instQueue.recordProducer(inst); 1094 1095 iewExecutedNop[tid]++; 1096 1097 add_to_iq = false; 1098 } else { 1099 assert(!inst->isExecuted()); 1100 add_to_iq = true; 1101 } 1102 1103 if (inst->isNonSpeculative()) { 1104 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1105 "encountered, skipping.\n", tid); 1106 1107 // Same as non-speculative stores. 1108 inst->setCanCommit(); 1109 1110 // Specifically insert it as nonspeculative. 1111 instQueue.insertNonSpec(inst); 1112 1113 ++iewDispNonSpecInsts; 1114 1115 add_to_iq = false; 1116 } 1117 1118 // If the instruction queue is not full, then add the 1119 // instruction. 1120 if (add_to_iq) { 1121 instQueue.insert(inst); 1122 } 1123 1124 insts_to_dispatch.pop(); 1125 1126 toRename->iewInfo[tid].dispatched++; 1127 1128 ++iewDispatchedInsts; 1129 1130#if TRACING_ON 1131 inst->dispatchTick = curTick() - inst->fetchTick; 1132#endif 1133 ppDispatch->notify(inst); 1134 } 1135 1136 if (!insts_to_dispatch.empty()) { 1137 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1138 block(tid); 1139 toRename->iewUnblock[tid] = false; 1140 } 1141 1142 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1143 dispatchStatus[tid] = Running; 1144 1145 updatedQueues = true; 1146 } 1147 1148 dis_num_inst = 0; 1149} 1150 1151template <class Impl> 1152void 1153DefaultIEW<Impl>::printAvailableInsts() 1154{ 1155 int inst = 0; 1156 1157 std::cout << "Available Instructions: "; 1158 1159 while (fromIssue->insts[inst]) { 1160 1161 if (inst%3==0) std::cout << "\n\t"; 1162 1163 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1164 << " TN: " << fromIssue->insts[inst]->threadNumber 1165 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1166 1167 inst++; 1168 1169 } 1170 1171 std::cout << "\n"; 1172} 1173 1174template <class Impl> 1175void 1176DefaultIEW<Impl>::executeInsts() 1177{ 1178 wbNumInst = 0; 1179 wbCycle = 0; 1180 1181 list<ThreadID>::iterator threads = activeThreads->begin(); 1182 list<ThreadID>::iterator end = activeThreads->end(); 1183 1184 while (threads != end) { 1185 ThreadID tid = *threads++; 1186 fetchRedirect[tid] = false; 1187 } 1188 1189 // Uncomment this if you want to see all available instructions. 1190 // @todo This doesn't actually work anymore, we should fix it. 1191// printAvailableInsts(); 1192 1193 // Execute/writeback any instructions that are available. 1194 int insts_to_execute = fromIssue->size; 1195 int inst_num = 0; 1196 for (; inst_num < insts_to_execute; 1197 ++inst_num) { 1198 1199 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1200 1201 DynInstPtr inst = instQueue.getInstToExecute(); 1202 1203 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1204 inst->pcState(), inst->threadNumber,inst->seqNum); 1205 1206 // Notify potential listeners that this instruction has started 1207 // executing 1208 ppExecute->notify(inst); 1209 1210 // Check if the instruction is squashed; if so then skip it 1211 if (inst->isSquashed()) { 1212 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1213 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1214 inst->seqNum); 1215 1216 // Consider this instruction executed so that commit can go 1217 // ahead and retire the instruction. 1218 inst->setExecuted(); 1219 1220 // Not sure if I should set this here or just let commit try to 1221 // commit any squashed instructions. I like the latter a bit more. 1222 inst->setCanCommit(); 1223 1224 ++iewExecSquashedInsts; 1225 1226 continue; 1227 } 1228 1229 Fault fault = NoFault; 1230 1231 // Execute instruction. 1232 // Note that if the instruction faults, it will be handled 1233 // at the commit stage. 1234 if (inst->isMemRef()) { 1235 DPRINTF(IEW, "Execute: Calculating address for memory " 1236 "reference.\n"); 1237 1238 // Tell the LDSTQ to execute this instruction (if it is a load). 1239 if (inst->isLoad()) { 1240 // Loads will mark themselves as executed, and their writeback 1241 // event adds the instruction to the queue to commit 1242 fault = ldstQueue.executeLoad(inst); 1243 1244 if (inst->isTranslationDelayed() && 1245 fault == NoFault) { 1246 // A hw page table walk is currently going on; the 1247 // instruction must be deferred. 1248 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1249 "load.\n"); 1250 instQueue.deferMemInst(inst); 1251 continue; 1252 } 1253 1254 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1255 inst->fault = NoFault; 1256 } 1257 } else if (inst->isStore()) { 1258 fault = ldstQueue.executeStore(inst); 1259 1260 if (inst->isTranslationDelayed() && 1261 fault == NoFault) { 1262 // A hw page table walk is currently going on; the 1263 // instruction must be deferred. 1264 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1265 "store.\n"); 1266 instQueue.deferMemInst(inst); 1267 continue; 1268 } 1269 1270 // If the store had a fault then it may not have a mem req 1271 if (fault != NoFault || !inst->readPredicate() || 1272 !inst->isStoreConditional()) { 1273 // If the instruction faulted, then we need to send it along 1274 // to commit without the instruction completing. 1275 // Send this instruction to commit, also make sure iew stage 1276 // realizes there is activity. 1277 inst->setExecuted(); 1278 instToCommit(inst); 1279 activityThisCycle(); 1280 } 1281 1282 // Store conditionals will mark themselves as 1283 // executed, and their writeback event will add the 1284 // instruction to the queue to commit. 1285 } else { 1286 panic("Unexpected memory type!\n"); 1287 } 1288 1289 } else { 1290 // If the instruction has already faulted, then skip executing it. 1291 // Such case can happen when it faulted during ITLB translation. 1292 // If we execute the instruction (even if it's a nop) the fault 1293 // will be replaced and we will lose it. 1294 if (inst->getFault() == NoFault) { 1295 inst->execute(); 1296 if (!inst->readPredicate()) 1297 inst->forwardOldRegs(); 1298 } 1299 1300 inst->setExecuted(); 1301 1302 instToCommit(inst); 1303 } 1304 1305 updateExeInstStats(inst); 1306 1307 // Check if branch prediction was correct, if not then we need 1308 // to tell commit to squash in flight instructions. Only 1309 // handle this if there hasn't already been something that 1310 // redirects fetch in this group of instructions. 1311 1312 // This probably needs to prioritize the redirects if a different 1313 // scheduler is used. Currently the scheduler schedules the oldest 1314 // instruction first, so the branch resolution order will be correct. 1315 ThreadID tid = inst->threadNumber; 1316 1317 if (!fetchRedirect[tid] || 1318 !toCommit->squash[tid] || 1319 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1320 1321 // Prevent testing for misprediction on load instructions, 1322 // that have not been executed. 1323 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1324 1325 if (inst->mispredicted() && !loadNotExecuted) { 1326 fetchRedirect[tid] = true; 1327 1328 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1329 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1330 inst->readPredTarg()); 1331 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1332 inst->pcState()); 1333 // If incorrect, then signal the ROB that it must be squashed. 1334 squashDueToBranch(inst, tid); 1335 1336 ppMispredict->notify(inst); 1337 1338 if (inst->readPredTaken()) { 1339 predictedTakenIncorrect++; 1340 } else { 1341 predictedNotTakenIncorrect++; 1342 } 1343 } else if (ldstQueue.violation(tid)) { 1344 assert(inst->isMemRef()); 1345 // If there was an ordering violation, then get the 1346 // DynInst that caused the violation. Note that this 1347 // clears the violation signal. 1348 DynInstPtr violator; 1349 violator = ldstQueue.getMemDepViolator(tid); 1350 1351 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1352 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1353 violator->pcState(), violator->seqNum, 1354 inst->pcState(), inst->seqNum, inst->physEffAddrLow); 1355 1356 fetchRedirect[tid] = true; 1357 1358 // Tell the instruction queue that a violation has occured. 1359 instQueue.violation(inst, violator); 1360 1361 // Squash. 1362 squashDueToMemOrder(violator, tid); 1363 1364 ++memOrderViolationEvents; 1365 } 1366 } else { 1367 // Reset any state associated with redirects that will not 1368 // be used. 1369 if (ldstQueue.violation(tid)) { 1370 assert(inst->isMemRef()); 1371 1372 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1373 1374 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1375 "%s, inst PC: %s. Addr is: %#x.\n", 1376 violator->pcState(), inst->pcState(), 1377 inst->physEffAddrLow); 1378 DPRINTF(IEW, "Violation will not be handled because " 1379 "already squashing\n"); 1380 1381 ++memOrderViolationEvents; 1382 } 1383 } 1384 } 1385 1386 // Update and record activity if we processed any instructions. 1387 if (inst_num) { 1388 if (exeStatus == Idle) { 1389 exeStatus = Running; 1390 } 1391 1392 updatedQueues = true; 1393 1394 cpu->activityThisCycle(); 1395 } 1396 1397 // Need to reset this in case a writeback event needs to write into the 1398 // iew queue. That way the writeback event will write into the correct 1399 // spot in the queue. 1400 wbNumInst = 0; 1401 1402} 1403 1404template <class Impl> 1405void 1406DefaultIEW<Impl>::writebackInsts() 1407{ 1408 // Loop through the head of the time buffer and wake any 1409 // dependents. These instructions are about to write back. Also 1410 // mark scoreboard that this instruction is finally complete. 1411 // Either have IEW have direct access to scoreboard, or have this 1412 // as part of backwards communication. 1413 for (int inst_num = 0; inst_num < wbWidth && 1414 toCommit->insts[inst_num]; inst_num++) { 1415 DynInstPtr inst = toCommit->insts[inst_num]; 1416 ThreadID tid = inst->threadNumber; 1417 1418 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1419 inst->seqNum, inst->pcState()); 1420 1421 iewInstsToCommit[tid]++; 1422 // Notify potential listeners that execution is complete for this 1423 // instruction. 1424 ppToCommit->notify(inst); 1425 1426 // Some instructions will be sent to commit without having 1427 // executed because they need commit to handle them. 1428 // E.g. Strictly ordered loads have not actually executed when they 1429 // are first sent to commit. Instead commit must tell the LSQ 1430 // when it's ready to execute the strictly ordered load. 1431 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1432 int dependents = instQueue.wakeDependents(inst); 1433 1434 for (int i = 0; i < inst->numDestRegs(); i++) { 1435 //mark as Ready 1436 DPRINTF(IEW,"Setting Destination Register %i\n", 1437 inst->renamedDestRegIdx(i)); 1438 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1439 } 1440 1441 if (dependents) { 1442 producerInst[tid]++; 1443 consumerInst[tid]+= dependents; 1444 } 1445 writebackCount[tid]++; 1446 } 1447 } 1448} 1449 1450template<class Impl> 1451void 1452DefaultIEW<Impl>::tick() 1453{ 1454 wbNumInst = 0; 1455 wbCycle = 0; 1456 1457 wroteToTimeBuffer = false; 1458 updatedQueues = false; 1459 1460 sortInsts(); 1461 1462 // Free function units marked as being freed this cycle. 1463 fuPool->processFreeUnits(); 1464 1465 list<ThreadID>::iterator threads = activeThreads->begin(); 1466 list<ThreadID>::iterator end = activeThreads->end(); 1467 1468 // Check stall and squash signals, dispatch any instructions. 1469 while (threads != end) { 1470 ThreadID tid = *threads++; 1471 1472 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1473 1474 checkSignalsAndUpdate(tid); 1475 dispatch(tid); 1476 } 1477 1478 if (exeStatus != Squashing) { 1479 executeInsts(); 1480 1481 writebackInsts(); 1482 1483 // Have the instruction queue try to schedule any ready instructions. 1484 // (In actuality, this scheduling is for instructions that will 1485 // be executed next cycle.) 1486 instQueue.scheduleReadyInsts(); 1487 1488 // Also should advance its own time buffers if the stage ran. 1489 // Not the best place for it, but this works (hopefully). 1490 issueToExecQueue.advance(); 1491 } 1492 1493 bool broadcast_free_entries = false; 1494 1495 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1496 exeStatus = Idle; 1497 updateLSQNextCycle = false; 1498 1499 broadcast_free_entries = true; 1500 } 1501 1502 // Writeback any stores using any leftover bandwidth. 1503 ldstQueue.writebackStores(); 1504 1505 // Check the committed load/store signals to see if there's a load 1506 // or store to commit. Also check if it's being told to execute a 1507 // nonspeculative instruction. 1508 // This is pretty inefficient... 1509 1510 threads = activeThreads->begin(); 1511 while (threads != end) { 1512 ThreadID tid = (*threads++); 1513 1514 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1515 1516 // Update structures based on instructions committed. 1517 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1518 !fromCommit->commitInfo[tid].squash && 1519 !fromCommit->commitInfo[tid].robSquashing) { 1520 1521 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1522 1523 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1524 1525 updateLSQNextCycle = true; 1526 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1527 } 1528 1529 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1530 1531 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1532 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1533 instQueue.replayMemInst( 1534 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1535 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1536 } else { 1537 instQueue.scheduleNonSpec( 1538 fromCommit->commitInfo[tid].nonSpecSeqNum); 1539 } 1540 } 1541 1542 if (broadcast_free_entries) { 1543 toFetch->iewInfo[tid].iqCount = 1544 instQueue.getCount(tid); 1545 toFetch->iewInfo[tid].ldstqCount = 1546 ldstQueue.getCount(tid); 1547 1548 toRename->iewInfo[tid].usedIQ = true; 1549 toRename->iewInfo[tid].freeIQEntries = 1550 instQueue.numFreeEntries(tid); 1551 toRename->iewInfo[tid].usedLSQ = true; 1552 1553 toRename->iewInfo[tid].freeLQEntries = 1554 ldstQueue.numFreeLoadEntries(tid); 1555 toRename->iewInfo[tid].freeSQEntries = 1556 ldstQueue.numFreeStoreEntries(tid); 1557 1558 wroteToTimeBuffer = true; 1559 } 1560 1561 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1562 tid, toRename->iewInfo[tid].dispatched); 1563 } 1564 1565 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1566 "LQ has %i free entries. SQ has %i free entries.\n", 1567 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1568 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1569 1570 updateStatus(); 1571 1572 if (wroteToTimeBuffer) { 1573 DPRINTF(Activity, "Activity this cycle.\n"); 1574 cpu->activityThisCycle(); 1575 } 1576} 1577 1578template <class Impl> 1579void 1580DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1581{ 1582 ThreadID tid = inst->threadNumber; 1583 1584 iewExecutedInsts++; 1585 1586#if TRACING_ON 1587 if (DTRACE(O3PipeView)) { 1588 inst->completeTick = curTick() - inst->fetchTick; 1589 } 1590#endif 1591 1592 // 1593 // Control operations 1594 // 1595 if (inst->isControl()) 1596 iewExecutedBranches[tid]++; 1597 1598 // 1599 // Memory operations 1600 // 1601 if (inst->isMemRef()) { 1602 iewExecutedRefs[tid]++; 1603 1604 if (inst->isLoad()) { 1605 iewExecLoadInsts[tid]++; 1606 } 1607 } 1608} 1609 1610template <class Impl> 1611void 1612DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1613{ 1614 ThreadID tid = inst->threadNumber; 1615 1616 if (!fetchRedirect[tid] || 1617 !toCommit->squash[tid] || 1618 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1619 1620 if (inst->mispredicted()) { 1621 fetchRedirect[tid] = true; 1622 1623 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1624 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1625 inst->predInstAddr(), inst->predNextInstAddr()); 1626 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1627 " NPC: %#x.\n", inst->nextInstAddr(), 1628 inst->nextInstAddr()); 1629 // If incorrect, then signal the ROB that it must be squashed. 1630 squashDueToBranch(inst, tid); 1631 1632 if (inst->readPredTaken()) { 1633 predictedTakenIncorrect++; 1634 } else { 1635 predictedNotTakenIncorrect++; 1636 } 1637 } 1638 } 1639} 1640 1641#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
|