82 _status = Active;
83 exeStatus = Running;
84 wbStatus = Idle;
85
86 // Setup wire to read instructions coming from issue.
87 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
88
89 // Instruction queue needs the queue between issue and execute.
90 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
91
92 for (ThreadID tid = 0; tid < numThreads; tid++) {
93 dispatchStatus[tid] = Running;
94 stalls[tid].commit = false;
95 fetchRedirect[tid] = false;
96 }
97
98 wbMax = wbWidth * params->wbDepth;
99
100 updateLSQNextCycle = false;
101
102 ableToIssue = true;
103
104 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
105}
106
107template <class Impl>
108std::string
109DefaultIEW<Impl>::name() const
110{
111 return cpu->name() + ".iew";
112}
113
114template <class Impl>
115void
116DefaultIEW<Impl>::regProbePoints()
117{
118 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
119 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
120}
121
122template <class Impl>
123void
124DefaultIEW<Impl>::regStats()
125{
126 using namespace Stats;
127
128 instQueue.regStats();
129 ldstQueue.regStats();
130
131 iewIdleCycles
132 .name(name() + ".iewIdleCycles")
133 .desc("Number of cycles IEW is idle");
134
135 iewSquashCycles
136 .name(name() + ".iewSquashCycles")
137 .desc("Number of cycles IEW is squashing");
138
139 iewBlockCycles
140 .name(name() + ".iewBlockCycles")
141 .desc("Number of cycles IEW is blocking");
142
143 iewUnblockCycles
144 .name(name() + ".iewUnblockCycles")
145 .desc("Number of cycles IEW is unblocking");
146
147 iewDispatchedInsts
148 .name(name() + ".iewDispatchedInsts")
149 .desc("Number of instructions dispatched to IQ");
150
151 iewDispSquashedInsts
152 .name(name() + ".iewDispSquashedInsts")
153 .desc("Number of squashed instructions skipped by dispatch");
154
155 iewDispLoadInsts
156 .name(name() + ".iewDispLoadInsts")
157 .desc("Number of dispatched load instructions");
158
159 iewDispStoreInsts
160 .name(name() + ".iewDispStoreInsts")
161 .desc("Number of dispatched store instructions");
162
163 iewDispNonSpecInsts
164 .name(name() + ".iewDispNonSpecInsts")
165 .desc("Number of dispatched non-speculative instructions");
166
167 iewIQFullEvents
168 .name(name() + ".iewIQFullEvents")
169 .desc("Number of times the IQ has become full, causing a stall");
170
171 iewLSQFullEvents
172 .name(name() + ".iewLSQFullEvents")
173 .desc("Number of times the LSQ has become full, causing a stall");
174
175 memOrderViolationEvents
176 .name(name() + ".memOrderViolationEvents")
177 .desc("Number of memory order violations");
178
179 predictedTakenIncorrect
180 .name(name() + ".predictedTakenIncorrect")
181 .desc("Number of branches that were predicted taken incorrectly");
182
183 predictedNotTakenIncorrect
184 .name(name() + ".predictedNotTakenIncorrect")
185 .desc("Number of branches that were predicted not taken incorrectly");
186
187 branchMispredicts
188 .name(name() + ".branchMispredicts")
189 .desc("Number of branch mispredicts detected at execute");
190
191 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
192
193 iewExecutedInsts
194 .name(name() + ".iewExecutedInsts")
195 .desc("Number of executed instructions");
196
197 iewExecLoadInsts
198 .init(cpu->numThreads)
199 .name(name() + ".iewExecLoadInsts")
200 .desc("Number of load instructions executed")
201 .flags(total);
202
203 iewExecSquashedInsts
204 .name(name() + ".iewExecSquashedInsts")
205 .desc("Number of squashed instructions skipped in execute");
206
207 iewExecutedSwp
208 .init(cpu->numThreads)
209 .name(name() + ".exec_swp")
210 .desc("number of swp insts executed")
211 .flags(total);
212
213 iewExecutedNop
214 .init(cpu->numThreads)
215 .name(name() + ".exec_nop")
216 .desc("number of nop insts executed")
217 .flags(total);
218
219 iewExecutedRefs
220 .init(cpu->numThreads)
221 .name(name() + ".exec_refs")
222 .desc("number of memory reference insts executed")
223 .flags(total);
224
225 iewExecutedBranches
226 .init(cpu->numThreads)
227 .name(name() + ".exec_branches")
228 .desc("Number of branches executed")
229 .flags(total);
230
231 iewExecStoreInsts
232 .name(name() + ".exec_stores")
233 .desc("Number of stores executed")
234 .flags(total);
235 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
236
237 iewExecRate
238 .name(name() + ".exec_rate")
239 .desc("Inst execution rate")
240 .flags(total);
241
242 iewExecRate = iewExecutedInsts / cpu->numCycles;
243
244 iewInstsToCommit
245 .init(cpu->numThreads)
246 .name(name() + ".wb_sent")
247 .desc("cumulative count of insts sent to commit")
248 .flags(total);
249
250 writebackCount
251 .init(cpu->numThreads)
252 .name(name() + ".wb_count")
253 .desc("cumulative count of insts written-back")
254 .flags(total);
255
256 producerInst
257 .init(cpu->numThreads)
258 .name(name() + ".wb_producers")
259 .desc("num instructions producing a value")
260 .flags(total);
261
262 consumerInst
263 .init(cpu->numThreads)
264 .name(name() + ".wb_consumers")
265 .desc("num instructions consuming a value")
266 .flags(total);
267
268 wbPenalized
269 .init(cpu->numThreads)
270 .name(name() + ".wb_penalized")
271 .desc("number of instrctions required to write to 'other' IQ")
272 .flags(total);
273
274 wbPenalizedRate
275 .name(name() + ".wb_penalized_rate")
276 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
277 .flags(total);
278
279 wbPenalizedRate = wbPenalized / writebackCount;
280
281 wbFanout
282 .name(name() + ".wb_fanout")
283 .desc("average fanout of values written-back")
284 .flags(total);
285
286 wbFanout = producerInst / consumerInst;
287
288 wbRate
289 .name(name() + ".wb_rate")
290 .desc("insts written-back per cycle")
291 .flags(total);
292 wbRate = writebackCount / cpu->numCycles;
293}
294
295template<class Impl>
296void
297DefaultIEW<Impl>::startupStage()
298{
299 for (ThreadID tid = 0; tid < numThreads; tid++) {
300 toRename->iewInfo[tid].usedIQ = true;
301 toRename->iewInfo[tid].freeIQEntries =
302 instQueue.numFreeEntries(tid);
303
304 toRename->iewInfo[tid].usedLSQ = true;
305 toRename->iewInfo[tid].freeLSQEntries =
306 ldstQueue.numFreeEntries(tid);
307 }
308
309 // Initialize the checker's dcache port here
310 if (cpu->checker) {
311 cpu->checker->setDcachePort(&cpu->getDataPort());
312 }
313
314 cpu->activateStage(O3CPU::IEWIdx);
315}
316
317template<class Impl>
318void
319DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
320{
321 timeBuffer = tb_ptr;
322
323 // Setup wire to read information from time buffer, from commit.
324 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
325
326 // Setup wire to write information back to previous stages.
327 toRename = timeBuffer->getWire(0);
328
329 toFetch = timeBuffer->getWire(0);
330
331 // Instruction queue also needs main time buffer.
332 instQueue.setTimeBuffer(tb_ptr);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
338{
339 renameQueue = rq_ptr;
340
341 // Setup wire to read information from rename queue.
342 fromRename = renameQueue->getWire(-renameToIEWDelay);
343}
344
345template<class Impl>
346void
347DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
348{
349 iewQueue = iq_ptr;
350
351 // Setup wire to write instructions to commit.
352 toCommit = iewQueue->getWire(0);
353}
354
355template<class Impl>
356void
357DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
358{
359 activeThreads = at_ptr;
360
361 ldstQueue.setActiveThreads(at_ptr);
362 instQueue.setActiveThreads(at_ptr);
363}
364
365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 scoreboard = sb_ptr;
370}
371
372template <class Impl>
373bool
374DefaultIEW<Impl>::isDrained() const
375{
376 bool drained(ldstQueue.isDrained());
377
378 for (ThreadID tid = 0; tid < numThreads; tid++) {
379 if (!insts[tid].empty()) {
380 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
381 drained = false;
382 }
383 if (!skidBuffer[tid].empty()) {
384 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
385 drained = false;
386 }
387 }
388
389 // Also check the FU pool as instructions are "stored" in FU
390 // completion events until they are done and not accounted for
391 // above
392 if (drained && !fuPool->isDrained()) {
393 DPRINTF(Drain, "FU pool still busy.\n");
394 drained = false;
395 }
396
397 return drained;
398}
399
400template <class Impl>
401void
402DefaultIEW<Impl>::drainSanityCheck() const
403{
404 assert(isDrained());
405
406 instQueue.drainSanityCheck();
407 ldstQueue.drainSanityCheck();
408}
409
410template <class Impl>
411void
412DefaultIEW<Impl>::takeOverFrom()
413{
414 // Reset all state.
415 _status = Active;
416 exeStatus = Running;
417 wbStatus = Idle;
418
419 instQueue.takeOverFrom();
420 ldstQueue.takeOverFrom();
421 fuPool->takeOverFrom();
422
423 startupStage();
424 cpu->activityThisCycle();
425
426 for (ThreadID tid = 0; tid < numThreads; tid++) {
427 dispatchStatus[tid] = Running;
428 stalls[tid].commit = false;
429 fetchRedirect[tid] = false;
430 }
431
432 updateLSQNextCycle = false;
433
434 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
435 issueToExecQueue.advance();
436 }
437}
438
439template<class Impl>
440void
441DefaultIEW<Impl>::squash(ThreadID tid)
442{
443 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
444
445 // Tell the IQ to start squashing.
446 instQueue.squash(tid);
447
448 // Tell the LDSTQ to start squashing.
449 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
450 updatedQueues = true;
451
452 // Clear the skid buffer in case it has any data in it.
453 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
454 tid, fromCommit->commitInfo[tid].doneSeqNum);
455
456 while (!skidBuffer[tid].empty()) {
457 if (skidBuffer[tid].front()->isLoad() ||
458 skidBuffer[tid].front()->isStore() ) {
459 toRename->iewInfo[tid].dispatchedToLSQ++;
460 }
461
462 toRename->iewInfo[tid].dispatched++;
463
464 skidBuffer[tid].pop();
465 }
466
467 emptyRenameInsts(tid);
468}
469
470template<class Impl>
471void
472DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
473{
474 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
475 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
476
477 if (toCommit->squash[tid] == false ||
478 inst->seqNum < toCommit->squashedSeqNum[tid]) {
479 toCommit->squash[tid] = true;
480 toCommit->squashedSeqNum[tid] = inst->seqNum;
481 toCommit->branchTaken[tid] = inst->pcState().branching();
482
483 TheISA::PCState pc = inst->pcState();
484 TheISA::advancePC(pc, inst->staticInst);
485
486 toCommit->pc[tid] = pc;
487 toCommit->mispredictInst[tid] = inst;
488 toCommit->includeSquashInst[tid] = false;
489
490 wroteToTimeBuffer = true;
491 }
492
493}
494
495template<class Impl>
496void
497DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
498{
499 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
500 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
501 // Need to include inst->seqNum in the following comparison to cover the
502 // corner case when a branch misprediction and a memory violation for the
503 // same instruction (e.g. load PC) are detected in the same cycle. In this
504 // case the memory violator should take precedence over the branch
505 // misprediction because it requires the violator itself to be included in
506 // the squash.
507 if (toCommit->squash[tid] == false ||
508 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
509 toCommit->squash[tid] = true;
510
511 toCommit->squashedSeqNum[tid] = inst->seqNum;
512 toCommit->pc[tid] = inst->pcState();
513 toCommit->mispredictInst[tid] = NULL;
514
515 // Must include the memory violator in the squash.
516 toCommit->includeSquashInst[tid] = true;
517
518 wroteToTimeBuffer = true;
519 }
520}
521
522template<class Impl>
523void
524DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
525{
526 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
527 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
528 if (toCommit->squash[tid] == false ||
529 inst->seqNum < toCommit->squashedSeqNum[tid]) {
530 toCommit->squash[tid] = true;
531
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->pc[tid] = inst->pcState();
534 toCommit->mispredictInst[tid] = NULL;
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;
542 }
543}
544
545template<class Impl>
546void
547DefaultIEW<Impl>::block(ThreadID tid)
548{
549 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
550
551 if (dispatchStatus[tid] != Blocked &&
552 dispatchStatus[tid] != Unblocking) {
553 toRename->iewBlock[tid] = true;
554 wroteToTimeBuffer = true;
555 }
556
557 // Add the current inputs to the skid buffer so they can be
558 // reprocessed when this stage unblocks.
559 skidInsert(tid);
560
561 dispatchStatus[tid] = Blocked;
562}
563
564template<class Impl>
565void
566DefaultIEW<Impl>::unblock(ThreadID tid)
567{
568 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
569 "buffer %u.\n",tid, tid);
570
571 // If the skid bufffer is empty, signal back to previous stages to unblock.
572 // Also switch status to running.
573 if (skidBuffer[tid].empty()) {
574 toRename->iewUnblock[tid] = true;
575 wroteToTimeBuffer = true;
576 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
577 dispatchStatus[tid] = Running;
578 }
579}
580
581template<class Impl>
582void
583DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
584{
585 instQueue.wakeDependents(inst);
586}
587
588template<class Impl>
589void
590DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
591{
592 instQueue.rescheduleMemInst(inst);
593}
594
595template<class Impl>
596void
597DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
598{
599 instQueue.replayMemInst(inst);
600}
601
602template<class Impl>
603void
604DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
605{
606 // This function should not be called after writebackInsts in a
607 // single cycle. That will cause problems with an instruction
608 // being added to the queue to commit without being processed by
609 // writebackInsts prior to being sent to commit.
610
611 // First check the time slot that this instruction will write
612 // to. If there are free write ports at the time, then go ahead
613 // and write the instruction to that time. If there are not,
614 // keep looking back to see where's the first time there's a
615 // free slot.
616 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
617 ++wbNumInst;
618 if (wbNumInst == wbWidth) {
619 ++wbCycle;
620 wbNumInst = 0;
621 }
622
623 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
624 }
625
626 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
627 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
628 // Add finished instruction to queue to commit.
629 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
630 (*iewQueue)[wbCycle].size++;
631}
632
633template <class Impl>
634unsigned
635DefaultIEW<Impl>::validInstsFromRename()
636{
637 unsigned inst_count = 0;
638
639 for (int i=0; i<fromRename->size; i++) {
640 if (!fromRename->insts[i]->isSquashed())
641 inst_count++;
642 }
643
644 return inst_count;
645}
646
647template<class Impl>
648void
649DefaultIEW<Impl>::skidInsert(ThreadID tid)
650{
651 DynInstPtr inst = NULL;
652
653 while (!insts[tid].empty()) {
654 inst = insts[tid].front();
655
656 insts[tid].pop();
657
658 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
659 "dispatch skidBuffer %i\n",tid, inst->seqNum,
660 inst->pcState(),tid);
661
662 skidBuffer[tid].push(inst);
663 }
664
665 assert(skidBuffer[tid].size() <= skidBufferMax &&
666 "Skidbuffer Exceeded Max Size");
667}
668
669template<class Impl>
670int
671DefaultIEW<Impl>::skidCount()
672{
673 int max=0;
674
675 list<ThreadID>::iterator threads = activeThreads->begin();
676 list<ThreadID>::iterator end = activeThreads->end();
677
678 while (threads != end) {
679 ThreadID tid = *threads++;
680 unsigned thread_count = skidBuffer[tid].size();
681 if (max < thread_count)
682 max = thread_count;
683 }
684
685 return max;
686}
687
688template<class Impl>
689bool
690DefaultIEW<Impl>::skidsEmpty()
691{
692 list<ThreadID>::iterator threads = activeThreads->begin();
693 list<ThreadID>::iterator end = activeThreads->end();
694
695 while (threads != end) {
696 ThreadID tid = *threads++;
697
698 if (!skidBuffer[tid].empty())
699 return false;
700 }
701
702 return true;
703}
704
705template <class Impl>
706void
707DefaultIEW<Impl>::updateStatus()
708{
709 bool any_unblocking = false;
710
711 list<ThreadID>::iterator threads = activeThreads->begin();
712 list<ThreadID>::iterator end = activeThreads->end();
713
714 while (threads != end) {
715 ThreadID tid = *threads++;
716
717 if (dispatchStatus[tid] == Unblocking) {
718 any_unblocking = true;
719 break;
720 }
721 }
722
723 // If there are no ready instructions waiting to be scheduled by the IQ,
724 // and there's no stores waiting to write back, and dispatch is not
725 // unblocking, then there is no internal activity for the IEW stage.
726 instQueue.intInstQueueReads++;
727 if (_status == Active && !instQueue.hasReadyInsts() &&
728 !ldstQueue.willWB() && !any_unblocking) {
729 DPRINTF(IEW, "IEW switching to idle\n");
730
731 deactivateStage();
732
733 _status = Inactive;
734 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
735 ldstQueue.willWB() ||
736 any_unblocking)) {
737 // Otherwise there is internal activity. Set to active.
738 DPRINTF(IEW, "IEW switching to active\n");
739
740 activateStage();
741
742 _status = Active;
743 }
744}
745
746template <class Impl>
747void
748DefaultIEW<Impl>::resetEntries()
749{
750 instQueue.resetEntries();
751 ldstQueue.resetEntries();
752}
753
754template <class Impl>
755void
756DefaultIEW<Impl>::readStallSignals(ThreadID tid)
757{
758 if (fromCommit->commitBlock[tid]) {
759 stalls[tid].commit = true;
760 }
761
762 if (fromCommit->commitUnblock[tid]) {
763 assert(stalls[tid].commit);
764 stalls[tid].commit = false;
765 }
766}
767
768template <class Impl>
769bool
770DefaultIEW<Impl>::checkStall(ThreadID tid)
771{
772 bool ret_val(false);
773
774 if (stalls[tid].commit) {
775 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
776 ret_val = true;
777 } else if (instQueue.isFull(tid)) {
778 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
779 ret_val = true;
780 } else if (ldstQueue.isFull(tid)) {
781 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
782
783 if (ldstQueue.numLoads(tid) > 0 ) {
784
785 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
786 tid,ldstQueue.getLoadHeadSeqNum(tid));
787 }
788
789 if (ldstQueue.numStores(tid) > 0) {
790
791 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
792 tid,ldstQueue.getStoreHeadSeqNum(tid));
793 }
794
795 ret_val = true;
796 } else if (ldstQueue.isStalled(tid)) {
797 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
798 ret_val = true;
799 }
800
801 return ret_val;
802}
803
804template <class Impl>
805void
806DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
807{
808 // Check if there's a squash signal, squash if there is
809 // Check stall signals, block if there is.
810 // If status was Blocked
811 // if so then go to unblocking
812 // If status was Squashing
813 // check if squashing is not high. Switch to running this cycle.
814
815 readStallSignals(tid);
816
817 if (fromCommit->commitInfo[tid].squash) {
818 squash(tid);
819
820 if (dispatchStatus[tid] == Blocked ||
821 dispatchStatus[tid] == Unblocking) {
822 toRename->iewUnblock[tid] = true;
823 wroteToTimeBuffer = true;
824 }
825
826 dispatchStatus[tid] = Squashing;
827 fetchRedirect[tid] = false;
828 return;
829 }
830
831 if (fromCommit->commitInfo[tid].robSquashing) {
832 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
833
834 dispatchStatus[tid] = Squashing;
835 emptyRenameInsts(tid);
836 wroteToTimeBuffer = true;
837 return;
838 }
839
840 if (checkStall(tid)) {
841 block(tid);
842 dispatchStatus[tid] = Blocked;
843 return;
844 }
845
846 if (dispatchStatus[tid] == Blocked) {
847 // Status from previous cycle was blocked, but there are no more stall
848 // conditions. Switch over to unblocking.
849 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
850 tid);
851
852 dispatchStatus[tid] = Unblocking;
853
854 unblock(tid);
855
856 return;
857 }
858
859 if (dispatchStatus[tid] == Squashing) {
860 // Switch status to running if rename isn't being told to block or
861 // squash this cycle.
862 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
863 tid);
864
865 dispatchStatus[tid] = Running;
866
867 return;
868 }
869}
870
871template <class Impl>
872void
873DefaultIEW<Impl>::sortInsts()
874{
875 int insts_from_rename = fromRename->size;
876#ifdef DEBUG
877 for (ThreadID tid = 0; tid < numThreads; tid++)
878 assert(insts[tid].empty());
879#endif
880 for (int i = 0; i < insts_from_rename; ++i) {
881 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
882 }
883}
884
885template <class Impl>
886void
887DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
888{
889 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
890
891 while (!insts[tid].empty()) {
892
893 if (insts[tid].front()->isLoad() ||
894 insts[tid].front()->isStore() ) {
895 toRename->iewInfo[tid].dispatchedToLSQ++;
896 }
897
898 toRename->iewInfo[tid].dispatched++;
899
900 insts[tid].pop();
901 }
902}
903
904template <class Impl>
905void
906DefaultIEW<Impl>::wakeCPU()
907{
908 cpu->wakeCPU();
909}
910
911template <class Impl>
912void
913DefaultIEW<Impl>::activityThisCycle()
914{
915 DPRINTF(Activity, "Activity this cycle.\n");
916 cpu->activityThisCycle();
917}
918
919template <class Impl>
920inline void
921DefaultIEW<Impl>::activateStage()
922{
923 DPRINTF(Activity, "Activating stage.\n");
924 cpu->activateStage(O3CPU::IEWIdx);
925}
926
927template <class Impl>
928inline void
929DefaultIEW<Impl>::deactivateStage()
930{
931 DPRINTF(Activity, "Deactivating stage.\n");
932 cpu->deactivateStage(O3CPU::IEWIdx);
933}
934
935template<class Impl>
936void
937DefaultIEW<Impl>::dispatch(ThreadID tid)
938{
939 // If status is Running or idle,
940 // call dispatchInsts()
941 // If status is Unblocking,
942 // buffer any instructions coming from rename
943 // continue trying to empty skid buffer
944 // check if stall conditions have passed
945
946 if (dispatchStatus[tid] == Blocked) {
947 ++iewBlockCycles;
948
949 } else if (dispatchStatus[tid] == Squashing) {
950 ++iewSquashCycles;
951 }
952
953 // Dispatch should try to dispatch as many instructions as its bandwidth
954 // will allow, as long as it is not currently blocked.
955 if (dispatchStatus[tid] == Running ||
956 dispatchStatus[tid] == Idle) {
957 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
958 "dispatch.\n", tid);
959
960 dispatchInsts(tid);
961 } else if (dispatchStatus[tid] == Unblocking) {
962 // Make sure that the skid buffer has something in it if the
963 // status is unblocking.
964 assert(!skidsEmpty());
965
966 // If the status was unblocking, then instructions from the skid
967 // buffer were used. Remove those instructions and handle
968 // the rest of unblocking.
969 dispatchInsts(tid);
970
971 ++iewUnblockCycles;
972
973 if (validInstsFromRename()) {
974 // Add the current inputs to the skid buffer so they can be
975 // reprocessed when this stage unblocks.
976 skidInsert(tid);
977 }
978
979 unblock(tid);
980 }
981}
982
983template <class Impl>
984void
985DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
986{
987 // Obtain instructions from skid buffer if unblocking, or queue from rename
988 // otherwise.
989 std::queue<DynInstPtr> &insts_to_dispatch =
990 dispatchStatus[tid] == Unblocking ?
991 skidBuffer[tid] : insts[tid];
992
993 int insts_to_add = insts_to_dispatch.size();
994
995 DynInstPtr inst;
996 bool add_to_iq = false;
997 int dis_num_inst = 0;
998
999 // Loop through the instructions, putting them in the instruction
1000 // queue.
1001 for ( ; dis_num_inst < insts_to_add &&
1002 dis_num_inst < dispatchWidth;
1003 ++dis_num_inst)
1004 {
1005 inst = insts_to_dispatch.front();
1006
1007 if (dispatchStatus[tid] == Unblocking) {
1008 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1009 "buffer\n", tid);
1010 }
1011
1012 // Make sure there's a valid instruction there.
1013 assert(inst);
1014
1015 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1016 "IQ.\n",
1017 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1018
1019 // Be sure to mark these instructions as ready so that the
1020 // commit stage can go ahead and execute them, and mark
1021 // them as issued so the IQ doesn't reprocess them.
1022
1023 // Check for squashed instructions.
1024 if (inst->isSquashed()) {
1025 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1026 "not adding to IQ.\n", tid);
1027
1028 ++iewDispSquashedInsts;
1029
1030 insts_to_dispatch.pop();
1031
1032 //Tell Rename That An Instruction has been processed
1033 if (inst->isLoad() || inst->isStore()) {
1034 toRename->iewInfo[tid].dispatchedToLSQ++;
1035 }
1036 toRename->iewInfo[tid].dispatched++;
1037
1038 continue;
1039 }
1040
1041 // Check for full conditions.
1042 if (instQueue.isFull(tid)) {
1043 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1044
1045 // Call function to start blocking.
1046 block(tid);
1047
1048 // Set unblock to false. Special case where we are using
1049 // skidbuffer (unblocking) instructions but then we still
1050 // get full in the IQ.
1051 toRename->iewUnblock[tid] = false;
1052
1053 ++iewIQFullEvents;
1054 break;
1055 } else if (ldstQueue.isFull(tid)) {
1056 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1057
1058 // Call function to start blocking.
1059 block(tid);
1060
1061 // Set unblock to false. Special case where we are using
1062 // skidbuffer (unblocking) instructions but then we still
1063 // get full in the IQ.
1064 toRename->iewUnblock[tid] = false;
1065
1066 ++iewLSQFullEvents;
1067 break;
1068 }
1069
1070 // Otherwise issue the instruction just fine.
1071 if (inst->isLoad()) {
1072 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1073 "encountered, adding to LSQ.\n", tid);
1074
1075 // Reserve a spot in the load store queue for this
1076 // memory access.
1077 ldstQueue.insertLoad(inst);
1078
1079 ++iewDispLoadInsts;
1080
1081 add_to_iq = true;
1082
1083 toRename->iewInfo[tid].dispatchedToLSQ++;
1084 } else if (inst->isStore()) {
1085 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1086 "encountered, adding to LSQ.\n", tid);
1087
1088 ldstQueue.insertStore(inst);
1089
1090 ++iewDispStoreInsts;
1091
1092 if (inst->isStoreConditional()) {
1093 // Store conditionals need to be set as "canCommit()"
1094 // so that commit can process them when they reach the
1095 // head of commit.
1096 // @todo: This is somewhat specific to Alpha.
1097 inst->setCanCommit();
1098 instQueue.insertNonSpec(inst);
1099 add_to_iq = false;
1100
1101 ++iewDispNonSpecInsts;
1102 } else {
1103 add_to_iq = true;
1104 }
1105
1106 toRename->iewInfo[tid].dispatchedToLSQ++;
1107 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1108 // Same as non-speculative stores.
1109 inst->setCanCommit();
1110 instQueue.insertBarrier(inst);
1111 add_to_iq = false;
1112 } else if (inst->isNop()) {
1113 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1114 "skipping.\n", tid);
1115
1116 inst->setIssued();
1117 inst->setExecuted();
1118 inst->setCanCommit();
1119
1120 instQueue.recordProducer(inst);
1121
1122 iewExecutedNop[tid]++;
1123
1124 add_to_iq = false;
1125 } else if (inst->isExecuted()) {
1126 assert(0 && "Instruction shouldn't be executed.\n");
1127 DPRINTF(IEW, "Issue: Executed branch encountered, "
1128 "skipping.\n");
1129
1130 inst->setIssued();
1131 inst->setCanCommit();
1132
1133 instQueue.recordProducer(inst);
1134
1135 add_to_iq = false;
1136 } else {
1137 add_to_iq = true;
1138 }
1139 if (inst->isNonSpeculative()) {
1140 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1141 "encountered, skipping.\n", tid);
1142
1143 // Same as non-speculative stores.
1144 inst->setCanCommit();
1145
1146 // Specifically insert it as nonspeculative.
1147 instQueue.insertNonSpec(inst);
1148
1149 ++iewDispNonSpecInsts;
1150
1151 add_to_iq = false;
1152 }
1153
1154 // If the instruction queue is not full, then add the
1155 // instruction.
1156 if (add_to_iq) {
1157 instQueue.insert(inst);
1158 }
1159
1160 insts_to_dispatch.pop();
1161
1162 toRename->iewInfo[tid].dispatched++;
1163
1164 ++iewDispatchedInsts;
1165
1166#if TRACING_ON
1167 inst->dispatchTick = curTick() - inst->fetchTick;
1168#endif
1169 ppDispatch->notify(inst);
1170 }
1171
1172 if (!insts_to_dispatch.empty()) {
1173 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1174 block(tid);
1175 toRename->iewUnblock[tid] = false;
1176 }
1177
1178 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1179 dispatchStatus[tid] = Running;
1180
1181 updatedQueues = true;
1182 }
1183
1184 dis_num_inst = 0;
1185}
1186
1187template <class Impl>
1188void
1189DefaultIEW<Impl>::printAvailableInsts()
1190{
1191 int inst = 0;
1192
1193 std::cout << "Available Instructions: ";
1194
1195 while (fromIssue->insts[inst]) {
1196
1197 if (inst%3==0) std::cout << "\n\t";
1198
1199 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1200 << " TN: " << fromIssue->insts[inst]->threadNumber
1201 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1202
1203 inst++;
1204
1205 }
1206
1207 std::cout << "\n";
1208}
1209
1210template <class Impl>
1211void
1212DefaultIEW<Impl>::executeInsts()
1213{
1214 wbNumInst = 0;
1215 wbCycle = 0;
1216
1217 list<ThreadID>::iterator threads = activeThreads->begin();
1218 list<ThreadID>::iterator end = activeThreads->end();
1219
1220 while (threads != end) {
1221 ThreadID tid = *threads++;
1222 fetchRedirect[tid] = false;
1223 }
1224
1225 // Uncomment this if you want to see all available instructions.
1226 // @todo This doesn't actually work anymore, we should fix it.
1227// printAvailableInsts();
1228
1229 // Execute/writeback any instructions that are available.
1230 int insts_to_execute = fromIssue->size;
1231 int inst_num = 0;
1232 for (; inst_num < insts_to_execute;
1233 ++inst_num) {
1234
1235 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1236
1237 DynInstPtr inst = instQueue.getInstToExecute();
1238
1239 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1240 inst->pcState(), inst->threadNumber,inst->seqNum);
1241
1242 // Check if the instruction is squashed; if so then skip it
1243 if (inst->isSquashed()) {
1244 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1245 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1246 inst->seqNum);
1247
1248 // Consider this instruction executed so that commit can go
1249 // ahead and retire the instruction.
1250 inst->setExecuted();
1251
1252 // Not sure if I should set this here or just let commit try to
1253 // commit any squashed instructions. I like the latter a bit more.
1254 inst->setCanCommit();
1255
1256 ++iewExecSquashedInsts;
1257
1258 decrWb(inst->seqNum);
1259 continue;
1260 }
1261
1262 Fault fault = NoFault;
1263
1264 // Execute instruction.
1265 // Note that if the instruction faults, it will be handled
1266 // at the commit stage.
1267 if (inst->isMemRef()) {
1268 DPRINTF(IEW, "Execute: Calculating address for memory "
1269 "reference.\n");
1270
1271 // Tell the LDSTQ to execute this instruction (if it is a load).
1272 if (inst->isLoad()) {
1273 // Loads will mark themselves as executed, and their writeback
1274 // event adds the instruction to the queue to commit
1275 fault = ldstQueue.executeLoad(inst);
1276
1277 if (inst->isTranslationDelayed() &&
1278 fault == NoFault) {
1279 // A hw page table walk is currently going on; the
1280 // instruction must be deferred.
1281 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1282 "load.\n");
1283 instQueue.deferMemInst(inst);
1284 continue;
1285 }
1286
1287 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1288 inst->fault = NoFault;
1289 }
1290 } else if (inst->isStore()) {
1291 fault = ldstQueue.executeStore(inst);
1292
1293 if (inst->isTranslationDelayed() &&
1294 fault == NoFault) {
1295 // A hw page table walk is currently going on; the
1296 // instruction must be deferred.
1297 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1298 "store.\n");
1299 instQueue.deferMemInst(inst);
1300 continue;
1301 }
1302
1303 // If the store had a fault then it may not have a mem req
1304 if (fault != NoFault || inst->readPredicate() == false ||
1305 !inst->isStoreConditional()) {
1306 // If the instruction faulted, then we need to send it along
1307 // to commit without the instruction completing.
1308 // Send this instruction to commit, also make sure iew stage
1309 // realizes there is activity.
1310 inst->setExecuted();
1311 instToCommit(inst);
1312 activityThisCycle();
1313 }
1314
1315 // Store conditionals will mark themselves as
1316 // executed, and their writeback event will add the
1317 // instruction to the queue to commit.
1318 } else {
1319 panic("Unexpected memory type!\n");
1320 }
1321
1322 } else {
1323 // If the instruction has already faulted, then skip executing it.
1324 // Such case can happen when it faulted during ITLB translation.
1325 // If we execute the instruction (even if it's a nop) the fault
1326 // will be replaced and we will lose it.
1327 if (inst->getFault() == NoFault) {
1328 inst->execute();
1329 if (inst->readPredicate() == false)
1330 inst->forwardOldRegs();
1331 }
1332
1333 inst->setExecuted();
1334
1335 instToCommit(inst);
1336 }
1337
1338 updateExeInstStats(inst);
1339
1340 // Check if branch prediction was correct, if not then we need
1341 // to tell commit to squash in flight instructions. Only
1342 // handle this if there hasn't already been something that
1343 // redirects fetch in this group of instructions.
1344
1345 // This probably needs to prioritize the redirects if a different
1346 // scheduler is used. Currently the scheduler schedules the oldest
1347 // instruction first, so the branch resolution order will be correct.
1348 ThreadID tid = inst->threadNumber;
1349
1350 if (!fetchRedirect[tid] ||
1351 !toCommit->squash[tid] ||
1352 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1353
1354 // Prevent testing for misprediction on load instructions,
1355 // that have not been executed.
1356 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1357
1358 if (inst->mispredicted() && !loadNotExecuted) {
1359 fetchRedirect[tid] = true;
1360
1361 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1362 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1363 inst->readPredTarg());
1364 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1365 inst->pcState());
1366 // If incorrect, then signal the ROB that it must be squashed.
1367 squashDueToBranch(inst, tid);
1368
1369 ppMispredict->notify(inst);
1370
1371 if (inst->readPredTaken()) {
1372 predictedTakenIncorrect++;
1373 } else {
1374 predictedNotTakenIncorrect++;
1375 }
1376 } else if (ldstQueue.violation(tid)) {
1377 assert(inst->isMemRef());
1378 // If there was an ordering violation, then get the
1379 // DynInst that caused the violation. Note that this
1380 // clears the violation signal.
1381 DynInstPtr violator;
1382 violator = ldstQueue.getMemDepViolator(tid);
1383
1384 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1385 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1386 violator->pcState(), violator->seqNum,
1387 inst->pcState(), inst->seqNum, inst->physEffAddr);
1388
1389 fetchRedirect[tid] = true;
1390
1391 // Tell the instruction queue that a violation has occured.
1392 instQueue.violation(inst, violator);
1393
1394 // Squash.
1395 squashDueToMemOrder(violator, tid);
1396
1397 ++memOrderViolationEvents;
1398 } else if (ldstQueue.loadBlocked(tid) &&
1399 !ldstQueue.isLoadBlockedHandled(tid)) {
1400 fetchRedirect[tid] = true;
1401
1402 DPRINTF(IEW, "Load operation couldn't execute because the "
1403 "memory system is blocked. PC: %s [sn:%lli]\n",
1404 inst->pcState(), inst->seqNum);
1405
1406 squashDueToMemBlocked(inst, tid);
1407 }
1408 } else {
1409 // Reset any state associated with redirects that will not
1410 // be used.
1411 if (ldstQueue.violation(tid)) {
1412 assert(inst->isMemRef());
1413
1414 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1415
1416 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1417 "%s, inst PC: %s. Addr is: %#x.\n",
1418 violator->pcState(), inst->pcState(),
1419 inst->physEffAddr);
1420 DPRINTF(IEW, "Violation will not be handled because "
1421 "already squashing\n");
1422
1423 ++memOrderViolationEvents;
1424 }
1425 if (ldstQueue.loadBlocked(tid) &&
1426 !ldstQueue.isLoadBlockedHandled(tid)) {
1427 DPRINTF(IEW, "Load operation couldn't execute because the "
1428 "memory system is blocked. PC: %s [sn:%lli]\n",
1429 inst->pcState(), inst->seqNum);
1430 DPRINTF(IEW, "Blocked load will not be handled because "
1431 "already squashing\n");
1432
1433 ldstQueue.setLoadBlockedHandled(tid);
1434 }
1435
1436 }
1437 }
1438
1439 // Update and record activity if we processed any instructions.
1440 if (inst_num) {
1441 if (exeStatus == Idle) {
1442 exeStatus = Running;
1443 }
1444
1445 updatedQueues = true;
1446
1447 cpu->activityThisCycle();
1448 }
1449
1450 // Need to reset this in case a writeback event needs to write into the
1451 // iew queue. That way the writeback event will write into the correct
1452 // spot in the queue.
1453 wbNumInst = 0;
1454
1455}
1456
1457template <class Impl>
1458void
1459DefaultIEW<Impl>::writebackInsts()
1460{
1461 // Loop through the head of the time buffer and wake any
1462 // dependents. These instructions are about to write back. Also
1463 // mark scoreboard that this instruction is finally complete.
1464 // Either have IEW have direct access to scoreboard, or have this
1465 // as part of backwards communication.
1466 for (int inst_num = 0; inst_num < wbWidth &&
1467 toCommit->insts[inst_num]; inst_num++) {
1468 DynInstPtr inst = toCommit->insts[inst_num];
1469 ThreadID tid = inst->threadNumber;
1470
1471 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1472 inst->seqNum, inst->pcState());
1473
1474 iewInstsToCommit[tid]++;
1475
1476 // Some instructions will be sent to commit without having
1477 // executed because they need commit to handle them.
1478 // E.g. Uncached loads have not actually executed when they
1479 // are first sent to commit. Instead commit must tell the LSQ
1480 // when it's ready to execute the uncached load.
1481 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1482 int dependents = instQueue.wakeDependents(inst);
1483
1484 for (int i = 0; i < inst->numDestRegs(); i++) {
1485 //mark as Ready
1486 DPRINTF(IEW,"Setting Destination Register %i\n",
1487 inst->renamedDestRegIdx(i));
1488 scoreboard->setReg(inst->renamedDestRegIdx(i));
1489 }
1490
1491 if (dependents) {
1492 producerInst[tid]++;
1493 consumerInst[tid]+= dependents;
1494 }
1495 writebackCount[tid]++;
1496 }
1497
1498 decrWb(inst->seqNum);
1499 }
1500}
1501
1502template<class Impl>
1503void
1504DefaultIEW<Impl>::tick()
1505{
1506 wbNumInst = 0;
1507 wbCycle = 0;
1508
1509 wroteToTimeBuffer = false;
1510 updatedQueues = false;
1511
1512 sortInsts();
1513
1514 // Free function units marked as being freed this cycle.
1515 fuPool->processFreeUnits();
1516
1517 list<ThreadID>::iterator threads = activeThreads->begin();
1518 list<ThreadID>::iterator end = activeThreads->end();
1519
1520 // Check stall and squash signals, dispatch any instructions.
1521 while (threads != end) {
1522 ThreadID tid = *threads++;
1523
1524 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1525
1526 checkSignalsAndUpdate(tid);
1527 dispatch(tid);
1528 }
1529
1530 if (exeStatus != Squashing) {
1531 executeInsts();
1532
1533 writebackInsts();
1534
1535 // Have the instruction queue try to schedule any ready instructions.
1536 // (In actuality, this scheduling is for instructions that will
1537 // be executed next cycle.)
1538 instQueue.scheduleReadyInsts();
1539
1540 // Also should advance its own time buffers if the stage ran.
1541 // Not the best place for it, but this works (hopefully).
1542 issueToExecQueue.advance();
1543 }
1544
1545 bool broadcast_free_entries = false;
1546
1547 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1548 exeStatus = Idle;
1549 updateLSQNextCycle = false;
1550
1551 broadcast_free_entries = true;
1552 }
1553
1554 // Writeback any stores using any leftover bandwidth.
1555 ldstQueue.writebackStores();
1556
1557 // Check the committed load/store signals to see if there's a load
1558 // or store to commit. Also check if it's being told to execute a
1559 // nonspeculative instruction.
1560 // This is pretty inefficient...
1561
1562 threads = activeThreads->begin();
1563 while (threads != end) {
1564 ThreadID tid = (*threads++);
1565
1566 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1567
1568 // Update structures based on instructions committed.
1569 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1570 !fromCommit->commitInfo[tid].squash &&
1571 !fromCommit->commitInfo[tid].robSquashing) {
1572
1573 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1574
1575 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1576
1577 updateLSQNextCycle = true;
1578 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1579 }
1580
1581 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1582
1583 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1584 if (fromCommit->commitInfo[tid].uncached) {
1585 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1586 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1587 } else {
1588 instQueue.scheduleNonSpec(
1589 fromCommit->commitInfo[tid].nonSpecSeqNum);
1590 }
1591 }
1592
1593 if (broadcast_free_entries) {
1594 toFetch->iewInfo[tid].iqCount =
1595 instQueue.getCount(tid);
1596 toFetch->iewInfo[tid].ldstqCount =
1597 ldstQueue.getCount(tid);
1598
1599 toRename->iewInfo[tid].usedIQ = true;
1600 toRename->iewInfo[tid].freeIQEntries =
1601 instQueue.numFreeEntries(tid);
1602 toRename->iewInfo[tid].usedLSQ = true;
1603 toRename->iewInfo[tid].freeLSQEntries =
1604 ldstQueue.numFreeEntries(tid);
1605
1606 wroteToTimeBuffer = true;
1607 }
1608
1609 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1610 tid, toRename->iewInfo[tid].dispatched);
1611 }
1612
1613 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1614 "LSQ has %i free entries.\n",
1615 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1616 ldstQueue.numFreeEntries());
1617
1618 updateStatus();
1619
1620 if (wroteToTimeBuffer) {
1621 DPRINTF(Activity, "Activity this cycle.\n");
1622 cpu->activityThisCycle();
1623 }
1624}
1625
1626template <class Impl>
1627void
1628DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1629{
1630 ThreadID tid = inst->threadNumber;
1631
1632 iewExecutedInsts++;
1633
1634#if TRACING_ON
1635 if (DTRACE(O3PipeView)) {
1636 inst->completeTick = curTick() - inst->fetchTick;
1637 }
1638#endif
1639
1640 //
1641 // Control operations
1642 //
1643 if (inst->isControl())
1644 iewExecutedBranches[tid]++;
1645
1646 //
1647 // Memory operations
1648 //
1649 if (inst->isMemRef()) {
1650 iewExecutedRefs[tid]++;
1651
1652 if (inst->isLoad()) {
1653 iewExecLoadInsts[tid]++;
1654 }
1655 }
1656}
1657
1658template <class Impl>
1659void
1660DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1661{
1662 ThreadID tid = inst->threadNumber;
1663
1664 if (!fetchRedirect[tid] ||
1665 !toCommit->squash[tid] ||
1666 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1667
1668 if (inst->mispredicted()) {
1669 fetchRedirect[tid] = true;
1670
1671 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1672 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1673 inst->predInstAddr(), inst->predNextInstAddr());
1674 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1675 " NPC: %#x.\n", inst->nextInstAddr(),
1676 inst->nextInstAddr());
1677 // If incorrect, then signal the ROB that it must be squashed.
1678 squashDueToBranch(inst, tid);
1679
1680 if (inst->readPredTaken()) {
1681 predictedTakenIncorrect++;
1682 } else {
1683 predictedNotTakenIncorrect++;
1684 }
1685 }
1686 }
1687}
1688
1689#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
| 95 _status = Active;
96 exeStatus = Running;
97 wbStatus = Idle;
98
99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
101
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
104
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
107 stalls[tid].commit = false;
108 fetchRedirect[tid] = false;
109 }
110
111 wbMax = wbWidth * params->wbDepth;
112
113 updateLSQNextCycle = false;
114
115 ableToIssue = true;
116
117 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
118}
119
120template <class Impl>
121std::string
122DefaultIEW<Impl>::name() const
123{
124 return cpu->name() + ".iew";
125}
126
127template <class Impl>
128void
129DefaultIEW<Impl>::regProbePoints()
130{
131 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
132 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
133}
134
135template <class Impl>
136void
137DefaultIEW<Impl>::regStats()
138{
139 using namespace Stats;
140
141 instQueue.regStats();
142 ldstQueue.regStats();
143
144 iewIdleCycles
145 .name(name() + ".iewIdleCycles")
146 .desc("Number of cycles IEW is idle");
147
148 iewSquashCycles
149 .name(name() + ".iewSquashCycles")
150 .desc("Number of cycles IEW is squashing");
151
152 iewBlockCycles
153 .name(name() + ".iewBlockCycles")
154 .desc("Number of cycles IEW is blocking");
155
156 iewUnblockCycles
157 .name(name() + ".iewUnblockCycles")
158 .desc("Number of cycles IEW is unblocking");
159
160 iewDispatchedInsts
161 .name(name() + ".iewDispatchedInsts")
162 .desc("Number of instructions dispatched to IQ");
163
164 iewDispSquashedInsts
165 .name(name() + ".iewDispSquashedInsts")
166 .desc("Number of squashed instructions skipped by dispatch");
167
168 iewDispLoadInsts
169 .name(name() + ".iewDispLoadInsts")
170 .desc("Number of dispatched load instructions");
171
172 iewDispStoreInsts
173 .name(name() + ".iewDispStoreInsts")
174 .desc("Number of dispatched store instructions");
175
176 iewDispNonSpecInsts
177 .name(name() + ".iewDispNonSpecInsts")
178 .desc("Number of dispatched non-speculative instructions");
179
180 iewIQFullEvents
181 .name(name() + ".iewIQFullEvents")
182 .desc("Number of times the IQ has become full, causing a stall");
183
184 iewLSQFullEvents
185 .name(name() + ".iewLSQFullEvents")
186 .desc("Number of times the LSQ has become full, causing a stall");
187
188 memOrderViolationEvents
189 .name(name() + ".memOrderViolationEvents")
190 .desc("Number of memory order violations");
191
192 predictedTakenIncorrect
193 .name(name() + ".predictedTakenIncorrect")
194 .desc("Number of branches that were predicted taken incorrectly");
195
196 predictedNotTakenIncorrect
197 .name(name() + ".predictedNotTakenIncorrect")
198 .desc("Number of branches that were predicted not taken incorrectly");
199
200 branchMispredicts
201 .name(name() + ".branchMispredicts")
202 .desc("Number of branch mispredicts detected at execute");
203
204 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
205
206 iewExecutedInsts
207 .name(name() + ".iewExecutedInsts")
208 .desc("Number of executed instructions");
209
210 iewExecLoadInsts
211 .init(cpu->numThreads)
212 .name(name() + ".iewExecLoadInsts")
213 .desc("Number of load instructions executed")
214 .flags(total);
215
216 iewExecSquashedInsts
217 .name(name() + ".iewExecSquashedInsts")
218 .desc("Number of squashed instructions skipped in execute");
219
220 iewExecutedSwp
221 .init(cpu->numThreads)
222 .name(name() + ".exec_swp")
223 .desc("number of swp insts executed")
224 .flags(total);
225
226 iewExecutedNop
227 .init(cpu->numThreads)
228 .name(name() + ".exec_nop")
229 .desc("number of nop insts executed")
230 .flags(total);
231
232 iewExecutedRefs
233 .init(cpu->numThreads)
234 .name(name() + ".exec_refs")
235 .desc("number of memory reference insts executed")
236 .flags(total);
237
238 iewExecutedBranches
239 .init(cpu->numThreads)
240 .name(name() + ".exec_branches")
241 .desc("Number of branches executed")
242 .flags(total);
243
244 iewExecStoreInsts
245 .name(name() + ".exec_stores")
246 .desc("Number of stores executed")
247 .flags(total);
248 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
249
250 iewExecRate
251 .name(name() + ".exec_rate")
252 .desc("Inst execution rate")
253 .flags(total);
254
255 iewExecRate = iewExecutedInsts / cpu->numCycles;
256
257 iewInstsToCommit
258 .init(cpu->numThreads)
259 .name(name() + ".wb_sent")
260 .desc("cumulative count of insts sent to commit")
261 .flags(total);
262
263 writebackCount
264 .init(cpu->numThreads)
265 .name(name() + ".wb_count")
266 .desc("cumulative count of insts written-back")
267 .flags(total);
268
269 producerInst
270 .init(cpu->numThreads)
271 .name(name() + ".wb_producers")
272 .desc("num instructions producing a value")
273 .flags(total);
274
275 consumerInst
276 .init(cpu->numThreads)
277 .name(name() + ".wb_consumers")
278 .desc("num instructions consuming a value")
279 .flags(total);
280
281 wbPenalized
282 .init(cpu->numThreads)
283 .name(name() + ".wb_penalized")
284 .desc("number of instrctions required to write to 'other' IQ")
285 .flags(total);
286
287 wbPenalizedRate
288 .name(name() + ".wb_penalized_rate")
289 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
290 .flags(total);
291
292 wbPenalizedRate = wbPenalized / writebackCount;
293
294 wbFanout
295 .name(name() + ".wb_fanout")
296 .desc("average fanout of values written-back")
297 .flags(total);
298
299 wbFanout = producerInst / consumerInst;
300
301 wbRate
302 .name(name() + ".wb_rate")
303 .desc("insts written-back per cycle")
304 .flags(total);
305 wbRate = writebackCount / cpu->numCycles;
306}
307
308template<class Impl>
309void
310DefaultIEW<Impl>::startupStage()
311{
312 for (ThreadID tid = 0; tid < numThreads; tid++) {
313 toRename->iewInfo[tid].usedIQ = true;
314 toRename->iewInfo[tid].freeIQEntries =
315 instQueue.numFreeEntries(tid);
316
317 toRename->iewInfo[tid].usedLSQ = true;
318 toRename->iewInfo[tid].freeLSQEntries =
319 ldstQueue.numFreeEntries(tid);
320 }
321
322 // Initialize the checker's dcache port here
323 if (cpu->checker) {
324 cpu->checker->setDcachePort(&cpu->getDataPort());
325 }
326
327 cpu->activateStage(O3CPU::IEWIdx);
328}
329
330template<class Impl>
331void
332DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
333{
334 timeBuffer = tb_ptr;
335
336 // Setup wire to read information from time buffer, from commit.
337 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
338
339 // Setup wire to write information back to previous stages.
340 toRename = timeBuffer->getWire(0);
341
342 toFetch = timeBuffer->getWire(0);
343
344 // Instruction queue also needs main time buffer.
345 instQueue.setTimeBuffer(tb_ptr);
346}
347
348template<class Impl>
349void
350DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
351{
352 renameQueue = rq_ptr;
353
354 // Setup wire to read information from rename queue.
355 fromRename = renameQueue->getWire(-renameToIEWDelay);
356}
357
358template<class Impl>
359void
360DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
361{
362 iewQueue = iq_ptr;
363
364 // Setup wire to write instructions to commit.
365 toCommit = iewQueue->getWire(0);
366}
367
368template<class Impl>
369void
370DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
371{
372 activeThreads = at_ptr;
373
374 ldstQueue.setActiveThreads(at_ptr);
375 instQueue.setActiveThreads(at_ptr);
376}
377
378template<class Impl>
379void
380DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
381{
382 scoreboard = sb_ptr;
383}
384
385template <class Impl>
386bool
387DefaultIEW<Impl>::isDrained() const
388{
389 bool drained(ldstQueue.isDrained());
390
391 for (ThreadID tid = 0; tid < numThreads; tid++) {
392 if (!insts[tid].empty()) {
393 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
394 drained = false;
395 }
396 if (!skidBuffer[tid].empty()) {
397 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
398 drained = false;
399 }
400 }
401
402 // Also check the FU pool as instructions are "stored" in FU
403 // completion events until they are done and not accounted for
404 // above
405 if (drained && !fuPool->isDrained()) {
406 DPRINTF(Drain, "FU pool still busy.\n");
407 drained = false;
408 }
409
410 return drained;
411}
412
413template <class Impl>
414void
415DefaultIEW<Impl>::drainSanityCheck() const
416{
417 assert(isDrained());
418
419 instQueue.drainSanityCheck();
420 ldstQueue.drainSanityCheck();
421}
422
423template <class Impl>
424void
425DefaultIEW<Impl>::takeOverFrom()
426{
427 // Reset all state.
428 _status = Active;
429 exeStatus = Running;
430 wbStatus = Idle;
431
432 instQueue.takeOverFrom();
433 ldstQueue.takeOverFrom();
434 fuPool->takeOverFrom();
435
436 startupStage();
437 cpu->activityThisCycle();
438
439 for (ThreadID tid = 0; tid < numThreads; tid++) {
440 dispatchStatus[tid] = Running;
441 stalls[tid].commit = false;
442 fetchRedirect[tid] = false;
443 }
444
445 updateLSQNextCycle = false;
446
447 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
448 issueToExecQueue.advance();
449 }
450}
451
452template<class Impl>
453void
454DefaultIEW<Impl>::squash(ThreadID tid)
455{
456 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
457
458 // Tell the IQ to start squashing.
459 instQueue.squash(tid);
460
461 // Tell the LDSTQ to start squashing.
462 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
463 updatedQueues = true;
464
465 // Clear the skid buffer in case it has any data in it.
466 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
467 tid, fromCommit->commitInfo[tid].doneSeqNum);
468
469 while (!skidBuffer[tid].empty()) {
470 if (skidBuffer[tid].front()->isLoad() ||
471 skidBuffer[tid].front()->isStore() ) {
472 toRename->iewInfo[tid].dispatchedToLSQ++;
473 }
474
475 toRename->iewInfo[tid].dispatched++;
476
477 skidBuffer[tid].pop();
478 }
479
480 emptyRenameInsts(tid);
481}
482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
486{
487 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
488 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489
490 if (toCommit->squash[tid] == false ||
491 inst->seqNum < toCommit->squashedSeqNum[tid]) {
492 toCommit->squash[tid] = true;
493 toCommit->squashedSeqNum[tid] = inst->seqNum;
494 toCommit->branchTaken[tid] = inst->pcState().branching();
495
496 TheISA::PCState pc = inst->pcState();
497 TheISA::advancePC(pc, inst->staticInst);
498
499 toCommit->pc[tid] = pc;
500 toCommit->mispredictInst[tid] = inst;
501 toCommit->includeSquashInst[tid] = false;
502
503 wroteToTimeBuffer = true;
504 }
505
506}
507
508template<class Impl>
509void
510DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
511{
512 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
513 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
514 // Need to include inst->seqNum in the following comparison to cover the
515 // corner case when a branch misprediction and a memory violation for the
516 // same instruction (e.g. load PC) are detected in the same cycle. In this
517 // case the memory violator should take precedence over the branch
518 // misprediction because it requires the violator itself to be included in
519 // the squash.
520 if (toCommit->squash[tid] == false ||
521 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
522 toCommit->squash[tid] = true;
523
524 toCommit->squashedSeqNum[tid] = inst->seqNum;
525 toCommit->pc[tid] = inst->pcState();
526 toCommit->mispredictInst[tid] = NULL;
527
528 // Must include the memory violator in the squash.
529 toCommit->includeSquashInst[tid] = true;
530
531 wroteToTimeBuffer = true;
532 }
533}
534
535template<class Impl>
536void
537DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
538{
539 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
540 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
541 if (toCommit->squash[tid] == false ||
542 inst->seqNum < toCommit->squashedSeqNum[tid]) {
543 toCommit->squash[tid] = true;
544
545 toCommit->squashedSeqNum[tid] = inst->seqNum;
546 toCommit->pc[tid] = inst->pcState();
547 toCommit->mispredictInst[tid] = NULL;
548
549 // Must include the broadcasted SN in the squash.
550 toCommit->includeSquashInst[tid] = true;
551
552 ldstQueue.setLoadBlockedHandled(tid);
553
554 wroteToTimeBuffer = true;
555 }
556}
557
558template<class Impl>
559void
560DefaultIEW<Impl>::block(ThreadID tid)
561{
562 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
563
564 if (dispatchStatus[tid] != Blocked &&
565 dispatchStatus[tid] != Unblocking) {
566 toRename->iewBlock[tid] = true;
567 wroteToTimeBuffer = true;
568 }
569
570 // Add the current inputs to the skid buffer so they can be
571 // reprocessed when this stage unblocks.
572 skidInsert(tid);
573
574 dispatchStatus[tid] = Blocked;
575}
576
577template<class Impl>
578void
579DefaultIEW<Impl>::unblock(ThreadID tid)
580{
581 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
582 "buffer %u.\n",tid, tid);
583
584 // If the skid bufffer is empty, signal back to previous stages to unblock.
585 // Also switch status to running.
586 if (skidBuffer[tid].empty()) {
587 toRename->iewUnblock[tid] = true;
588 wroteToTimeBuffer = true;
589 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
590 dispatchStatus[tid] = Running;
591 }
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
597{
598 instQueue.wakeDependents(inst);
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
604{
605 instQueue.rescheduleMemInst(inst);
606}
607
608template<class Impl>
609void
610DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
611{
612 instQueue.replayMemInst(inst);
613}
614
615template<class Impl>
616void
617DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
618{
619 // This function should not be called after writebackInsts in a
620 // single cycle. That will cause problems with an instruction
621 // being added to the queue to commit without being processed by
622 // writebackInsts prior to being sent to commit.
623
624 // First check the time slot that this instruction will write
625 // to. If there are free write ports at the time, then go ahead
626 // and write the instruction to that time. If there are not,
627 // keep looking back to see where's the first time there's a
628 // free slot.
629 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
630 ++wbNumInst;
631 if (wbNumInst == wbWidth) {
632 ++wbCycle;
633 wbNumInst = 0;
634 }
635
636 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
637 }
638
639 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
640 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
641 // Add finished instruction to queue to commit.
642 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
643 (*iewQueue)[wbCycle].size++;
644}
645
646template <class Impl>
647unsigned
648DefaultIEW<Impl>::validInstsFromRename()
649{
650 unsigned inst_count = 0;
651
652 for (int i=0; i<fromRename->size; i++) {
653 if (!fromRename->insts[i]->isSquashed())
654 inst_count++;
655 }
656
657 return inst_count;
658}
659
660template<class Impl>
661void
662DefaultIEW<Impl>::skidInsert(ThreadID tid)
663{
664 DynInstPtr inst = NULL;
665
666 while (!insts[tid].empty()) {
667 inst = insts[tid].front();
668
669 insts[tid].pop();
670
671 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
672 "dispatch skidBuffer %i\n",tid, inst->seqNum,
673 inst->pcState(),tid);
674
675 skidBuffer[tid].push(inst);
676 }
677
678 assert(skidBuffer[tid].size() <= skidBufferMax &&
679 "Skidbuffer Exceeded Max Size");
680}
681
682template<class Impl>
683int
684DefaultIEW<Impl>::skidCount()
685{
686 int max=0;
687
688 list<ThreadID>::iterator threads = activeThreads->begin();
689 list<ThreadID>::iterator end = activeThreads->end();
690
691 while (threads != end) {
692 ThreadID tid = *threads++;
693 unsigned thread_count = skidBuffer[tid].size();
694 if (max < thread_count)
695 max = thread_count;
696 }
697
698 return max;
699}
700
701template<class Impl>
702bool
703DefaultIEW<Impl>::skidsEmpty()
704{
705 list<ThreadID>::iterator threads = activeThreads->begin();
706 list<ThreadID>::iterator end = activeThreads->end();
707
708 while (threads != end) {
709 ThreadID tid = *threads++;
710
711 if (!skidBuffer[tid].empty())
712 return false;
713 }
714
715 return true;
716}
717
718template <class Impl>
719void
720DefaultIEW<Impl>::updateStatus()
721{
722 bool any_unblocking = false;
723
724 list<ThreadID>::iterator threads = activeThreads->begin();
725 list<ThreadID>::iterator end = activeThreads->end();
726
727 while (threads != end) {
728 ThreadID tid = *threads++;
729
730 if (dispatchStatus[tid] == Unblocking) {
731 any_unblocking = true;
732 break;
733 }
734 }
735
736 // If there are no ready instructions waiting to be scheduled by the IQ,
737 // and there's no stores waiting to write back, and dispatch is not
738 // unblocking, then there is no internal activity for the IEW stage.
739 instQueue.intInstQueueReads++;
740 if (_status == Active && !instQueue.hasReadyInsts() &&
741 !ldstQueue.willWB() && !any_unblocking) {
742 DPRINTF(IEW, "IEW switching to idle\n");
743
744 deactivateStage();
745
746 _status = Inactive;
747 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
748 ldstQueue.willWB() ||
749 any_unblocking)) {
750 // Otherwise there is internal activity. Set to active.
751 DPRINTF(IEW, "IEW switching to active\n");
752
753 activateStage();
754
755 _status = Active;
756 }
757}
758
759template <class Impl>
760void
761DefaultIEW<Impl>::resetEntries()
762{
763 instQueue.resetEntries();
764 ldstQueue.resetEntries();
765}
766
767template <class Impl>
768void
769DefaultIEW<Impl>::readStallSignals(ThreadID tid)
770{
771 if (fromCommit->commitBlock[tid]) {
772 stalls[tid].commit = true;
773 }
774
775 if (fromCommit->commitUnblock[tid]) {
776 assert(stalls[tid].commit);
777 stalls[tid].commit = false;
778 }
779}
780
781template <class Impl>
782bool
783DefaultIEW<Impl>::checkStall(ThreadID tid)
784{
785 bool ret_val(false);
786
787 if (stalls[tid].commit) {
788 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
789 ret_val = true;
790 } else if (instQueue.isFull(tid)) {
791 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
792 ret_val = true;
793 } else if (ldstQueue.isFull(tid)) {
794 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
795
796 if (ldstQueue.numLoads(tid) > 0 ) {
797
798 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
799 tid,ldstQueue.getLoadHeadSeqNum(tid));
800 }
801
802 if (ldstQueue.numStores(tid) > 0) {
803
804 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
805 tid,ldstQueue.getStoreHeadSeqNum(tid));
806 }
807
808 ret_val = true;
809 } else if (ldstQueue.isStalled(tid)) {
810 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
811 ret_val = true;
812 }
813
814 return ret_val;
815}
816
817template <class Impl>
818void
819DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
820{
821 // Check if there's a squash signal, squash if there is
822 // Check stall signals, block if there is.
823 // If status was Blocked
824 // if so then go to unblocking
825 // If status was Squashing
826 // check if squashing is not high. Switch to running this cycle.
827
828 readStallSignals(tid);
829
830 if (fromCommit->commitInfo[tid].squash) {
831 squash(tid);
832
833 if (dispatchStatus[tid] == Blocked ||
834 dispatchStatus[tid] == Unblocking) {
835 toRename->iewUnblock[tid] = true;
836 wroteToTimeBuffer = true;
837 }
838
839 dispatchStatus[tid] = Squashing;
840 fetchRedirect[tid] = false;
841 return;
842 }
843
844 if (fromCommit->commitInfo[tid].robSquashing) {
845 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
846
847 dispatchStatus[tid] = Squashing;
848 emptyRenameInsts(tid);
849 wroteToTimeBuffer = true;
850 return;
851 }
852
853 if (checkStall(tid)) {
854 block(tid);
855 dispatchStatus[tid] = Blocked;
856 return;
857 }
858
859 if (dispatchStatus[tid] == Blocked) {
860 // Status from previous cycle was blocked, but there are no more stall
861 // conditions. Switch over to unblocking.
862 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
863 tid);
864
865 dispatchStatus[tid] = Unblocking;
866
867 unblock(tid);
868
869 return;
870 }
871
872 if (dispatchStatus[tid] == Squashing) {
873 // Switch status to running if rename isn't being told to block or
874 // squash this cycle.
875 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
876 tid);
877
878 dispatchStatus[tid] = Running;
879
880 return;
881 }
882}
883
884template <class Impl>
885void
886DefaultIEW<Impl>::sortInsts()
887{
888 int insts_from_rename = fromRename->size;
889#ifdef DEBUG
890 for (ThreadID tid = 0; tid < numThreads; tid++)
891 assert(insts[tid].empty());
892#endif
893 for (int i = 0; i < insts_from_rename; ++i) {
894 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
895 }
896}
897
898template <class Impl>
899void
900DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
901{
902 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
903
904 while (!insts[tid].empty()) {
905
906 if (insts[tid].front()->isLoad() ||
907 insts[tid].front()->isStore() ) {
908 toRename->iewInfo[tid].dispatchedToLSQ++;
909 }
910
911 toRename->iewInfo[tid].dispatched++;
912
913 insts[tid].pop();
914 }
915}
916
917template <class Impl>
918void
919DefaultIEW<Impl>::wakeCPU()
920{
921 cpu->wakeCPU();
922}
923
924template <class Impl>
925void
926DefaultIEW<Impl>::activityThisCycle()
927{
928 DPRINTF(Activity, "Activity this cycle.\n");
929 cpu->activityThisCycle();
930}
931
932template <class Impl>
933inline void
934DefaultIEW<Impl>::activateStage()
935{
936 DPRINTF(Activity, "Activating stage.\n");
937 cpu->activateStage(O3CPU::IEWIdx);
938}
939
940template <class Impl>
941inline void
942DefaultIEW<Impl>::deactivateStage()
943{
944 DPRINTF(Activity, "Deactivating stage.\n");
945 cpu->deactivateStage(O3CPU::IEWIdx);
946}
947
948template<class Impl>
949void
950DefaultIEW<Impl>::dispatch(ThreadID tid)
951{
952 // If status is Running or idle,
953 // call dispatchInsts()
954 // If status is Unblocking,
955 // buffer any instructions coming from rename
956 // continue trying to empty skid buffer
957 // check if stall conditions have passed
958
959 if (dispatchStatus[tid] == Blocked) {
960 ++iewBlockCycles;
961
962 } else if (dispatchStatus[tid] == Squashing) {
963 ++iewSquashCycles;
964 }
965
966 // Dispatch should try to dispatch as many instructions as its bandwidth
967 // will allow, as long as it is not currently blocked.
968 if (dispatchStatus[tid] == Running ||
969 dispatchStatus[tid] == Idle) {
970 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
971 "dispatch.\n", tid);
972
973 dispatchInsts(tid);
974 } else if (dispatchStatus[tid] == Unblocking) {
975 // Make sure that the skid buffer has something in it if the
976 // status is unblocking.
977 assert(!skidsEmpty());
978
979 // If the status was unblocking, then instructions from the skid
980 // buffer were used. Remove those instructions and handle
981 // the rest of unblocking.
982 dispatchInsts(tid);
983
984 ++iewUnblockCycles;
985
986 if (validInstsFromRename()) {
987 // Add the current inputs to the skid buffer so they can be
988 // reprocessed when this stage unblocks.
989 skidInsert(tid);
990 }
991
992 unblock(tid);
993 }
994}
995
996template <class Impl>
997void
998DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
999{
1000 // Obtain instructions from skid buffer if unblocking, or queue from rename
1001 // otherwise.
1002 std::queue<DynInstPtr> &insts_to_dispatch =
1003 dispatchStatus[tid] == Unblocking ?
1004 skidBuffer[tid] : insts[tid];
1005
1006 int insts_to_add = insts_to_dispatch.size();
1007
1008 DynInstPtr inst;
1009 bool add_to_iq = false;
1010 int dis_num_inst = 0;
1011
1012 // Loop through the instructions, putting them in the instruction
1013 // queue.
1014 for ( ; dis_num_inst < insts_to_add &&
1015 dis_num_inst < dispatchWidth;
1016 ++dis_num_inst)
1017 {
1018 inst = insts_to_dispatch.front();
1019
1020 if (dispatchStatus[tid] == Unblocking) {
1021 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1022 "buffer\n", tid);
1023 }
1024
1025 // Make sure there's a valid instruction there.
1026 assert(inst);
1027
1028 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1029 "IQ.\n",
1030 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1031
1032 // Be sure to mark these instructions as ready so that the
1033 // commit stage can go ahead and execute them, and mark
1034 // them as issued so the IQ doesn't reprocess them.
1035
1036 // Check for squashed instructions.
1037 if (inst->isSquashed()) {
1038 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1039 "not adding to IQ.\n", tid);
1040
1041 ++iewDispSquashedInsts;
1042
1043 insts_to_dispatch.pop();
1044
1045 //Tell Rename That An Instruction has been processed
1046 if (inst->isLoad() || inst->isStore()) {
1047 toRename->iewInfo[tid].dispatchedToLSQ++;
1048 }
1049 toRename->iewInfo[tid].dispatched++;
1050
1051 continue;
1052 }
1053
1054 // Check for full conditions.
1055 if (instQueue.isFull(tid)) {
1056 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1057
1058 // Call function to start blocking.
1059 block(tid);
1060
1061 // Set unblock to false. Special case where we are using
1062 // skidbuffer (unblocking) instructions but then we still
1063 // get full in the IQ.
1064 toRename->iewUnblock[tid] = false;
1065
1066 ++iewIQFullEvents;
1067 break;
1068 } else if (ldstQueue.isFull(tid)) {
1069 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1070
1071 // Call function to start blocking.
1072 block(tid);
1073
1074 // Set unblock to false. Special case where we are using
1075 // skidbuffer (unblocking) instructions but then we still
1076 // get full in the IQ.
1077 toRename->iewUnblock[tid] = false;
1078
1079 ++iewLSQFullEvents;
1080 break;
1081 }
1082
1083 // Otherwise issue the instruction just fine.
1084 if (inst->isLoad()) {
1085 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1086 "encountered, adding to LSQ.\n", tid);
1087
1088 // Reserve a spot in the load store queue for this
1089 // memory access.
1090 ldstQueue.insertLoad(inst);
1091
1092 ++iewDispLoadInsts;
1093
1094 add_to_iq = true;
1095
1096 toRename->iewInfo[tid].dispatchedToLSQ++;
1097 } else if (inst->isStore()) {
1098 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1099 "encountered, adding to LSQ.\n", tid);
1100
1101 ldstQueue.insertStore(inst);
1102
1103 ++iewDispStoreInsts;
1104
1105 if (inst->isStoreConditional()) {
1106 // Store conditionals need to be set as "canCommit()"
1107 // so that commit can process them when they reach the
1108 // head of commit.
1109 // @todo: This is somewhat specific to Alpha.
1110 inst->setCanCommit();
1111 instQueue.insertNonSpec(inst);
1112 add_to_iq = false;
1113
1114 ++iewDispNonSpecInsts;
1115 } else {
1116 add_to_iq = true;
1117 }
1118
1119 toRename->iewInfo[tid].dispatchedToLSQ++;
1120 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1121 // Same as non-speculative stores.
1122 inst->setCanCommit();
1123 instQueue.insertBarrier(inst);
1124 add_to_iq = false;
1125 } else if (inst->isNop()) {
1126 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1127 "skipping.\n", tid);
1128
1129 inst->setIssued();
1130 inst->setExecuted();
1131 inst->setCanCommit();
1132
1133 instQueue.recordProducer(inst);
1134
1135 iewExecutedNop[tid]++;
1136
1137 add_to_iq = false;
1138 } else if (inst->isExecuted()) {
1139 assert(0 && "Instruction shouldn't be executed.\n");
1140 DPRINTF(IEW, "Issue: Executed branch encountered, "
1141 "skipping.\n");
1142
1143 inst->setIssued();
1144 inst->setCanCommit();
1145
1146 instQueue.recordProducer(inst);
1147
1148 add_to_iq = false;
1149 } else {
1150 add_to_iq = true;
1151 }
1152 if (inst->isNonSpeculative()) {
1153 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1154 "encountered, skipping.\n", tid);
1155
1156 // Same as non-speculative stores.
1157 inst->setCanCommit();
1158
1159 // Specifically insert it as nonspeculative.
1160 instQueue.insertNonSpec(inst);
1161
1162 ++iewDispNonSpecInsts;
1163
1164 add_to_iq = false;
1165 }
1166
1167 // If the instruction queue is not full, then add the
1168 // instruction.
1169 if (add_to_iq) {
1170 instQueue.insert(inst);
1171 }
1172
1173 insts_to_dispatch.pop();
1174
1175 toRename->iewInfo[tid].dispatched++;
1176
1177 ++iewDispatchedInsts;
1178
1179#if TRACING_ON
1180 inst->dispatchTick = curTick() - inst->fetchTick;
1181#endif
1182 ppDispatch->notify(inst);
1183 }
1184
1185 if (!insts_to_dispatch.empty()) {
1186 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1187 block(tid);
1188 toRename->iewUnblock[tid] = false;
1189 }
1190
1191 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1192 dispatchStatus[tid] = Running;
1193
1194 updatedQueues = true;
1195 }
1196
1197 dis_num_inst = 0;
1198}
1199
1200template <class Impl>
1201void
1202DefaultIEW<Impl>::printAvailableInsts()
1203{
1204 int inst = 0;
1205
1206 std::cout << "Available Instructions: ";
1207
1208 while (fromIssue->insts[inst]) {
1209
1210 if (inst%3==0) std::cout << "\n\t";
1211
1212 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1213 << " TN: " << fromIssue->insts[inst]->threadNumber
1214 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1215
1216 inst++;
1217
1218 }
1219
1220 std::cout << "\n";
1221}
1222
1223template <class Impl>
1224void
1225DefaultIEW<Impl>::executeInsts()
1226{
1227 wbNumInst = 0;
1228 wbCycle = 0;
1229
1230 list<ThreadID>::iterator threads = activeThreads->begin();
1231 list<ThreadID>::iterator end = activeThreads->end();
1232
1233 while (threads != end) {
1234 ThreadID tid = *threads++;
1235 fetchRedirect[tid] = false;
1236 }
1237
1238 // Uncomment this if you want to see all available instructions.
1239 // @todo This doesn't actually work anymore, we should fix it.
1240// printAvailableInsts();
1241
1242 // Execute/writeback any instructions that are available.
1243 int insts_to_execute = fromIssue->size;
1244 int inst_num = 0;
1245 for (; inst_num < insts_to_execute;
1246 ++inst_num) {
1247
1248 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1249
1250 DynInstPtr inst = instQueue.getInstToExecute();
1251
1252 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1253 inst->pcState(), inst->threadNumber,inst->seqNum);
1254
1255 // Check if the instruction is squashed; if so then skip it
1256 if (inst->isSquashed()) {
1257 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1258 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1259 inst->seqNum);
1260
1261 // Consider this instruction executed so that commit can go
1262 // ahead and retire the instruction.
1263 inst->setExecuted();
1264
1265 // Not sure if I should set this here or just let commit try to
1266 // commit any squashed instructions. I like the latter a bit more.
1267 inst->setCanCommit();
1268
1269 ++iewExecSquashedInsts;
1270
1271 decrWb(inst->seqNum);
1272 continue;
1273 }
1274
1275 Fault fault = NoFault;
1276
1277 // Execute instruction.
1278 // Note that if the instruction faults, it will be handled
1279 // at the commit stage.
1280 if (inst->isMemRef()) {
1281 DPRINTF(IEW, "Execute: Calculating address for memory "
1282 "reference.\n");
1283
1284 // Tell the LDSTQ to execute this instruction (if it is a load).
1285 if (inst->isLoad()) {
1286 // Loads will mark themselves as executed, and their writeback
1287 // event adds the instruction to the queue to commit
1288 fault = ldstQueue.executeLoad(inst);
1289
1290 if (inst->isTranslationDelayed() &&
1291 fault == NoFault) {
1292 // A hw page table walk is currently going on; the
1293 // instruction must be deferred.
1294 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1295 "load.\n");
1296 instQueue.deferMemInst(inst);
1297 continue;
1298 }
1299
1300 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1301 inst->fault = NoFault;
1302 }
1303 } else if (inst->isStore()) {
1304 fault = ldstQueue.executeStore(inst);
1305
1306 if (inst->isTranslationDelayed() &&
1307 fault == NoFault) {
1308 // A hw page table walk is currently going on; the
1309 // instruction must be deferred.
1310 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1311 "store.\n");
1312 instQueue.deferMemInst(inst);
1313 continue;
1314 }
1315
1316 // If the store had a fault then it may not have a mem req
1317 if (fault != NoFault || inst->readPredicate() == false ||
1318 !inst->isStoreConditional()) {
1319 // If the instruction faulted, then we need to send it along
1320 // to commit without the instruction completing.
1321 // Send this instruction to commit, also make sure iew stage
1322 // realizes there is activity.
1323 inst->setExecuted();
1324 instToCommit(inst);
1325 activityThisCycle();
1326 }
1327
1328 // Store conditionals will mark themselves as
1329 // executed, and their writeback event will add the
1330 // instruction to the queue to commit.
1331 } else {
1332 panic("Unexpected memory type!\n");
1333 }
1334
1335 } else {
1336 // If the instruction has already faulted, then skip executing it.
1337 // Such case can happen when it faulted during ITLB translation.
1338 // If we execute the instruction (even if it's a nop) the fault
1339 // will be replaced and we will lose it.
1340 if (inst->getFault() == NoFault) {
1341 inst->execute();
1342 if (inst->readPredicate() == false)
1343 inst->forwardOldRegs();
1344 }
1345
1346 inst->setExecuted();
1347
1348 instToCommit(inst);
1349 }
1350
1351 updateExeInstStats(inst);
1352
1353 // Check if branch prediction was correct, if not then we need
1354 // to tell commit to squash in flight instructions. Only
1355 // handle this if there hasn't already been something that
1356 // redirects fetch in this group of instructions.
1357
1358 // This probably needs to prioritize the redirects if a different
1359 // scheduler is used. Currently the scheduler schedules the oldest
1360 // instruction first, so the branch resolution order will be correct.
1361 ThreadID tid = inst->threadNumber;
1362
1363 if (!fetchRedirect[tid] ||
1364 !toCommit->squash[tid] ||
1365 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1366
1367 // Prevent testing for misprediction on load instructions,
1368 // that have not been executed.
1369 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1370
1371 if (inst->mispredicted() && !loadNotExecuted) {
1372 fetchRedirect[tid] = true;
1373
1374 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1375 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1376 inst->readPredTarg());
1377 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1378 inst->pcState());
1379 // If incorrect, then signal the ROB that it must be squashed.
1380 squashDueToBranch(inst, tid);
1381
1382 ppMispredict->notify(inst);
1383
1384 if (inst->readPredTaken()) {
1385 predictedTakenIncorrect++;
1386 } else {
1387 predictedNotTakenIncorrect++;
1388 }
1389 } else if (ldstQueue.violation(tid)) {
1390 assert(inst->isMemRef());
1391 // If there was an ordering violation, then get the
1392 // DynInst that caused the violation. Note that this
1393 // clears the violation signal.
1394 DynInstPtr violator;
1395 violator = ldstQueue.getMemDepViolator(tid);
1396
1397 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1398 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1399 violator->pcState(), violator->seqNum,
1400 inst->pcState(), inst->seqNum, inst->physEffAddr);
1401
1402 fetchRedirect[tid] = true;
1403
1404 // Tell the instruction queue that a violation has occured.
1405 instQueue.violation(inst, violator);
1406
1407 // Squash.
1408 squashDueToMemOrder(violator, tid);
1409
1410 ++memOrderViolationEvents;
1411 } else if (ldstQueue.loadBlocked(tid) &&
1412 !ldstQueue.isLoadBlockedHandled(tid)) {
1413 fetchRedirect[tid] = true;
1414
1415 DPRINTF(IEW, "Load operation couldn't execute because the "
1416 "memory system is blocked. PC: %s [sn:%lli]\n",
1417 inst->pcState(), inst->seqNum);
1418
1419 squashDueToMemBlocked(inst, tid);
1420 }
1421 } else {
1422 // Reset any state associated with redirects that will not
1423 // be used.
1424 if (ldstQueue.violation(tid)) {
1425 assert(inst->isMemRef());
1426
1427 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1428
1429 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1430 "%s, inst PC: %s. Addr is: %#x.\n",
1431 violator->pcState(), inst->pcState(),
1432 inst->physEffAddr);
1433 DPRINTF(IEW, "Violation will not be handled because "
1434 "already squashing\n");
1435
1436 ++memOrderViolationEvents;
1437 }
1438 if (ldstQueue.loadBlocked(tid) &&
1439 !ldstQueue.isLoadBlockedHandled(tid)) {
1440 DPRINTF(IEW, "Load operation couldn't execute because the "
1441 "memory system is blocked. PC: %s [sn:%lli]\n",
1442 inst->pcState(), inst->seqNum);
1443 DPRINTF(IEW, "Blocked load will not be handled because "
1444 "already squashing\n");
1445
1446 ldstQueue.setLoadBlockedHandled(tid);
1447 }
1448
1449 }
1450 }
1451
1452 // Update and record activity if we processed any instructions.
1453 if (inst_num) {
1454 if (exeStatus == Idle) {
1455 exeStatus = Running;
1456 }
1457
1458 updatedQueues = true;
1459
1460 cpu->activityThisCycle();
1461 }
1462
1463 // Need to reset this in case a writeback event needs to write into the
1464 // iew queue. That way the writeback event will write into the correct
1465 // spot in the queue.
1466 wbNumInst = 0;
1467
1468}
1469
1470template <class Impl>
1471void
1472DefaultIEW<Impl>::writebackInsts()
1473{
1474 // Loop through the head of the time buffer and wake any
1475 // dependents. These instructions are about to write back. Also
1476 // mark scoreboard that this instruction is finally complete.
1477 // Either have IEW have direct access to scoreboard, or have this
1478 // as part of backwards communication.
1479 for (int inst_num = 0; inst_num < wbWidth &&
1480 toCommit->insts[inst_num]; inst_num++) {
1481 DynInstPtr inst = toCommit->insts[inst_num];
1482 ThreadID tid = inst->threadNumber;
1483
1484 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1485 inst->seqNum, inst->pcState());
1486
1487 iewInstsToCommit[tid]++;
1488
1489 // Some instructions will be sent to commit without having
1490 // executed because they need commit to handle them.
1491 // E.g. Uncached loads have not actually executed when they
1492 // are first sent to commit. Instead commit must tell the LSQ
1493 // when it's ready to execute the uncached load.
1494 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1495 int dependents = instQueue.wakeDependents(inst);
1496
1497 for (int i = 0; i < inst->numDestRegs(); i++) {
1498 //mark as Ready
1499 DPRINTF(IEW,"Setting Destination Register %i\n",
1500 inst->renamedDestRegIdx(i));
1501 scoreboard->setReg(inst->renamedDestRegIdx(i));
1502 }
1503
1504 if (dependents) {
1505 producerInst[tid]++;
1506 consumerInst[tid]+= dependents;
1507 }
1508 writebackCount[tid]++;
1509 }
1510
1511 decrWb(inst->seqNum);
1512 }
1513}
1514
1515template<class Impl>
1516void
1517DefaultIEW<Impl>::tick()
1518{
1519 wbNumInst = 0;
1520 wbCycle = 0;
1521
1522 wroteToTimeBuffer = false;
1523 updatedQueues = false;
1524
1525 sortInsts();
1526
1527 // Free function units marked as being freed this cycle.
1528 fuPool->processFreeUnits();
1529
1530 list<ThreadID>::iterator threads = activeThreads->begin();
1531 list<ThreadID>::iterator end = activeThreads->end();
1532
1533 // Check stall and squash signals, dispatch any instructions.
1534 while (threads != end) {
1535 ThreadID tid = *threads++;
1536
1537 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1538
1539 checkSignalsAndUpdate(tid);
1540 dispatch(tid);
1541 }
1542
1543 if (exeStatus != Squashing) {
1544 executeInsts();
1545
1546 writebackInsts();
1547
1548 // Have the instruction queue try to schedule any ready instructions.
1549 // (In actuality, this scheduling is for instructions that will
1550 // be executed next cycle.)
1551 instQueue.scheduleReadyInsts();
1552
1553 // Also should advance its own time buffers if the stage ran.
1554 // Not the best place for it, but this works (hopefully).
1555 issueToExecQueue.advance();
1556 }
1557
1558 bool broadcast_free_entries = false;
1559
1560 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1561 exeStatus = Idle;
1562 updateLSQNextCycle = false;
1563
1564 broadcast_free_entries = true;
1565 }
1566
1567 // Writeback any stores using any leftover bandwidth.
1568 ldstQueue.writebackStores();
1569
1570 // Check the committed load/store signals to see if there's a load
1571 // or store to commit. Also check if it's being told to execute a
1572 // nonspeculative instruction.
1573 // This is pretty inefficient...
1574
1575 threads = activeThreads->begin();
1576 while (threads != end) {
1577 ThreadID tid = (*threads++);
1578
1579 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1580
1581 // Update structures based on instructions committed.
1582 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1583 !fromCommit->commitInfo[tid].squash &&
1584 !fromCommit->commitInfo[tid].robSquashing) {
1585
1586 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1587
1588 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1589
1590 updateLSQNextCycle = true;
1591 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1592 }
1593
1594 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1595
1596 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1597 if (fromCommit->commitInfo[tid].uncached) {
1598 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1599 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1600 } else {
1601 instQueue.scheduleNonSpec(
1602 fromCommit->commitInfo[tid].nonSpecSeqNum);
1603 }
1604 }
1605
1606 if (broadcast_free_entries) {
1607 toFetch->iewInfo[tid].iqCount =
1608 instQueue.getCount(tid);
1609 toFetch->iewInfo[tid].ldstqCount =
1610 ldstQueue.getCount(tid);
1611
1612 toRename->iewInfo[tid].usedIQ = true;
1613 toRename->iewInfo[tid].freeIQEntries =
1614 instQueue.numFreeEntries(tid);
1615 toRename->iewInfo[tid].usedLSQ = true;
1616 toRename->iewInfo[tid].freeLSQEntries =
1617 ldstQueue.numFreeEntries(tid);
1618
1619 wroteToTimeBuffer = true;
1620 }
1621
1622 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1623 tid, toRename->iewInfo[tid].dispatched);
1624 }
1625
1626 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1627 "LSQ has %i free entries.\n",
1628 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1629 ldstQueue.numFreeEntries());
1630
1631 updateStatus();
1632
1633 if (wroteToTimeBuffer) {
1634 DPRINTF(Activity, "Activity this cycle.\n");
1635 cpu->activityThisCycle();
1636 }
1637}
1638
1639template <class Impl>
1640void
1641DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1642{
1643 ThreadID tid = inst->threadNumber;
1644
1645 iewExecutedInsts++;
1646
1647#if TRACING_ON
1648 if (DTRACE(O3PipeView)) {
1649 inst->completeTick = curTick() - inst->fetchTick;
1650 }
1651#endif
1652
1653 //
1654 // Control operations
1655 //
1656 if (inst->isControl())
1657 iewExecutedBranches[tid]++;
1658
1659 //
1660 // Memory operations
1661 //
1662 if (inst->isMemRef()) {
1663 iewExecutedRefs[tid]++;
1664
1665 if (inst->isLoad()) {
1666 iewExecLoadInsts[tid]++;
1667 }
1668 }
1669}
1670
1671template <class Impl>
1672void
1673DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1674{
1675 ThreadID tid = inst->threadNumber;
1676
1677 if (!fetchRedirect[tid] ||
1678 !toCommit->squash[tid] ||
1679 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1680
1681 if (inst->mispredicted()) {
1682 fetchRedirect[tid] = true;
1683
1684 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1685 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1686 inst->predInstAddr(), inst->predNextInstAddr());
1687 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1688 " NPC: %#x.\n", inst->nextInstAddr(),
1689 inst->nextInstAddr());
1690 // If incorrect, then signal the ROB that it must be squashed.
1691 squashDueToBranch(inst, tid);
1692
1693 if (inst->readPredTaken()) {
1694 predictedTakenIncorrect++;
1695 } else {
1696 predictedNotTakenIncorrect++;
1697 }
1698 }
1699 }
1700}
1701
1702#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
|